JPH0590848A - Current mirror circuit in semiconductor integrated circuit - Google Patents

Current mirror circuit in semiconductor integrated circuit

Info

Publication number
JPH0590848A
JPH0590848A JP3276147A JP27614791A JPH0590848A JP H0590848 A JPH0590848 A JP H0590848A JP 3276147 A JP3276147 A JP 3276147A JP 27614791 A JP27614791 A JP 27614791A JP H0590848 A JPH0590848 A JP H0590848A
Authority
JP
Japan
Prior art keywords
transistor
collector
current mirror
base
mirror circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3276147A
Other languages
Japanese (ja)
Inventor
Giichi Shimizu
義一 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3276147A priority Critical patent/JPH0590848A/en
Publication of JPH0590848A publication Critical patent/JPH0590848A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a real current mirror circuit that cannot be affected by the operating condition and the deviation in the manufacturing process for semiconductor integrated circuits. CONSTITUTION:In order to make the potential between the base and the collector of transistor 1Q1 equal to the potential between the base and the collector of transistor 2Q2, a chain of diodes 4 is inserted between transistor 1Q1 and the power supply. Accordingly, a current mirror circuit can be realized that is not affected by the potential at the collector of transistor 1Q1 and the deviation in the manufacturing process of semiconductors.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路に関し、
特にカレントミラー回路を有する半導体集積回路に関す
る。
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a current mirror circuit.

【0002】[0002]

【従来の技術】従来のカレントミラー回路は、図3に示
すように一対にトランジスタQ1 ,Q2 を有し、Q2
コレクタとベースをショートし、抵抗3によってQ2
コレクタ電流を決定し、一方のトランジスタ(Q1 )の
ベースエミッタ電位がQ2 のベースエミッタ電位と同一
であればQ1 のコレクタ電流はQ2 のコレクタ電流に等
しいという、トランジスタ動作の基本式(整流式)を応
用して、Q1 のコレクタ電流をQ2 のコレクタ電流と同
一にする、即ちカレントミラー回路として、動作させる
ものである。
2. Description of the Related Art A conventional current mirror circuit has a pair of transistors Q 1 and Q 2 as shown in FIG. 3, a collector and a base of Q 2 are short-circuited, and a resistor 3 determines a collector current of Q 2. However, if the base-emitter potential of one transistor (Q 1 ) is the same as the base-emitter potential of Q 2 , the collector current of Q 1 is equal to the collector current of Q 2. By applying it, the collector current of Q 1 is made the same as the collector current of Q 2 , that is, it is operated as a current mirror circuit.

【0003】[0003]

【発明が解決しようとする課題】この従来のカレントミ
ラー回路では、理論上トランジスタQ1 とQ2 のコレク
タ電流は同一になるはずであるが、実際にはQ1 とQ2
のコレクタ・ベース間電位が大幅に異なるため(Q1
コレクタ・ベース間電位はVCC−VB ,Q2 のコレクタ
・ベース間電位はOV )アーリー効果により、Q1 のコ
レクタ電流はQ2のコレクタ電流とは等しくならず、必
らずQ1 のコレクタ電流の方が多いという現象が生ず
る。さらに悪いことには、半導体集積回路装置の製造上
のバラツキにより、Q1 ,Q2 のエミッタ深さが大幅に
変わり従ってベース領域に拡がる空乏層の幅が変わり、
1 のコレクタ電流とQ2 のコレクタ電流の比は、製造
ロット毎に大幅にバラツクという致命的問題点があっ
た。
In this conventional current mirror circuit, the collector currents of the transistors Q 1 and Q 2 should theoretically be the same, but in reality they are Q 1 and Q 2.
Since the collector-base potential of Q 1 is significantly different (the collector-base potential of Q 1 is V CC -V B , the collector-base potential of Q 2 is O V ), the collector current of Q 1 is Q The collector current of Q 1 is not equal to the collector current of 2 , and the phenomenon that the collector current of Q 1 is inevitably occurs. To make matters worse, variations in the manufacturing of the semiconductor integrated circuit device significantly change the emitter depths of Q 1 and Q 2 , and thus the width of the depletion layer extending to the base region.
There is a fatal problem that the ratio of the collector current of Q 1 and the collector current of Q 2 greatly varies from manufacturing lot to manufacturing lot.

【0004】[0004]

【課題を解決するための手段】本発明の半導体集積回路
の中のカレントミラー回路は第1のトランジスタと第2
のトランジスタのベース電極同士が接続され、かつ第2
のトランジスタのコレクタ電極とベース電極は互いに接
続され、その端子は抵抗を通して電源端子に接続され、
かつ第1のトランジスタのコレクタ端子は1個以上のダ
イオードチェーンを介して電源端子に接続されている。
A current mirror circuit in a semiconductor integrated circuit according to the present invention comprises a first transistor and a second transistor.
The base electrodes of the transistors are connected to each other, and the second
The collector electrode and the base electrode of the transistor of are connected to each other, and the terminal is connected to the power supply terminal through the resistor,
Moreover, the collector terminal of the first transistor is connected to the power supply terminal via one or more diode chains.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0006】図1は、本発明の一実施例としてNPNト
ランジスタの場合を示す回路図である。ベース共通のペ
アトランジスタ1(Q1 )と2(Q2 )を有し、Q2
コレクタとベースは短絡され、電源端子に接続し、Q1
とQ2 のベース同士は短絡され、かつ、Q1 とQ2 のエ
ミッタ同士も短絡されている。さらに、Q2 のコレクタ
には、電流設定用の抵抗3が接続されている。Q1のコ
レクタには1個以上のダイオードチェーンが接続されて
いて、ダイオード1個の順方向電圧をVF ,ダイオード
の個数をn,電源電圧をVCC,Q1 ,Q2 のベース電位
をVB としたとき、VB =VCC−n・VF が成立つよう
にして正確なカレントミラー回路が実現される。
FIG. 1 is a circuit diagram showing a case of an NPN transistor as an embodiment of the present invention. A common base transistor pair 1 (Q 1) 2 and (Q 2), the collector and base of Q 2 is shorted, and connected to the power supply terminal, Q 1
The bases of Q 2 and Q 2 are short-circuited, and the emitters of Q 1 and Q 2 are also short-circuited. Further, a current setting resistor 3 is connected to the collector of Q 2 . One or more diode chains are connected to the collector of Q 1 , and the forward voltage of one diode is V F , the number of diodes is n, the power supply voltage is V CC , the base potentials of Q 1 and Q 2 are When V B is set, V B = V CC −n · V F is satisfied, and an accurate current mirror circuit is realized.

【0007】図2は、本発明の第2の実施例であり、N
PNトランジスタのかわりにPNPトランジスタを使用
した場合を示す。
FIG. 2 shows a second embodiment of the present invention, N
The case where a PNP transistor is used instead of the PN transistor is shown.

【0008】[0008]

【発明の効果】以上説明したように、本発明は、カレン
トミラー回路のペアトランジスタのコレクタ・ベース間
電位を同一にすることにより、アーリー効果の影響を排
除し、半導体装置の製造上のバラツキにも影響されず、
真のカレントミラー回路を実現できるという効果を有す
る。
As described above, according to the present invention, by making the collector-base potentials of the pair transistors of the current mirror circuit the same, the influence of the Early effect is eliminated, and variations in the manufacturing of semiconductor devices are eliminated. Is not affected,
This has the effect of realizing a true current mirror circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

【図2】本発明の第2の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the present invention.

【図3】従来のカレントミラー回路の一例である。FIG. 3 is an example of a conventional current mirror circuit.

【符号の説明】[Explanation of symbols]

1 第1のトランジスタ 2 第2のトランジスタ 3 抵抗 4 ダイオードチェーン 1 1st transistor 2 2nd transistor 3 Resistor 4 Diode chain

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1のトランジスタと第2のトランジス
タのベース電極同士が接続され、かつ第2のトランジス
タのコレクタ電極とベース電極は互いに接続され、第2
のトランジスタのコレクタ・ベース端子は抵抗を通して
電源端子に接続され、かつ第1のトランジスタのコレク
タ端子は1個以上のダイオードチェーンを介して前記電
源端子に接続されていることを特徴とする半導体集積回
路の中のカレントミラー回路。
1. The base electrodes of the first transistor and the second transistor are connected to each other, and the collector electrode and the base electrode of the second transistor are connected to each other.
The semiconductor integrated circuit is characterized in that the collector / base terminal of the transistor is connected to a power supply terminal through a resistor, and the collector terminal of the first transistor is connected to the power supply terminal through one or more diode chains. Current mirror circuit inside.
JP3276147A 1991-09-30 1991-09-30 Current mirror circuit in semiconductor integrated circuit Pending JPH0590848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3276147A JPH0590848A (en) 1991-09-30 1991-09-30 Current mirror circuit in semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3276147A JPH0590848A (en) 1991-09-30 1991-09-30 Current mirror circuit in semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0590848A true JPH0590848A (en) 1993-04-09

Family

ID=17565423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3276147A Pending JPH0590848A (en) 1991-09-30 1991-09-30 Current mirror circuit in semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0590848A (en)

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