JPH10261765A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of ensuring normal operation, by excluding adverse influence caused by a B-C diode, and preventing malfunction of adjacent elements. SOLUTION: This integrated circuit is provided with the following; an epitaxial layer 2 formed on a semiconductor substrate, a first N<+> diffusion layer 5 formed in the epitaxial layer 2, a P diffusion layer 4 formed in the epitaxial layer 2, a second N<+> diffusion layer 6 which is formed in the P diffusion layer 4 and connected with an I/O terminal, and an isolation layer 3 which isolates the epitaxial layer 2 and is grounded. The first N<+> diffusion layer constituting the collector of a transistor formed in the epitaxial layer 2 is connected with the P diffusion layer 4 constituting the base of the transistor. The layers 4, 5 are grounded independently of the isolation layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a surge protection function for preventing a malfunction caused by a surge applied to an input / output terminal.

[0002]

2. Description of the Related Art FIG. 7 is a sectional view showing a conventional example. FIG. 8 is an explanatory diagram of the operation. In FIG. 7, 1 is P
Type semiconductor substrate, 2 denotes an epitaxial layer (hereinafter referred to as an epi layer), 3 denotes a separation layer surrounding the epi layer 2, and 6 denotes an epi layer 2.
Is an N + diffusion layer, which is another epi layer, and 8 is a pad constituting an input / output terminal.

In this conventional technique, as a surge protection for a pad 8 constituting an input / output terminal, an isolation layer 3 called ISO and an epi layer 2 surrounded by the isolation layer 3 are provided with N +.
Diffusion layer 6 is inserted, and N + diffusion layer 6 is connected to pad 8.

Here, a negative potential is applied to the pad 8,
When it falls below the ground (separation) potential, N
+ A current flows through the layer 6. That is, the current flows through the diode D1 shown in FIG. Here, the diode D1 is called a PN junction base-collector diode (hereinafter referred to as a BC diode).

If the negative potential has no current capability or the like, the diode D1 limits the potential, and the potential of the pad 8 is clamped at about -0.7 V (the VF potential of the diode D1).

However, if the negative potential further increases and the current capability exists, the other epitaxial layers, ie, the N + layers 8 and
A parasitic NPN transistor Tr1 is generated by the ISO separation layer 3 and the N + layer 6 of the diode D1, and the next epi layer 7
Draws current from Thereby, the adjacent epi layer 7
May malfunction or the characteristics of the element may not be obtained.

The prior art as a publication includes Japanese Unexamined Patent Publication No.
Although there is -253260, this does not solve the above-mentioned problem.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the adverse effect of a BC diode, prevent a malfunction of an adjacent element, and secure its normal operation.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: an epitaxial layer formed on a semiconductor substrate; and a first N + layer formed on the epitaxial layer.
A diffusion layer, a P diffusion layer formed in the epitaxial layer, a second N + diffusion layer formed in the P diffusion layer and connected to the input / output terminal, and a separation layer separating the epitaxial layer and grounding The first layer forming a collector of a transistor formed in the epitaxial layer.
And the P diffusion layer constituting the base of the transistor are connected to each other, and this is grounded separately from the isolation layer.

[0010] In the semiconductor integrated circuit of the second invention,
An epitaxial layer formed on the semiconductor substrate, a first N + diffusion layer formed on the epitaxial layer, a P diffusion layer formed on the epitaxial layer, and an input / output terminal formed on the P diffusion layer. A second N + diffusion layer to be formed, and a separation layer separating the epitaxial layer and grounding, the first N + diffusion layer and the transistor forming a collector of a transistor formed in the epitaxial layer. Connected to the P-diffusion layer constituting the base, and grounded separately from the separation layer;
A third N + diffusion layer is provided as a floating collector for lowering the resistance between the epitaxial layer and the semiconductor substrate.

[0011] In the semiconductor integrated circuit of the third invention,
A third N + diffusion layer as a floating collector,
Between the epitaxial layer and the P layer of the semiconductor substrate,
It is provided corresponding to the first N + diffusion layer and the P diffusion layer of the epitaxial layer.

In a semiconductor integrated circuit according to a fourth aspect of the present invention,
An epitaxial layer formed on the semiconductor substrate, a first N + diffusion layer formed on the epitaxial layer, a P diffusion layer formed on the epitaxial layer, and an input / output terminal formed on the P diffusion layer. A second N + diffusion layer to be formed, and a separation layer separating the epitaxial layer and grounding, the first N + diffusion layer and the transistor forming a collector of a transistor formed in the epitaxial layer. Connected to the P-diffusion layer constituting the base, and grounded separately from the separation layer;
A fourth N + diffusion layer is provided as a collector wall for reducing the resistance of the epitaxial layer.

In a semiconductor integrated circuit according to a fifth aspect of the present invention,
A fourth N + diffusion layer as a collector wall is provided between the first N + diffusion layer and the third N + diffusion layer.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows Embodiment 1 of the present invention.
FIG. FIG. 2 is an explanatory diagram of the operation.
In FIG. 1, 1 is a semiconductor substrate made of a P layer, 2 is an epi layer, 3 is a separation layer surrounding the epi layer 2, 4 is a P diffusion layer, 5
Is an N + diffusion layer, 6 is an N + diffusion layer provided on the P diffusion layer 4, 7
Is an N + diffusion layer formed in another epi layer, and 8 is a pad constituting an input / output terminal.

In the structure of the first embodiment, an NPN transistor is formed on the single N + epilayer 6 connected to the pad 8, and the emitter 6 of the NPN transistor TR2 is formed.
To the pad 8 and the base 4 and the collector 5 of the NPN transistor TR2 are short-circuited and grounded separately from the ISO isolation layer 3.

As shown in FIG. 2, an NPN transistor of TR2 is formed, and its base 4 and collector 6 are short-circuited. FIG. 2 equivalently shows the NPN transistor TR1, the NPN transistor TR2 and the resistor R1 formed in this configuration in the sectional view of the first embodiment shown in FIG. 1, and additionally shows them. That is, with such a configuration, an emitter-base diode (hereinafter, referred to as an EB diode) can be operated.

Next, the operation will be described. When a negative potential is applied to the pad 8, when the potential drops below the ground potential, a current flows from the base 4 to the emitter 6 of the NPN transistor Tr2.

Here, the NPN transistor Tr2 is EB
It operates as a diode and performs the same function as a conventional CB diode. At this time, no current flows from the ISO separation layer 3.

Therefore, since the base 4 and the collector 5 of the NPN transistor Tr2 are short-circuited and grounded, a current flows from the ground portion, but no current flows from the ISO separation layer 3 and the NPN transistor Tr1
Does not work. That is, no current is drawn from the emitter of the parasitic transistor Tr1, and Tr1 does not operate. Therefore, no malfunction occurs.

According to the first embodiment, the first transistor forming the collector of the transistor formed in epi layer 2
N + diffusion layer 5 and P diffusion layer 4 forming the base of the transistor are connected, and this is grounded separately from isolation layer 3,
This eliminates the adverse effect of the BC diode, prevents malfunction of adjacent elements, and ensures normal operation.

Embodiment 2 FIG. FIG. 3 is a sectional view showing the second embodiment. FIG. 4 is an explanatory diagram of the operation. FIG.
FIG. 2 is a further reinforcement of FIG. In FIG. 3, 1 is a semiconductor substrate made of a P layer, 2 is an epitaxial layer (hereinafter referred to as an epi layer), 3 is a separation layer surrounding the epi layer 2,
4 is a P diffusion layer, 5 is an N + diffusion layer, 6 is an N + diffusion layer provided in the P diffusion layer 4, 7 is another N + diffusion layer as an epi layer, 8 is a pad constituting an input / output terminal, 9 is an N + diffusion layer as a floating collector.

An N + diffusion layer 9 as a floating collector is provided between the epi layer 2 and the P layer of the semiconductor substrate 1.
It is provided corresponding to the N + diffusion layer 5 and the P diffusion layer 4 of the epi layer 2.

In FIGS. 1 and 2, when a negative potential is applied to the pad 8 and a large current flows, the resistor R1 shown in FIG. 2 is formed on the collector 6 side of the NPN transistor Tr2 by the resistance component of the epi layer. . That is, when the amount of current is small, no potential difference occurs, and the diode functions as a diode.

Then, a potential difference occurs due to the resistance R1,
The NPN transistor Tr2 performs a transistor operation. Then, the NPN transistor Tr2 becomes saturated, and NP
The emitter potential of the N transistor Tr1 becomes low,
The NPN transistor Tr1 operates.

In order to eliminate this state, an N + layer 9 is buried between the epi layers as a substrate to reduce the resistance R1 of FIG. As a result, a malfunction and a parasitic element operation can be prevented with respect to a further negative surge input.

According to the second embodiment, the first transistor constituting the collector of the transistor formed in epi layer 2
N + diffusion layer 5 and P diffusion layer 4 forming the base of the transistor are connected to each other and grounded separately from isolation layer 3 to reduce the resistance between epi layer 2 and semiconductor substrate 1. Third N + with floating collector
By providing the diffusion layer 9 between the epi layer 2 and the P layer of the semiconductor substrate 1 corresponding to the first N + diffusion layer 5 and the P diffusion layer 4, the adverse effect of the BC diode is eliminated. However, malfunction of adjacent elements can be prevented, and normal operation thereof can be ensured.

Embodiment 3 FIG. 5 is a sectional view showing the third embodiment. FIG. 6 is an explanatory diagram of the operation. In FIG. 5, 1 is a semiconductor substrate composed of a P layer, 2 is an epitaxial layer (hereinafter referred to as an epi layer), 3 is a separation layer surrounding the epi layer 2, 4 is a P diffusion layer, 5 is an N + diffusion layer, 6 Is an N + diffusion layer provided in the P diffusion layer 4, 7 is an N + diffusion layer as another epi layer, 8 is a pad constituting an input / output terminal, 9 is an N + diffusion layer as a floating collector, and 10 is a collector. An N + diffusion layer as a wall.

An N + diffusion layer 9 as a floating collector is provided between the epi layer 2 and the P layer of the semiconductor substrate 1.
It is provided corresponding to the N + diffusion layer 5 and the P diffusion layer 4 of the epi layer 2. N + diffusion layer 1 as collector wall
0 is provided between the N + diffusion layer 5 and the N + diffusion layer 9 as a floating collector.

The third embodiment is basically the same as the second embodiment, except that the N + layer 9 called CW is diffused to further reduce the resistance of the epi layer for further strengthening. , Except that it does not work at all except for the NPN transistor Tr2.

According to the third embodiment, the first transistor constituting the collector of the transistor formed in epi layer 2 is formed.
N + diffusion layer 5 and P diffusion layer 4 forming the base of the transistor are connected to each other, grounded separately from isolation layer 3, and a fourth collector wall as a collector wall for lowering the resistance of the epitaxial layer is connected. Is provided between the first N + diffusion layer 5 and the third N + diffusion layer 9 as a floating collector, so that the B-C
This eliminates the adverse effect of the diode, prevents malfunction of adjacent elements, and ensures normal operation.

[0031]

According to the first aspect of the present invention, the first N + diffusion layer forming the collector of the transistor formed in the epitaxial layer and the P type forming the base of the transistor are formed.
Diffusion layer is connected, and this is grounded separately from the separation layer.
This eliminates the adverse effects of the -C diode, prevents malfunction of adjacent elements, and ensures normal operation.

According to the second invention, the first N + diffusion layer forming the collector of the transistor formed in the epitaxial layer is connected to the P diffusion layer forming the base of the transistor, and this is connected to the separation layer. And a third N + as a floating collector for lowering the resistance between the epitaxial layer and the semiconductor substrate.
By providing a diffusion layer, it is possible to eliminate the adverse effect of the BC diode, prevent a malfunction of an adjacent element, and secure its normal operation.

According to the third aspect of the present invention, the third N + diffusion layer as a floating collector is provided between the epitaxial layer and the P layer of the semiconductor substrate by the first N + diffusion layer and the P diffusion of the epitaxial layer. By providing the layers corresponding to the layers, the adverse effect of the BC diode can be eliminated, malfunction of adjacent elements can be prevented, and normal operation can be ensured.

According to the fourth aspect, the first N + diffusion layer forming the collector of the transistor formed in the epitaxial layer is connected to the P diffusion layer forming the base of the transistor. By providing grounding separately from the isolation layer and providing a fourth N + diffusion layer as a collector wall for lowering the resistance of the epitaxial layer, the adverse effect of the BC diode is eliminated, and malfunction of adjacent elements is prevented. It is possible to prevent the normal operation.

According to the fifth aspect of the present invention, the fourth N + diffusion layer as a collector wall is provided between the first N + diffusion layer and the third N + diffusion layer. This eliminates the adverse effects of the C diode, prevents malfunction of adjacent elements, and ensures normal operation.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of FIG. 3;

FIG. 5 is a sectional view showing Embodiment 3 of the present invention.

FIG. 6 is an operation explanatory diagram of FIG. 5;

FIG. 7 is a cross-sectional view showing a structure according to a conventional technique.

8 is an operation explanatory diagram of FIG. 7;

[Explanation of symbols]

1 a semiconductor substrate composed of a P layer, 2 epi layers, 3 isolation layers surrounding the epi layer 2, 4 P diffusion layers, 5 first N + diffusion layers,
6 a second N + diffusion layer provided on the P diffusion layer 4, 7 another N + diffusion layer as an epi layer, 8 a pad constituting an input / output terminal, 9 a third N + diffusion layer as a floating collector, 10 Fourth N + diffusion layer as collector wall, Tr1 NPN transistor, Tr2 NPN transistor, D1 diode, R1 resistor, PP diffusion layer, N + N + diffusion layer, ISO isolation (P diffusion) layer, FC
Floating collector: N + diffusion layer, CW Collector wall: N + diffusion layer.

Claims (5)

[Claims] 1. An epitaxial layer formed on a semiconductor substrate, a first N + diffusion layer formed on the epitaxial layer, a P diffusion layer formed on the epitaxial layer, and a P diffusion layer formed on the epitaxial layer. A second N + diffusion layer connected to the input / output terminal; and a separation layer separating the epitaxial layer and grounding, the first layer constituting a collector of a transistor formed in the epitaxial layer.
Wherein the N @ + diffusion layer is connected to the P diffusion layer forming the base of the transistor, and this is grounded separately from the isolation layer. 2. An epitaxial layer formed on a semiconductor substrate, a first N + diffusion layer formed on the epitaxial layer, a P diffusion layer formed on the epitaxial layer, and a P diffusion layer formed on the P layer. A second N + diffusion layer connected to the input / output terminal; and a separation layer separating the epitaxial layer and grounding, the first layer constituting a collector of a transistor formed in the epitaxial layer.
N + diffusion layer and the P diffusion layer constituting the base of the transistor are connected to each other and grounded separately from the isolation layer, and the floating layer for lowering the resistance between the epitaxial layer and the semiconductor substrate is connected. 2. The semiconductor integrated circuit according to claim 1, wherein a third N + diffusion layer is provided as a collector. 3. A third N + diffusion layer as a floating collector is provided between the epitaxial layer and the P layer of the semiconductor substrate, corresponding to the first N + diffusion layer and the P diffusion layer of the epitaxial layer. 3. The device according to claim 2, wherein
3. The semiconductor integrated circuit according to claim 1. 4. An epitaxial layer formed on a semiconductor substrate, a first N + diffusion layer formed on the epitaxial layer, a P diffusion layer formed on the epitaxial layer, and a P diffusion layer formed on the P layer. A second N + diffusion layer connected to the input / output terminal; and a separation layer separating the epitaxial layer and grounding, the first layer constituting a collector of a transistor formed in the epitaxial layer.
N + diffusion layer and the P diffusion layer forming the base of the transistor are connected to each other and grounded separately from the isolation layer, and a fourth collector wall is formed as a collector wall for lowering the resistance of the epitaxial layer. 4. The semiconductor integrated circuit according to claim 1, further comprising an N @ + diffusion layer. 5. The method according to claim 4, wherein a fourth N + diffusion layer as a collector wall is provided between the first N + diffusion layer and the third N + diffusion layer. Semiconductor integrated circuit.