JPH0587151B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits (hereinafter referred to as IC).
In particular, those that require multiple power supplies and TTL
The present invention relates to a semiconductor integrated circuit having an input circuit.

[Conventional technology]

In conventional bipolar ICs that have two power supplies, one for TTL and one for ECL, the TTL section handles positive voltage digital signals and the other handles negative voltage.
The ECL section is mixed. Regarding the TTL section, if a negative voltage is applied to the input terminal due to reflection or crosstalk, the circuit may malfunction. For this reason, a clamp diode is provided at the input or output section to prevent negative voltage input.

3 to 5 show such conventional examples,
FIG. 3 is a circuit diagram showing a TTL input section that performs TTL-ECL conversion that allows a signal processed by a TTL circuit to be applied to an ECL circuit. A signal processed by a TTL circuit is applied from input terminal 1. Power supply terminal 5 for TTL and power supply terminal 3 for ECL
A resistor R is connected between the emitter and collector of the RNP input transistor _Q1 , and the base of the input transistor _Q1 is connected together with the input terminal 1 to the cathodes of the diodes _D1 and _D2 .
The anode of diode D ₂ is connected to ECL power supply terminal 3,
Further, the anode of the diode D ₁ is connected to the ground terminal 2 . This diode _D2 is formed parasitically in a semiconductor integrated circuit.

FIG. 4 shows a cross-sectional view of a TTL input section formed in a semiconductor, in which an n-type epitaxial layer is formed on a p-type semiconductor substrate 6, and an oxide isolation region 9 passes through this epitaxial layer. The epitaxial layer is separated into a plurality of n-type semiconductor portions 8 by the steps of FIG.
An input clamp diode 12 is formed by forming a P-type region 10 in one of the n-type semiconductor parts 8 . Thereby, a clamp diode D ₁ is configured between the ground line 2 and the input terminal 1. Since ECL power is applied to the semiconductor substrate 6, a parasitic diode _D2 is equivalently configured between the n-type semiconductor section 8 to which the input terminal 1 is connected and the P-type semiconductor substrate 6.
Next to the high-concentration P-type semiconductor section 15 for lowering the P-type substrate 6 to the lowest potential, other input/output TTLs are installed.
A high-concentration n-type semiconductor 16 is formed by diffusion to prevent level inversion, and this high-concentration pn-type semiconductor portion 1
3 is connected to the lowest potential ECL power supply terminal.
This part serves as a guard ring for the input clamp section. The TTL input transistor 14 has another n-type semiconductor part 8 as a base, a P-type region 10 formed therein as an emitter, and a semiconductor substrate 6 as a collector.
It constitutes a pnp transistor _Q1 .

[Problem that the invention seeks to solve]

The conventional two power supplies mentioned above, that is, the TTL power supply and
In the TTL input circuit of an IC that has an ECL power supply,
There was a problem in which pseudo latch-up occurred when a current of several tens of mA was drawn.

That is, when the current is gradually drawn out from the input terminal 1, it flows from the grounded p-type semiconductor 10 to the input terminal 1 through the n-type semiconductor section 8 and the high concentration n-type semiconductor section 7. The current path that was connected to the high concentration p-type semiconductor section 10 is grounded.
Therefore, the path almost changes to a path where it passes through the high concentration n-type semiconductor portion 7 of the buried layer, further passes through the p-type semiconductor substrate 6, and flows from the high concentration n-type semiconductor 16 to the ECL power supply terminal 3. For this reason, although the voltage between the grounding terminal 2 and the input terminal 1 has been clamped to about -0.75V, it sometimes jumps to about -2.0V.

If an equivalent circuit is drawn, as shown in FIG. 5 (also shown in FIG. 4), transistors Q ₂ and Q ₃ form a thyristor between the ground terminal 2 and the ECL power supply terminal 3. Input terminal 1 becomes the base of transistor Q ₂ , so if you draw tens of mA from here, you will see that several hundred mA of current flows from ground terminal 2 to ECL power supply terminal 3.

[Means for solving problems]

The object of the present invention has been made in view of the above points, and is an object of the present invention to provide an input section for TTL-ECL conversion of an integrated circuit having both ECL and TTL power supplies.
The present invention provides a TTL input circuit which has a stable clamping ability and which does not cause inversion of the potentials of other TTL input/outputs due to excessively lowering the input voltage.

The semiconductor integrated circuit of the present invention has a semiconductor substrate, an epitaxial layer laminated on the semiconductor substrate, and a separation region that separates the epitaxial layer into island regions, and further includes an isolation region for maintaining the potential of the semiconductor substrate. A semiconductor of the same conductivity type formed on a semiconductor substrate, a means for applying a substrate potential to the semiconductor portion of the same conductivity type, a semiconductor region of a different conductivity type formed on the semiconductor substrate, and a semiconductor region of the other conductivity type formed on the semiconductor substrate; and means for applying a potential different from the potential.

〔Example〕

Next, embodiments of the present invention will be described using the drawings. FIG. 1 is a cross section of a TTL input section of a semiconductor integrated circuit according to an embodiment of the present invention. In this embodiment, in the structure of the conventional example shown in FIG. 4, ECL power supplies of the lowest potential are applied to the highly doped P-type semiconductor region 15 and the highly doped N-type semiconductor region 16, respectively, in order to reduce the potential of the P-type semiconductor substrate 6 to the lowest potential. 3 and grounding 2 are given separately.

In this embodiment, when the level of input terminal 1 is lowered, current is injected from ground terminal 2, and the gap between ground terminal 2 and input terminal 1 is clamped to approximately -0.75V, which is approximately equal to one stage of diode. . On the other hand, the P-type substrate 6
It can be seen that since the high concentration n-type semiconductor portion 16 is connected to the ECL power supply terminal 3 and is connected to the ground terminal 2, a pnpn parasitic thyristor is not generated as in the conventional case. Furthermore, the high concentration n-type semiconductor section 16 is biased to a higher potential than before;
When the input potential of input terminal 1 is lowered, a current is injected from ground terminal 2. Therefore, as in the conventional case, no current is drawn from the n-type semiconductor portion 8 of other TTL input/output circuits, so that malfunctions of other input/output circuits do not occur.

[Embodiment 2] FIG. 2 is a sectional view of a TTL input section of a semiconductor integrated circuit according to another embodiment of the present invention. In this example,
A high-concentration P-type semiconductor section 15 for bringing the P-type semiconductor substrate 6 provided in a conventional TTL input section to the lowest potential, and a high-concentration N-type semiconductor section 16 for preventing reversal on the negative voltage side of TTL. The highly doped P-type semiconductor section 15, which is completely separated by the insulator 9, is set to the lowest potential ECL power source 3, while the highly doped N-type semiconductor section 16 is set to the ground potential.

This example also exhibits the same characteristics as the example shown in FIG.

[Effects of the Invention] As explained above, according to the present invention, ECL
The high-concentration P-type semiconductor part to lower the potential to the lowest potential of the power supply and the high-concentration N-type semiconductor part to prevent other TTL input/output levels from being reversed due to an excessive drop in the input voltage are placed at different potentials.
By setting the ECL power supply potential and ground potential,
Sufficient current can be drawn from the TTL input section, and malfunctions of other TTL inputs and outputs can be prevented.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a TTL input section of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a TTL input section of a semiconductor integrated circuit according to another embodiment of the present invention, and FIG. 3 is a TTL input section of a semiconductor integrated circuit according to another embodiment of the present invention. FIG. 4 is a sectional view of a TTL input section of a conventional semiconductor integrated circuit, and FIG. 5 is an equivalent circuit diagram of a pseudo latch-up that occurs in the conventional configuration. 1...Input terminal, 2...Ground terminal, 3...
Power supply terminal for ECL, 4...Internal circuit, 5...TLL
6... P-type semiconductor substrate, 7... Buried layer, 8... N-type semiconductor part, 9... Izration part, 10... P-type semiconductor part, 11... Al
Wiring, Q ₁ ... PNP input transistor, Q ₂ , Q ₃ ...
...parasitic transistor, D ₁ , D ₂ ... diode,
R...Resistor, 12...Input clamp diode section (corresponding to _D1 and _D2 in Fig. 3), 13...PN section guard ringing the input clamp diode,
14...TTL input transistor (corresponding to _Q1 in Figure 3), 15...High concentration p-type semiconductor section, 16
...High concentration n-type semiconductor section.

Claims (1)

[Claims] 1 a semiconductor substrate of one conductivity type, first, second, and third regions of another conductivity type formed on the semiconductor substrate and separated from each other by a separation region;
the fourth region of the one conductivity type formed within the region; and the fifth region of the one conductivity type formed within the third region, the first and third regions is connected to an input terminal, the fifth region is connected to a TTL terminal via a resistor, and the semiconductor substrate is connected to an input terminal.
It is connected to an EEL terminal, the second region is sandwiched between the first region and the second region, and the second and fourth regions are connected to a ground terminal. semiconductor integrated circuits.