JP2000101028A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of crosstalks in a semiconductor device where an analog and digital mixed integrated circuit is formed. SOLUTION: A p-type epitaxial film 102 is made on the surface of an n-type silicon substrate 101. A digital integrated circuit, in the region 103 of this epitaxial film 102, and an analog integrated circuit region, in the region 104, are made. A great part of the noise introduced from a gate electrode 107 is propagated to the region 104 through the substrate 101 from the region 103 of the epitaxial film 102 and reaches an n" diffused region 109, by completely separating these regions 103 and 104 with a trench structure of element isolating region 105. Here, a depletion layer is made at the interface (that is, the P-N junction face) between the n-type silicon substrate 101 and a p-type epitaxial film 102, so the parasitic capacity C8 and C9 in the vicinity of this interface becomes very small, therefore, the composite capacity of the noise propagation passage at large becomes small. Consequently, this semiconductor device can suppress the propagation of the noise and suppress the occurrence of crosstalk.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an analog integrated circuit and a digital integrated circuit are mounted.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device in which an analog integrated circuit and a digital integrated circuit are mixedly mounted (hereinafter referred to as an AD mixed LS).
I) are known. Such an LSI is used, for example, in the construction of a multimedia system.
Used to advance on-chip. AD mixed L
SI is effective in reducing the number of chips to achieve low power, miniaturization, economy, etc., but has the disadvantage that the characteristics of analog integrated circuits are likely to deteriorate due to noise generated in digital integrated circuits. are doing. In particular, crosstalk from a digital integrated circuit causes an increase in the SN ratio of the analog integrated circuit and a limitation on the dynamic range.

[0003] Crosstalk occurs when noise generated in an element in an integrated circuit propagates through a substrate and reaches another element. At this time, the noise propagation efficiency depends on the resistance component and the capacitance component of the substrate. That is, in order to suppress the crosstalk, the resistance of the substrate may be increased and the capacitance may be reduced. For this reason, the influence of crosstalk is small in an AD-mixed LSI using an insulating substrate,
An AD mixed LSI using a semiconductor substrate requires a design technique for suppressing crosstalk.

[0004] Conventionally, as a technique for suppressing crosstalk of an AD-mixed LSI, for example, the technique described in the following literature is known.

A. Vibiani et al., IEDM Tech. Deg. (1995)
p.713

[0006]

FIG. 2A is a sectional view conceptually showing a parasitic capacitance of an AD-mixed LSI manufactured using a silicon substrate.

As shown in FIG. 2A, a P-type silicon substrate 201 has a digital integrated circuit having a gate oxide film 202 and a gate electrode 203 and an N ⁺ diffusion layer 204.
Is formed. Here, the gate oxide film 202 and the gate electrode 203 are, for example, a part of a MOS (Metal Oxide Semiconductor) transistor, and the N ⁺ diffusion layer 204 is, for example, a source or a drain of a bipolar transistor. In such a configuration, the gate electrode 203 can be considered as a noise introduction source, and the N ⁺ diffusion layer 204 can be considered as a noise detection source.

[0008] Gate electrode 203 as a noise introducing source
If, between the rear surface of the substrate 201 (i.e. ground), the parasitic resistance R ₁ and the parasitic capacitance C ₁ is generated. Further, an N ⁺ diffusion layer 204 as a noise detection source and a substrate 2
01, the parasitic resistance R ₂ and the parasitic capacitance C
₂ occurs. Here, R ₁ = R ₂ and C ₁ = C ₂ .

A parasitic resistance R is provided between a noise introduction source (gate electrode 203) and a noise detection source (N ⁺ diffusion layer 204).
₃ and the parasitic capacitance C ₃ is generated.

A depletion layer formed near gate oxide film 202 has capacitance C ₄ , and a depletion layer formed at the PN junction between N ⁺ diffusion layer 204 and silicon substrate 201 has capacitance C ₅ . . Since the impurity concentration of the silicon substrate 201 is usually about 1 × 10 ¹⁸ cm ⁻³ , the gate oxide film 20
The width of the depletion layer formed near 2 is usually about 30 nm. Since the well concentration is usually about 1 × 10 ¹⁷ cm ^{−3, the} width of the depletion layer formed on the PN junction surface is usually 100 nm.
About.

FIG. 2B shows an SOI (Silicon On Insula).
ter) is a cross-sectional view conceptually showing the parasitic capacitance of the AD-mixed LSI manufactured using the substrate, and is the same as FIG. 7 of the above-mentioned document.

As shown in FIG. 2B, a P-type silicon substrate 211 has a buried oxide film 21 having a thickness of 400 nm.
2 are formed. Then, the buried oxide film 21
2, a digital integrated circuit having a P ⁺ diffusion layer 213, a gate oxide film 214, and a gate electrode 215, and an analog integrated circuit having an N ⁺ diffusion layer 216 are formed. Here, the P ⁺ diffusion layer 213 and the gate oxide film 214
The gate electrode 215 is, for example, a part of a MOS transistor, and the N ⁺ diffusion layer 216 is, for example, a source or a drain of a bipolar transistor.

Even in such an AD-mixed LSI, a noise introducing source (gate electrode 215) is provided in the silicon substrate 211.
The parasitic resistance R ₁ and the parasitic capacitance C ₁ , the noise detection source (N ⁺ diffusion layer 216) and the substrate 21
Parasitic resistance R ₂ and the parasitic capacitance C ₂ between the first back side, the parasitic resistance R ₃ and the parasitic capacitance C ₃ between the noise introduced source and the noise detection source, generated respectively. The values of the parasitic resistance and the parasitic capacitance are the same as those in the case of the AD mixed LSI shown in FIG.

In the buried oxide film 212, P ⁺
The parasitic capacitance C between the diffusion layer 213 and the silicon substrate 211
₆ , a parasitic capacitance C ₇ is generated between the N ⁺ diffusion layer 216 and the silicon substrate 211.

Here, the values of the parasitic capacitances C ₆ and C ₇ generated in the buried oxide film 212 are smaller than the parasitic capacitances C ₄ and C ₅ in FIG. 2A. Therefore, SOI
By manufacturing an AD mixed LSI using a substrate, crosstalk can be reduced as compared with the case where a silicon substrate is used.

An AD-mixed LSI using an SOI substrate
Then, the distance between the P ⁺ diffusion layer 213 and the N ⁺ diffusion layer 216 is increased, the resistance value of the silicon substrate 211 is increased, and a guard ring is provided between the P ⁺ diffusion layer 213 and the N ⁺ diffusion layer 216. It is possible to further reduce crosstalk by inserting.

However, when an SOI substrate is used for an AD-embedded LSI, there is a disadvantage that the production cost is increased because the SOI substrate is expensive.

[0018] On the contrary, it is also possible to use an inexpensive SIMOX (S eparation by Im planted Ox ygen) substrate to reduce manufacturing cost as an SOI substrate. However, since the limit of the thickness of the buried oxide film 212 is only about 400 nm in the SIMOX substrate, the parasitic capacitances C ₆ and C
The value of ₇ cannot be made small enough, so
There is a limit to the suppression of crosstalk.

For these reasons, there has been a demand for a technique for inexpensively manufacturing an AD mixed LSI in which crosstalk is sufficiently suppressed.

[0020]

Means for Solving the Problems (1) The present invention provides the first
A second conductive type semiconductor thin film formed on a surface of a conductive type semiconductor substrate; a digital integrated circuit region and an analog integrated circuit region provided on the semiconductor thin film; and a boundary region between the digital integrated circuit region and the analog integrated circuit region Device isolation means formed from the surface of the semiconductor thin film to the inside of the semiconductor substrate.

According to such a configuration, since the semiconductor substrate and the semiconductor thin film form a PN junction, a depletion layer can be generated near the PN junction surface. Also, since the digital integrated circuit region and the analog integrated circuit region are completely separated by the element isolation film, most of the noise generated in the digital integrated circuit region passes through the depletion layer and propagates to the semiconductor substrate. Further, it reaches the analog integrated circuit region through the depletion layer. Here, the parasitic capacitance of the depletion layer is much smaller than the parasitic capacitance formed in the semiconductor substrate and the semiconductor thin film. Therefore, the combined capacitance of the entire noise propagation path can be extremely reduced by the depletion layer, so that the influence of noise can be suppressed.

(2) In the present invention, it is preferable that the semiconductor device further includes a means for applying a potential to the semiconductor substrate such that a depletion layer generated in a boundary region between the semiconductor substrate and the semiconductor thin film spreads.

As a result, the depletion layer generated near this interface can be made thicker to further reduce the parasitic capacitance. As a result, the combined capacitance of the entire noise propagation path can be further reduced, so that the influence of noise is further suppressed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. Please understand that.

FIG. 1 is a sectional view conceptually showing a configuration of an AD mixed LSI as a semiconductor device according to this embodiment.

As shown in FIG. 1, in this embodiment, an N-type silicon substrate 101 having a high resistance (for example, several hundred Ω) is used as a semiconductor substrate of the present invention. This N-type silicon substrate 101 is connected to a power supply line Vcc.

In this embodiment, a high-resistance (eg, several hundred Ω) P-type epitaxial thin film 102 is formed on the surface of an N-type silicon substrate 101 as a semiconductor thin film of the present invention.
To form

The semiconductor thin film 102 includes a digital integrated circuit area 103 and an analog integrated circuit area 104.
Are provided.

An element isolation film 105 having a trench structure is formed in a boundary region between these regions 103 and 104. This element isolation film 105 is formed of a P-type epitaxial thin film 102.
From the surface of the N-type silicon substrate 101. That is, the P-type epitaxial thin film 102 is completely separated into the region 103 and the region 104 by the element isolation film 105.

In the digital integrated circuit area 103, for example, a MOS transistor or the like is formed. In FIG. 1, the MOS
Gate oxide film 106 and gate electrode 1 of transistor
Only 07 is shown. The gate electrode 107 is supplied with a signal potential Vin. The digital integrated circuit area 103 is connected to the ground line GND via the P ⁺ diffusion area 108.

On the other hand, in the analog integrated circuit area 104,
For example, a bipolar transistor or the like is formed. FIG. 1 shows only the N ⁺ diffusion region 109 as the emitter of the bipolar transistor. This N ⁺ diffusion region 10
9, a signal potential Vout is extracted. The analog integrated circuit region 104 is connected to the ground line GND via the P ⁺ diffusion region 110.

In such a configuration, the gate electrode 107 can be considered as a noise introduction source, and the N ⁺ diffusion layer 109 can be considered as a noise detection source.

In the AD-mixed LSI shown in FIG. 1, as in the conventional case (see FIGS. 2A and 2B), the gate electrode 107 as a noise introduction source, the back surface of the substrate 101 (ie, Vcc), Between the parasitic resistance R ₁ and the parasitic capacitance C
₁ occurs. A parasitic resistance R ₂ is provided between the N ⁺ diffusion layer 109 as a noise detection source and the back surface of the substrate 101.
And the parasitic capacitance C ₂ is generated. Where R ₁ = R ₂ ,
C ₁ = C ₂ .

Further, a noise introduction source (gate electrode 10)
7) and the noise detection source (N ⁺ diffusion layer 109)
Parasitic resistance R ₃ and the parasitic capacitance C ₃ is generated. In this embodiment, as described above, the P-type epitaxial thin film 10
Since the second regions 103 and 104 are completely separated by the element isolation film 105, the parasitic resistance R ₃ and the parasitic capacitance C ₃ are substantially formed only in the N-type silicon substrate 101, and the P-type epitaxial It is not formed in the thin film 102.

In addition, a depletion layer formed near gate oxide film 106 has capacitance C ₄ and N ⁺ diffusion layer 10.
A depletion layer formed at the PN junction between 9 and P-type epitaxial film 102 has a capacity C _5. Since the impurity concentration near the gate oxide film 107 is usually about 1 × 10 ¹⁸ cm ^{−3, the} width of the depletion layer formed near the gate oxide film 106 is usually about 30 nm. The well concentration is usually 1
Since it is about × 10 ¹⁷ cm ^{−3, the} width of the depletion layer formed on the PN junction surface is usually about 100 nm.

In this embodiment, since the PN junction is formed by the N-type silicon substrate 101 and the P-type epitaxial thin film 102, a depletion layer is formed near the PN junction surface. In Figure 1, of the parasitic capacitance due to the depletion layer, those formed in the digital integrated circuit region 103 side and the parasitic capacitance C _8, analog integrated circuit region 1
Those formed on the 04 side and the parasitic capacitance C _9. Here, C ₈ = C ₉ .

As described above, A according to this embodiment
In the D-mixed LSI, an element isolation film 105 was provided. Therefore, most of the noise introduced from the noise introduction source (gate electrode 107) is first of all the P-type epitaxial thin film 1
02 to the N-type silicon substrate 101, and then propagates through the analog integrated circuit region 104 of the P-type epitaxial thin film 102 to the noise detection source (N ⁺ diffusion region 109). Reach. That is, in this embodiment, noise causing crosstalk always passes through the parasitic capacitances C ₄ and C ₅ . Thus, the combined capacitance C ₀ of the parasitic capacitance in the noise propagation path is given by the following equation (1).

[0038] C ₀ ^{- 1} = C ₄ ^{- 1} + C ₈ ^{- 1} + C ₃ ^{- 1} + C ₉ ^{- 1} + C ₅ ^{- 1} (1) Here, by increasing the concentration of the N-type silicon substrate 101 and the P-type epitaxial thin film 102, the interface (PN
The thickness of the depletion layer formed on the junction surface) is the same for both the N-type silicon substrate 101 side and the P-type epitaxial thin film 102 side.
It is about 2 μm at the maximum. That is, a depletion layer having a thickness of about 4 μm can be formed at this interface.
This thickness corresponds to about 1 μm in terms of a silicon oxide film, and is larger than the thickness of the buried oxide film of SIMOX.

The parasitic capacitances C ₈ and C ₉ of the depletion layer are much smaller than the parasitic capacitance of silicon. For this reason,
In the AD-mixed LSI according to the present embodiment, the combined capacitance C ₀ (see the above equation (1)) of the parasitic capacitance can be made very small as compared with the conventional case. Therefore, it is possible to suppress noise propagation and prevent crosstalk.

Further, as described above, in this embodiment, the power supply potential Vcc is applied to the N-type silicon substrate 101. Thereby, the N-type silicon substrate 101 and P
Since the thickness of the depletion layer generated near the interface with the type epitaxial thin film 102 can be increased, the combined capacitance C ₀ of the parasitic capacitance can be further reduced.

However, it is desirable to control the thickness of the depletion layer generated near the interface between the N-type silicon substrate 101 and the P-type epitaxial thin film 102 so as not to reach the N ⁺ diffusion region 109. When the depletion layer reaches the N ⁺ diffusion region 109, the gate electrode 107 and the N ⁺ diffusion region 109
Is conducted, and there is a possibility that the AD-mixed LSI may malfunction.

In addition, the parasitic capacitance at the PN junction can be further reduced by appropriately changing other conditions such as the impurity concentration of the N-type silicon substrate 101 and the thickness of the P-type epitaxial thin film 102. is there.

In this embodiment, the semiconductor substrate is N-type and the semiconductor thin film is P-type. However, the same effect can be obtained in an AD-mixed LSI in which the conductivity types of the substrate, the thin film and the diffusion region are reversed. Can be.

[0044]

As described above in detail, according to the present invention, it is possible to provide a low-cost semiconductor device capable of sufficiently suppressing crosstalk.

[Brief description of the drawings]

FIG. 1 is a sectional view conceptually showing a structure of a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views conceptually showing the structure of a conventional semiconductor device.

DESCRIPTION OF SYMBOLS 101 N-type silicon substrate 102 P-type epitaxial thin film 103 Digital integrated circuit area 104 Analog integrated circuit area 105 Element isolation film 106 Gate oxide film 107 Gate electrode 108, 110 P ⁺ diffusion region 109 N ⁺ diffusion region

Claims (5)

[Claims] A second conductive type semiconductor thin film formed on a surface of a first conductive type semiconductor substrate; a digital integrated circuit region and an analog integrated circuit region provided on the semiconductor thin film; And a device separating means formed in a boundary region between the semiconductor thin film and the inside of the semiconductor substrate in a boundary region between the semiconductor integrated circuit region and the analog integrated circuit region. 2. The semiconductor device according to claim 1, further comprising means for applying a potential to the semiconductor substrate such that a depletion layer generated in a boundary region between the semiconductor substrate and the semiconductor thin film spreads. 3. The semiconductor device according to claim 2, wherein said potential is determined so that said depletion layer does not reach an element formed in said analog integrated circuit region. 4. The semiconductor device according to claim 1, wherein said semiconductor thin film is an epitaxially grown film. 5. The semiconductor device according to claim 1, wherein said element isolation means is an element isolation film having a trench structure.