JP2001283589A5 - - Google Patents

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Publication number
JP2001283589A5
JP2001283589A5 JP2000095826A JP2000095826A JP2001283589A5 JP 2001283589 A5 JP2001283589 A5 JP 2001283589A5 JP 2000095826 A JP2000095826 A JP 2000095826A JP 2000095826 A JP2000095826 A JP 2000095826A JP 2001283589 A5 JP2001283589 A5 JP 2001283589A5
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JP
Japan
Prior art keywords
clock signal
frequency divider
signal
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2000095826A
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English (en)
Japanese (ja)
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JP2001283589A (ja
JP4045064B2 (ja
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Publication date
Application filed filed Critical
Priority to JP2000095826A priority Critical patent/JP4045064B2/ja
Priority claimed from JP2000095826A external-priority patent/JP4045064B2/ja
Priority to US09/811,521 priority patent/US6388945B2/en
Publication of JP2001283589A publication Critical patent/JP2001283589A/ja
Publication of JP2001283589A5 publication Critical patent/JP2001283589A5/ja
Application granted granted Critical
Publication of JP4045064B2 publication Critical patent/JP4045064B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000095826A 2000-03-30 2000-03-30 半導体記憶装置 Expired - Fee Related JP4045064B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000095826A JP4045064B2 (ja) 2000-03-30 2000-03-30 半導体記憶装置
US09/811,521 US6388945B2 (en) 2000-03-30 2001-03-20 Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000095826A JP4045064B2 (ja) 2000-03-30 2000-03-30 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2001283589A JP2001283589A (ja) 2001-10-12
JP2001283589A5 true JP2001283589A5 (enExample) 2004-12-02
JP4045064B2 JP4045064B2 (ja) 2008-02-13

Family

ID=18610674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000095826A Expired - Fee Related JP4045064B2 (ja) 2000-03-30 2000-03-30 半導体記憶装置

Country Status (2)

Country Link
US (1) US6388945B2 (enExample)
JP (1) JP4045064B2 (enExample)

Families Citing this family (30)

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DE10149512B4 (de) * 2001-10-08 2006-08-03 Infineon Technologies Ag Verfahren und Vorrichtung zur Synchronisation der Datenübertragung zwischen zwei Schaltungen
KR100560644B1 (ko) * 2002-01-09 2006-03-16 삼성전자주식회사 클럭 동기회로를 구비하는 집적회로장치
KR100507875B1 (ko) * 2002-06-28 2005-08-18 주식회사 하이닉스반도체 지연고정루프에서의 클럭분주기 및 클럭분주방법
KR100484252B1 (ko) * 2002-11-27 2005-04-22 주식회사 하이닉스반도체 지연 고정 루프 회로
KR100500929B1 (ko) 2002-11-27 2005-07-14 주식회사 하이닉스반도체 지연 고정 루프 회로
JP4277979B2 (ja) * 2003-01-31 2009-06-10 株式会社ルネサステクノロジ 半導体集積回路装置
KR100596433B1 (ko) 2003-12-29 2006-07-05 주식회사 하이닉스반도체 반도체 기억 장치에서의 지연 고정 루프 및 그의 록킹 방법
KR100608372B1 (ko) * 2004-12-03 2006-08-08 주식회사 하이닉스반도체 동기식 메모리 장치의 데이타 출력 시점 조절 방법
JP4828203B2 (ja) * 2005-10-20 2011-11-30 エルピーダメモリ株式会社 同期型半導体記憶装置
KR100656464B1 (ko) * 2005-12-28 2006-12-11 주식회사 하이닉스반도체 반도체 메모리의 출력 인에이블 신호 생성장치 및 방법
KR100800472B1 (ko) * 2006-06-23 2008-02-04 삼성전자주식회사 스택 패키지(ｓｔａｃｋ ｐａｃｋａｇｅ)용 반도체메모리장치 및 이의 독출 데이터 스큐 조절방법
US7529996B2 (en) * 2006-08-03 2009-05-05 Texas Instruments Incorporated DDR input interface to IC test controller circuitry
US7675797B2 (en) 2006-10-31 2010-03-09 Samsung Electronics Co., Ltd. CAS latency circuit and semiconductor memory device including the same
US8045406B2 (en) 2006-10-31 2011-10-25 Samsung Electronics Co., Ltd. Latency circuit using division method related to CAS latency and semiconductor memory device
CN101617371B (zh) 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
JP5456275B2 (ja) 2008-05-16 2014-03-26 ピーエスフォー ルクスコ エスエイアールエル カウンタ回路、レイテンシカウンタ及びこれを備える半導体記憶装置、並びに、データ処理システム
KR101375466B1 (ko) 2009-01-12 2014-03-18 램버스 인코포레이티드 다중 전력 모드를 갖는 메조크로노스 시그널링 시스템
JP2011060355A (ja) * 2009-09-08 2011-03-24 Elpida Memory Inc レイテンシカウンタ及びこれを備える半導体記憶装置、並びに、データ処理システム
KR20110040538A (ko) * 2009-10-14 2011-04-20 삼성전자주식회사 레이턴시 회로 및 이를 포함하는 반도체 장치
KR101034617B1 (ko) 2009-12-29 2011-05-12 주식회사 하이닉스반도체 지연 고정 루프
JP2012190510A (ja) * 2011-03-11 2012-10-04 Elpida Memory Inc 半導体装置
US9570135B2 (en) * 2014-02-06 2017-02-14 Micron Technology, Inc. Apparatuses and methods to delay memory commands and clock signals
KR20150142851A (ko) 2014-06-12 2015-12-23 에스케이하이닉스 주식회사 동작 타이밍 마진을 개선할 수 있는 반도체 장치
KR102641515B1 (ko) * 2016-09-19 2024-02-28 삼성전자주식회사 메모리 장치 및 그것의 클록 분배 방법
US10210918B2 (en) 2017-02-28 2019-02-19 Micron Technology, Inc. Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
US10090026B2 (en) 2017-02-28 2018-10-02 Micron Technology, Inc. Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories
US10809790B2 (en) * 2017-06-30 2020-10-20 Intel Corporation Dynamic voltage-level clock tuning
US10063234B1 (en) * 2017-07-13 2018-08-28 Micron Technology, Inc. Half-frequency command path
US10269397B2 (en) 2017-08-31 2019-04-23 Micron Technology, Inc. Apparatuses and methods for providing active and inactive clock signals
US11049584B2 (en) 2019-01-15 2021-06-29 Samsung Electronics Co., Ltd. Integrated circuit memory devices having buffer dies and test interface circuits therein that support testing and methods of testing same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100245077B1 (ko) * 1997-04-25 2000-02-15 김영환 반도체 메모리 소자의 딜레이 루프 럭크 회로
JPH11110065A (ja) * 1997-10-03 1999-04-23 Mitsubishi Electric Corp 内部クロック信号発生回路

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