JP2001281704A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the aperture ratio of pixels of a reflection type display device without increasing the number of masks and without using black masks. SOLUTION: In this device, the high aperture ratio of a pixel is realized by arranging a pixel electrode 160 so that one part of it is overlapped on a gate wiring 143 and an island shaped source wiring 139 in a place shielding the light between pixels and by providing the color filter (lamination layer of red or red and blue) which is provided on a counter substrate in a place shielding the light of a TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their development is particularly urgent as switching elements for liquid crystal display devices.

In order to obtain a high-quality image in a liquid crystal display device, an active matrix type liquid crystal display device in which pixel electrodes are arranged in a matrix and a TFT is used as a switching element connected to each of the pixel electrodes has attracted attention. ing.

Active matrix type liquid crystal display devices are roughly classified into two types, a transmission type and a reflection type.

[0006] In particular, a reflective liquid crystal display device has an advantage that it consumes less power because it does not use a backlight, as compared with a transmissive liquid crystal display device. The demand as a direct-view display is increasing.

[0007] The reflection type liquid crystal display device utilizes the optical modulation of liquid crystal to reflect incident light on the pixel electrode and output the same to the outside of the device, and to reflect the incident light to the outside of the device. Is selected, the display of light and dark is performed, and an image is displayed by combining them. Generally, a pixel electrode in a reflective liquid crystal display device is
It is made of a metal material having high light reflectance such as aluminum and is electrically connected to a switching element such as a thin film transistor.

In a pixel structure of a conventional reflection type liquid crystal display device, three lines of a gate line (scanning line), a source line (signal line), and a capacitor line are respectively formed in a linear pattern. In addition, the source wiring is arranged in the row direction and the gate wiring is arranged in the column direction, and an interlayer insulating film is provided between the gate wiring and the source wiring to insulate the wirings from each other. In addition, the source line and the gate line partially cross each other, and the TFT is arranged near the crossing portion.

Conventionally, the pixel electrode is further provided with an interlayer insulating film covering the source wiring, and is formed on the interlayer insulating film. In the case of this structure, when the number of layers increases, the number of steps increases, which causes an increase in cost.

As another conventional structure, it is known that a pixel electrode is formed at the same time as a source wiring and a pixel electrode is formed between the source wirings. With this structure,
It was necessary to shield light between the source wiring and the pixel electrode with a black matrix.

Conventionally, light shielding between TFTs and between pixels is performed by a black matrix obtained by patterning a metal film formed of chromium or the like into a desired shape. However, in order to sufficiently shield the light with the black matrix, it is necessary to provide an interlayer insulating film between the black matrix and the pixel electrode for insulation. When the number of interlayer insulating films is increased in this way, the number of steps is increased, resulting in an increase in cost. In addition, it is disadvantageous in securing interlayer insulation. Further, conventionally, the number of processes and masks for forming the black matrix itself have been increased.

In addition, from the viewpoint of display performance, it is required to provide a pixel with a large storage capacity and a high aperture ratio. Since each pixel has a high aperture ratio, light use efficiency is improved, and power saving and downsizing of the display device can be achieved.

In recent years, the pixel size has been miniaturized, and a higher definition image has been demanded. Pixel size reduction is 1
The formation area of the TFT and the wiring occupying one pixel is increased, and the pixel aperture ratio is reduced.

Therefore, in order to obtain a high aperture ratio of each pixel within a specified pixel size, it is essential to efficiently lay out the circuit elements required for the pixel circuit configuration.

[0015]

As described above, in order to realize a reflection type liquid crystal display device having a high pixel aperture ratio with a small number of masks, a completely new pixel configuration which has not existed in the past is required.

An object of the present invention is to provide a reflective liquid crystal display device having a pixel structure realizing a high aperture ratio without increasing the number of masks and the number of steps. I do.

[0017]

In order to solve the above-mentioned problems of the prior art, the following measures have been taken.

The present invention is characterized by a pixel structure for shielding light between TFTs and pixels without using a black matrix. In order to shield light between pixels, a gate wiring and a source wiring are formed on the same insulating film (first insulating film), and a pixel electrode is overlapped with the gate wiring or the source wiring with the insulating film (second insulating film) interposed therebetween. To place. Further, in order to shield the TFT from light, a color filter (a red color filter or a laminated film of a red color filter and a blue color filter) is disposed as a light shielding film on the opposite substrate so as to overlap the TFT on the element substrate.

As shown in FIG. 1, one embodiment of the invention disclosed in this specification is a structure in which a first semiconductor layer and a second semiconductor layer are formed on an insulating surface, and the first semiconductor layer and the second semiconductor layer are formed on the insulating surface. A first insulating film on the first semiconductor layer and a first insulating film on the first insulating film;
A gate wiring overlapping the semiconductor layer, a capacitor wiring on the first insulating film located above the second semiconductor layer, an island-shaped source wiring on the first insulating film, the gate wiring, A second insulating film covering the capacitor wiring and the island-shaped source wiring, a connection electrode connected to the island-shaped source wiring and the first semiconductor layer on the second insulating film, 2 having a pixel electrode connected to the first semiconductor layer on the insulating film, wherein the pixel electrode overlaps the island-shaped source wiring with the second insulating film interposed therebetween. Semiconductor device.

In the above structure, a plurality of the island-shaped source wirings are arranged for each pixel, and the island-shaped source wirings are connected by the connection electrodes to form source wirings. And Further, the pixel electrode overlaps the gate wiring with the second insulating film interposed therebetween.

In another aspect of the invention, a first substrate comprises:
A semiconductor device which holds a liquid crystal between a second substrate and a substrate where the first substrate and the second substrate are bonded to each other, and includes a pixel portion including a thin film transistor over the first substrate. And a driving circuit, wherein the pixel portion includes a semiconductor layer, a first insulating film covering the semiconductor layer, a wiring on the first insulating film, a second insulating film covering the wiring, 2 having an electrode on an insulating film, and having, on the second substrate, red, blue, and green color filters corresponding to each pixel of the pixel portion, The laminated film of the red color filter and the blue color filter is
A light shielding film overlapping the thin film transistor on the substrate.

In the above structure, the wiring is a gate wiring, an island-shaped source wiring, and a capacitance wiring. In addition, a storage capacitor having the first insulating film as a dielectric is formed in a region where the capacitor wiring and the semiconductor layer overlap with the first insulating film interposed therebetween. The electrodes are a pixel electrode connected to the semiconductor layer and a connection electrode connected to the island-shaped source wiring.

In the above structure, the distance between the first substrate and the second substrate is held by a spacer made of a laminated film of the red color filter, the blue color filter, and the green color filter. It is characterized by having.

In another embodiment of the present invention, a first semiconductor layer and a second semiconductor layer are formed on an insulating surface as shown in FIG.
A first insulating film on the first semiconductor layer and the second semiconductor layer, a first electrode overlapping the first semiconductor layer on the first insulating film, A second electrode overlying the second semiconductor layer over the film, a source wiring over the first insulating film, a second insulating film covering the first electrode and the source wiring, A gate wiring connected to a first electrode on the film, the source wiring and the first wiring;
A connection electrode connected to the first semiconductor layer, and a pixel electrode connected to the first semiconductor layer on the second insulating film;
The semiconductor device is characterized in that the pixel electrode overlaps the source wiring with the second insulating film interposed therebetween.

In the above structure, the first electrode overlapping the first semiconductor layer is a gate electrode. Further, a storage capacitor is formed by using the first insulating film as a dielectric, the second semiconductor layer connected to the pixel electrode, and the second electrode connected to a gate wiring of an adjacent pixel. I have.

In the above-described configuration, an example was shown in which a storage capacitor using the first insulating film as a dielectric was used, but the present invention is not limited to the configuration of the storage capacitor.

According to another aspect of the present invention, a semiconductor layer on an insulating surface, a first insulating film covering the semiconductor layer, a source wiring on the first insulating film, and a first insulating film on the first insulating film. A gate electrode overlapping the semiconductor layer with a film interposed therebetween, a second insulating film covering the gate electrode and the source wiring, a gate wiring connected to the gate electrode on the second insulating film, 2. A semiconductor device comprising: a pixel electrode connected to the semiconductor layer on an insulating film.

In each of the above structures, the gate wiring is formed of a p-type doped with an impurity element imparting one conductivity type.
_{oly-Si, W, WSi X} , Al, Cu, Ta, C
It is characterized by being made of a film containing an element selected from r or Mo as a main component, an alloy film, or a laminated film thereof.

In each of the above structures, in order to reduce a parasitic capacitance, the second insulating film includes a first insulating layer containing silicon as a main component and a second insulating layer made of an organic resin material. It is characterized by.

According to another aspect of the present invention, there is provided a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film.
Wherein the gate electrode has a first conductive layer having a tapered end portion as a lower layer, a second conductive layer having a width smaller than that of the first conductive layer as an upper layer, The layer is formed of the second layer with the insulating film interposed therebetween.
A channel formation region overlapping the conductive layer, a third impurity region formed in contact with the channel formation region, a second impurity region formed in contact with the third impurity region, A semiconductor device including a first impurity region formed in contact with the impurity region.

The angle formed by the side slope of the first conductive layer with the horizontal plane (also referred to as a taper angle) is smaller than the angle formed by the side slope of the second conductive layer with the horizontal plane. Further, in this specification, for the sake of convenience, a side slope having a taper angle is referred to as a tapered shape, and a portion having a tapered shape is referred to as a tapered portion. The tapered portion also has an effect of blocking light from entering the channel formation region.

Further, in the above structure, the third impurity region overlaps with the first conductive layer with the insulating film interposed therebetween. The third impurity region is formed by doping in which an impurity element is added to a semiconductor layer through a first conductive layer having a tapered portion at an end portion and an insulating film. Also, in doping,
As the thickness of the material layer located on the semiconductor layer increases, the depth at which ions are implanted decreases. Therefore, the concentration of the impurity element added to the semiconductor layer changes due to the influence of the thickness of the tapered conductive layer. As the thickness of the first conductive layer increases, the impurity concentration in the semiconductor layer decreases, and as the thickness decreases, the concentration increases.

Further, in the above structure, the first impurity region is a source region or a drain region.

[0034] In the above structure, a region of the insulating film overlapping the second impurity region includes a tapered portion. The second impurity region is formed by doping in which an impurity element is added to a semiconductor layer through an insulating film. Therefore, the distribution of the impurity concentration of the second impurity region changes due to the influence of the tapered portion of the insulating film. As the thickness of the insulating film increases, the impurity concentration in the second impurity region decreases, and as the thickness decreases, the concentration increases. Note that the second impurity region is formed by the same doping as the third impurity region; however, since the second impurity region does not overlap with the first conductive layer, the impurity concentration of the second impurity region is lower than that of the third impurity region. Higher than impurity concentration. The width of the second impurity region in the channel length direction is the same as the width of the third impurity region, or is wider than the width of the third impurity region.

In the above structure, the TFT is n
It is characterized by being a channel type TFT or a p-channel type TFT. In the present invention, a pixel TFT is formed using an n-channel TFT. In addition, a driver circuit including a CMOS circuit using the n-channel TFT and the p-channel TFT is formed.

In the above structure, the semiconductor device is a reflection type liquid crystal display device.

The structure of the invention in a manufacturing process for realizing the above structure includes a first step of forming a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film on an insulating surface; A second step of forming a first insulating film on the semiconductor layer and the second semiconductor layer; a gate wiring overlapping the first semiconductor layer on the first insulating film; Forming a capacitor wiring on the first insulating film located above and an island-shaped source wiring on the first insulating film;
And a fourth step of forming a second insulating film covering the gate wiring, the capacitance wiring, and the island-shaped source wiring,
A fifth step of forming a connection electrode connecting the island-shaped source wiring and the first semiconductor layer on the second insulating film, and a pixel electrode overlapping the island-shaped source wiring. This is a method for manufacturing a semiconductor device, which is a feature.

Another aspect of the invention in a manufacturing process for realizing the above structure is a method for manufacturing a semiconductor device in which a liquid crystal is sandwiched between a pair of substrates, the method comprising forming a crystalline semiconductor film on a first substrate. A first step of forming a first semiconductor layer and a second semiconductor layer, a second step of forming a first insulating film on the first semiconductor layer and the second semiconductor layer, A gate wiring overlapping the first semiconductor layer on the film, a capacitor wiring on a first insulating film located above the second semiconductor layer, and an island-shaped source wiring on the first insulating film. Forming a second insulating film covering the gate wiring, the capacitor wiring, and the island-shaped source wiring; and forming the island-shaped source wiring on the second insulating film. A connection electrode connecting the first semiconductor layer and the first semiconductor layer, and the island-shaped source wiring Fifth forming a pixel electrode overlapping
Forming a red, blue, and green color filter corresponding to each pixel electrode on a second substrate, and simultaneously forming the red and blue color filters so as to overlap at least the first semiconductor layer. And a seventh step of bonding the first substrate and the second substrate to each other.

Another structure of the invention in a manufacturing process for realizing the above structure is a first method in which a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film are formed on an insulating surface.
A step of forming a first insulating film on the first semiconductor layer and the second semiconductor layer; and a first electrode overlapping the first semiconductor layer on the first insulating film. , The second
A third step of forming a second electrode overlapping the semiconductor layer and a source wiring, and a fourth step of forming a second insulating film covering the first electrode, the second electrode, and the source wiring Forming a gate wiring connected to the first electrode, a connection electrode connecting the first semiconductor layer and the source wiring, and a pixel electrode overlapping the source wiring on the second insulating film. And a fifth step of manufacturing a semiconductor device.

In the above structure, the second semiconductor layer connected to the pixel electrode overlaps with the second electrode connected to a gate wiring of an adjacent pixel with the first insulating film interposed therebetween. It is characterized by having.

Another aspect of the invention in a manufacturing process for realizing the above structure is a method for manufacturing a semiconductor device in which a liquid crystal is sandwiched between a pair of substrates, the method including forming a crystalline semiconductor film on a first substrate. A first step of forming a first semiconductor layer and a second semiconductor layer, a second step of forming a first insulating film on the first semiconductor layer and the second semiconductor layer, Forming a first electrode overlying the first semiconductor layer on the film, a second electrode overlapping the second semiconductor layer, and a source line; Forming a second insulating film covering the second electrode and the source wiring, a gate wiring connected to the first electrode on the second insulating film, the first semiconductor layer and the source. Forming a connection electrode for connecting a wiring and a pixel electrode overlapping the source wiring; Forming a red, blue, and green color filter corresponding to each pixel electrode on the second substrate, and simultaneously forming the red color filter and the green color filter so as to overlap at least the first semiconductor layer. The sixth step of forming a light-shielding film made of a laminated film with a blue color filter
And a seventh step of bonding the first substrate and the second substrate to each other.

Another structure of the invention in a manufacturing process for realizing the above structure includes a step of forming a semiconductor layer on an insulating surface, a step of forming an insulating film on the semiconductor layer, and a step of forming an insulating film on the insulating layer. Forming a first conductive layer and a second conductive layer, and adding an impurity element imparting one conductivity type using the first conductive layer and the second conductive layer as a mask to form a first impurity region; Forming a first conductive layer having a tapered portion by etching the first conductive layer and the second conductive layer, and forming a second conductive layer having a tapered portion; Then, an impurity element imparting one conductivity type is added to the semiconductor layer to form a second impurity region, and at the same time, the semiconductor layer is allowed to pass one conductivity type by passing through a tapered portion of the first conductive layer. Adding an impurity element to be imparted, toward an end of the semiconductor layer; Forming a third impurity region is an impurity concentration increases, a method for manufacturing a semiconductor device having a.

Another structure of the invention in a manufacturing step for realizing the above structure includes a step of forming a semiconductor layer on an insulating surface, a step of forming an insulating film on the semiconductor layer, and a step of forming an insulating film on the insulating layer. Forming a first conductive layer and a second conductive layer, and adding an impurity element imparting one conductivity type using the first conductive layer and the second conductive layer as a mask to form a first impurity region; Forming and etching the first conductive layer, the second conductive layer, and the insulating film to partially form a first conductive layer having a tapered portion, a second conductive layer, and a tapered portion. Forming the insulating film having, adding an impurity element imparting one conductivity type to the semiconductor layer by passing through the insulating film having a part of the tapered portion, and forming a second impurity region, The semiconductor is passed through the tapered portion of the first conductive layer. Adding an impurity element imparting one conductivity type layer, forming a third impurity region to increase the impurity concentration toward the end of the semiconductor layer, a method for manufacturing a semiconductor device having a.

[0044]

Embodiments of the present invention will be described below.

The reflective display device of the present invention has, as a basic configuration, an element substrate and a counter substrate adhered to each other with a predetermined gap therebetween, and an electro-optical material (a liquid crystal material or the like) held in the gap. And

[Embodiment 1] FIG. 1 shows a specific example of the pixel structure of the present invention.

As shown in FIG. 1, the element substrate includes a gate line 140 and a capacitor line 137 arranged in the row direction, a source line arranged in the column direction, and a pixel near an intersection of the gate line and the source line. A pixel portion including a TFT and a driver circuit including an n-channel TFT and a p-channel TFT are included.

However, the source wiring in FIG. 1 is composed of an island-shaped source wiring 139 arranged in the column direction and the connection electrode 16.
5 is connected. Note that the island-shaped source wiring 139 is formed in contact with the gate insulating film similarly to the gate wiring 140 (including the gate electrode 136) and the capacitor wiring 137. The connection electrode 165 is formed on an interlayer insulating film, like the pixel electrodes 167 and 160.

With such a configuration, light can be shielded between pixels by mainly overlapping the end portions of the pixel electrodes 160 with the island-shaped source wiring 139 and the gate wiring 140.

In order to shield the TFT on the element substrate from light, a red color filter, a laminated film of a red color filter and a blue color filter, or a laminated film of a red color filter, a blue color filter and a green color filter is used. Predetermined position of laminated film (position of TFT on element substrate)
Is provided on the opposite substrate.

With such a structure, the TFTs on the element substrate mainly correspond to the color filters (red color filters or a laminated film of the red color filter and the blue color filter, (A laminated film of a color filter, a blue color filter, and a green color filter).

The storage capacity of the pixel electrode 160 is the second capacity.
The insulating film covering the semiconductor layer 202 is made of a dielectric material, and is formed by the second semiconductor layer 202 connected to the pixel electrode 160 and the capacitor wiring 203.

Further, the number of masks required to form an element substrate having a pixel portion having the pixel structure shown in FIG. 1 and a driving circuit can be reduced to five. That is, the first one
A mask for patterning the first semiconductor layer 201 and the second semiconductor layer 202 is used.
04, a mask for patterning the capacitor wirings 137, 203, and the island-shaped source wirings 139, 206, 207;
The first is a mask for covering an n-channel TFT when an impurity element imparting p-type is added to form a p-channel TFT of a driver circuit. The fourth is a first semiconductor layer and a fourth semiconductor. The fifth mask is a mask for patterning the connection electrodes 165 and 205 and the pixel electrodes 160 and 167, which form contact holes respectively reaching the second semiconductor layer and the island-shaped source wiring.

As described above, with the pixel structure shown in FIG. 1, a reflective liquid crystal display device having a high pixel aperture ratio can be realized with a small number of masks.

[Embodiment 2] FIG. 10 shows a specific example of the pixel structure of the present invention.

As shown in FIG. 10, the element substrate includes gate wirings 1002 and 1012 arranged in the row direction, source wirings 1004 arranged in the column direction, and a pixel TFT near the intersection of the gate wiring and the source wiring. A pixel portion having
And a driver circuit having a channel TFT or a p-channel TFT.

Note that the gate wiring in FIG. 10 indicates a connection of an island-shaped gate electrode 1001 and an island-shaped capacitance electrode 1008 arranged in the column direction. Note that the island-shaped gate electrode 1001 is formed in contact with the gate insulating film similarly to the source wiring 1004 and the capacitor electrode 1008. In addition, the gate wirings 1002 and 1012
Are formed on an interlayer insulating film like the pixel electrodes 1006 and 1007 and the connection electrode 1005.

With such a structure, between the pixels, the end of the pixel electrode 1006 is mainly connected to the source line 10.
04 can be shielded from light.

In the same manner as in the first embodiment, the TFT of the element substrate is mainly formed of a color filter (a red color filter or a laminated film of a red color filter and a blue color filter) provided on the opposite substrate. Or a laminated film of a red color filter, a blue color filter, and a green color filter). Further, in the pixel structure of FIG. 10, since it is necessary to shield the gap between the gate wiring and the pixel electrode, the light may be shielded by using a color filter provided on the opposite substrate in this portion as well.

The storage capacity of the pixel electrode 1006 is determined by using an insulating film covering the second semiconductor layer as a dielectric,
06, a second semiconductor layer connected to the gate wiring 101,
2 and a capacitor electrode 1008 connected thereto.

Also, as in FIG. 1, the number of masks required to form an element substrate having a pixel portion having the pixel structure shown in FIG. 10 and a drive circuit can be reduced to five. That is, the first is a mask for patterning the first semiconductor layer and the second semiconductor layer, and the second is a gate electrode 100.
1. A mask for patterning the capacitor electrode 1008 and the source wiring 1004. The third sheet covers the n-channel TFT when an impurity element imparting p-type is added to form a p-channel TFT of a driver circuit. Mask for the
The fourth is a mask for forming contact holes reaching the first semiconductor layer, the second semiconductor layer, the gate electrode, the capacitor electrode, and the source wiring, respectively. The fifth is a connection electrode 100.
5, gate wirings 1002 and 1012, and pixel electrode 10
This is a mask for patterning 06 and 1007.

As described above, with the pixel structure shown in FIG. 10, a reflective liquid crystal display device having a high pixel aperture ratio can be realized with a small number of masks.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0064]

[Embodiment 1] In this embodiment, a method for simultaneously manufacturing a pixel portion and a TFT (an n-channel TFT and a p-channel TFT) of a driving circuit provided around the pixel portion on the same substrate will be described in detail. explain.

First, as shown in FIG. 2A, a substrate 100 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass is oxidized. A base film 101 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed. For example, a silicon oxynitride film 102a made of SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method has a thickness of 10 to 200 nm.
(Preferably 50-100 nm) and Si
Hydrogen oxynitride silicon film 1 made of H ₄ and N ₂ O
01b is 50 to 200 nm (preferably 100 to 150 nm).
(nm). In this embodiment, the base film 101 is used.
Is shown as a two-layer structure, but it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The island-like semiconductor layers 102 to 106 are formed of a semiconductor film having an amorphous structure by using a crystalline semiconductor film formed by a laser crystallization method or a known thermal crystallization method. The thickness of the island-shaped semiconductor layers 102 to 106 is 25 to 80 nm.
(Preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically, 20 to 400 mJ / cm ² ).
0 to 300 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and a pulse oscillation frequency of 1 is used.
-10kHz, laser energy density 300 ~
600 mJ / cm ² may (typically 350~500mJ / cm ²⁾ to. And a width of 100 to 1000 μm, for example 400
A laser beam condensed linearly in μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 80 to 98%.

Next, a gate insulating film 107 covering the island-shaped semiconductor layers 102 to 106 is formed. Gate insulating film 107
Uses a plasma CVD method or a sputtering method and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.5
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 0 to 500 ° C.

Then, a first conductive film 108 and a second conductive film 109 for forming a gate electrode are formed on the gate insulating film 107. In this embodiment, the first conductive film 10
8 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film is formed of W to a thickness of 100 to 300 nm.

The Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a film of tantalum nitride having a crystal structure close to that of the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm to form the a film, a Ta film of the α phase can be easily obtained. .

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target having a purity of 99.9999% or 99.99% and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μΩcm. Can be realized.

In this embodiment, the first conductive film 108
Is Ta and the second conductive film is W, but is not particularly limited.
Each of them may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than this embodiment is a combination in which the first conductive film is formed of tantalum nitride (TaN), the second conductive film is formed of W, and the first conductive film is formed of tantalum nitride (TaN). It is preferable that the second conductive film be formed using Al in combination, the first conductive film be formed using tantalum nitride (TaN), and the second conductive film be formed using Cu.

Next, resist masks 110 to 11 are used.
7, and a first etching process for forming an electrode and a wiring is performed. In this embodiment, the ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method, CF ₄ and Cl ₂ are mixed in an etching gas, and 1 Pa
500W RF (13.56MHz) to coil type electrode at pressure of
Power is supplied to generate plasma. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF ₄
When Cl and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. In this manner, the first shape conductive layers 119 to 126 (the first conductive layers 119a to 119a) each including the first conductive layer and the second conductive layer are formed by the first etching process.
26a and the second conductive layers 119b to 126b) are formed. Reference numeral 118 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 119 to 126 is etched by about 20 to 50 nm to form a thinned region.

In this embodiment, the first shape conductive layers 119 to 126 are formed by one etching, but it is needless to say that the conductive layers 119 to 126 may be formed by a plurality of etchings.

Then, a first doping process is performed to add an impurity element imparting n-type. (FIG. 2B) The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to ¹
The operation is performed at 00 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used.
In this case, the conductive layers 119 to 123 serve as a mask for the impurity element imparting n-type, and the first impurity regions 127 to 131 are formed in a self-aligned manner. The first impurity regions 127 to 131 have 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ^3.
Is added in the concentration range of n.

Next, a second etching process is performed as shown in FIG. Similarly, using the ICP etching method,
Mix CF ₄ , Cl ₂ and O ₂ in the etching gas
RF power (13.56 MH)
z) is supplied to generate plasma. Apply 50W RF (13.56MHz) power to the substrate side (sample stage)
A self-bias voltage lower than that in the first etching process is applied. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 133 to 140 (first Of the conductive layers 133a to 140a and the second conductive layers 133b to 140b). 132 is a gate insulating film, and the second shape conductive layers 133 to 13
The region not covered by 7 is further etched by about 20 to 50 nm to form a thinned area.

In this embodiment, the second shape conductive layers 133 to 14 shown in FIG.
Although 0 was formed, it is needless to say that it may be formed by a plurality of etchings. For example, after performing etching with a mixed gas of CF ₄ and Cl _2, CF _4, Cl ₂ and O
Etching with the mixed gas of ₂ may be performed.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is set to 1 × 10 ¹³ / cm ² , and a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. Form.
The doping is performed using the second conductive layers 133b to 137b as a mask for an impurity element.
Doping is performed so that the impurity element is also added to the region below a to 137a. Thus, the first conductive layer 133
a to 137a overlapping with third impurity regions 141 to 145
And a second impurity region between the first impurity region and the third impurity region.
Of impurity regions 146 to 150 are formed. The impurity element imparting n-type is 1 × 10 ¹⁷ to 1 in the second impurity region.
The concentration is set to be × 10 ¹⁹ atoms / cm ³ , and the concentration is set to be 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ in the third impurity region.

Further, here, an example in which the second doping process is performed while the resist mask is left as it is is described. However, the second doping process may be performed after removing the resist mask.

Then, as shown in FIG. 3B, a fourth impurity region 154 in which an impurity element of a conductivity type opposite to one conductivity type is added to the island-shaped semiconductor layer 104 forming the p-channel TFT. To 156 are formed. Using the second conductive layer as a mask for the impurity element, the impurity region is formed in a self-aligned manner. At this time, the entire surface of the island-shaped semiconductor layers 103, 105, and 106 forming the n-channel TFT is covered with resist masks 151 to 153. Although the impurity regions 154 to 156 are doped with phosphorus in different concentrations, respectively, diborane (B ₂ H ₆₎ is formed by ion doping using, 2 × 10 ²⁰ ~ the impurity concentration in that any region It is set to 2 × 10 ²¹ atoms / cm ³ . Actually, boron contained in the fourth impurity region is:
As in the case of the second doping treatment, the concentration of the impurity element added to the fourth impurity region changes due to the influence of the thickness of the conductive layer or the insulating film which is located on the semiconductor layer and has a tapered shape. ing.

Through the above steps, impurity regions are formed in the respective island-shaped semiconductor layers. Second overlapping with the island-shaped semiconductor layer
Of the conductive layers 133 to 136 function as gate electrodes.
Further, 139 functions as an island-shaped source wiring, 140 functions as a gate wiring, and 137 functions as a capacitor wiring.

In order to control the conductivity type in this way, FIG.
As shown in (C), a step of activating the impurity element added to each of the island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of ppm or less. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, 133-1
When the wiring material used for 40 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

Further, a heat treatment is carried out at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, the first interlayer insulating film 157 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 158 made of an organic insulating material is formed thereon. Next, an etching step for forming a contact hole is performed.

Then, the source wiring 1 for forming a contact with the source region of the island-shaped semiconductor layer in the drive circuit 406
59 to 161 and drain wirings 162 to 164 forming a contact with the drain region are formed. In addition, the pixel portion 4
07, the pixel electrodes 166 and 167 and the connection electrode 1
Form 65. (FIG. 4) Due to this connection electrode 165, the island-shaped source wiring 139 is
07 and the pixel TFT 404 are electrically connected. The pixel electrode 160 includes an island-shaped semiconductor layer (corresponding to the first semiconductor layer 201 in FIG. 1) corresponding to an active layer of the pixel TFT and an island-shaped semiconductor layer (second semiconductor in FIG. 1) forming a storage capacitor. (Corresponding to the layer 202). Note that the pixel electrode 167 is for an adjacent pixel.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03 and a pixel portion 407 including a pixel TFT 404 and a storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 40 of the drive circuit 406
Reference numeral 1 denotes a third impurity region 146 (G which overlaps with the channel formation region 168 and the second conductive layer 133 forming a gate electrode.
OLD region), a second impurity region 141 (LDD region) formed outside the gate electrode, and a first impurity region 127 functioning as a source region or a drain region. In the p-channel TFT 402, a channel formation region 169, a fourth impurity region 156 overlapping with the second conductive layer 134 forming a gate electrode, a fourth impurity region 155 formed outside the gate electrode, a source region or a drain. There is a fourth impurity region 154 functioning as a region. A channel formation region 170 and a second conductive layer 135 forming a gate electrode are formed in the n-channel TFT 403.
A third impurity region 148 (GOLD region) overlapping with the second impurity region 143 formed outside the gate electrode.
(LDD region) and a first impurity region 129 functioning as a source region or a drain region.

The pixel TFT 404 in the pixel portion has a channel forming region 171 and a second conductive layer 13 forming a gate electrode.
6, third impurity region 149 (GOLD region),
Second impurity region 144 formed outside gate electrode
(LDD region) and a first impurity region 130 functioning as a source region or a drain region. Also,
Semiconductor layer 1 functioning as one electrode of storage capacitor 405
The semiconductor layer 14 has the same concentration as the first impurity region 31.
5 has the same concentration as that of the third impurity region,
Is doped with an impurity element imparting n-type at the same concentration as that of the second impurity region, and a storage capacitor is formed by the capacitor wiring 137 and the insulating layer (the same layer as the gate insulating film) therebetween. I have. Further, an impurity element imparting n-type is added. Note that a storage capacitor 405 illustrated in FIG. 4 indicates a storage capacitor of an adjacent pixel.

In the top view of the pixel portion of the active matrix substrate manufactured in this embodiment, AA ′ in FIG. 4 corresponds to line AA ′ in FIG. That is, the island-shaped source wiring 139, the connection electrode 165, the pixel electrode 160,
167, the gate wiring 140, the gate electrode 136, and the capacitor wiring 137 are the same as those shown in FIG.

As described above, in the active matrix substrate having the pixel structure of the present invention, the source electrode and the connection electrode are formed in different layers, and the pixel electrode having a large area is formed by forming the pixel structure as shown in FIG. Can be arranged, and the aperture ratio can be improved.

Further, in the pixel structure of the present invention, the ends of the pixel electrodes are arranged so as to overlap the source wiring and the gate wiring so that the gap between the pixel electrodes can be shielded without using a black matrix. ing.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the island-shaped semiconductor layer pattern, the first wiring pattern (the gate wiring, the island-shaped source wiring). , A capacitor wiring), a mask pattern of an n-channel region, a contact hole pattern, and a second wiring pattern (including pixel electrodes and connection electrodes). As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below.
FIG. 5 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state shown in FIG. 4, an alignment film 567 is formed on the active matrix substrate shown in FIG. 4, and a rubbing process is performed.

On the other hand, a counter substrate 569 is prepared. The color filter layers 570 and 571 and the overcoat layer 573 are formed on the counter substrate 569. The color filter layer has a structure in which a red color filter layer 570 and a blue color filter layer 571 are formed over the TFT so as to also serve as a light shielding film. When the substrate of the first embodiment is used, at least the TFT, the connection electrode, and the pixel electrode need to be shielded from light. Therefore, a red color filter and a blue color filter are stacked so as to shield those positions from light. It is preferable to arrange them.

The red color filter layer 570 and the blue color filter layer 5 correspond to the connection electrodes 165.
71, a green color filter layer 572 is overlapped to form a spacer. The color filter of each color is a mixture of an acrylic resin and a pigment, and is formed with a thickness of 1 to 3 μm. This can be formed in a predetermined pattern using a photosensitive material and a mask. The height of the spacer can be set to 2 to 7 μm, preferably 4 to 6 μm by considering the thickness of the overcoat layer of 1 to 4 μm,
This height forms a gap when the active matrix substrate and the counter substrate are bonded to each other. The overcoat layer is formed of a light-curing or thermosetting organic resin material, for example, using polyimide or acrylic resin.

The arrangement of the spacers may be determined arbitrarily. For example, as shown in FIG. 5, it is preferable to arrange the spacers on the opposing substrate so as to be positioned on the connection electrodes. In addition, the driving circuit TF
The spacer may be arranged on the counter substrate with its position adjusted on T. The spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source line and the drain line.

After forming the overcoat layer 573, the counter electrode 576 is formed by patterning. After forming the alignment film 574, a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealant 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 5 is completed.

[Embodiment 3] In the embodiment 1, the example in which the gate wiring, the island-shaped source wiring, and the capacitor wiring are formed at the same time has been described. In the present embodiment, the step of forming the gate electrode by increasing one mask FIGS. 6 and 7 show an example in which an active matrix substrate is manufactured by separately performing steps of forming a gate wiring, a source wiring, and a capacitor wiring.

The gate electrode of the TFT shown in Embodiment 1 has a two-layer structure. Each of the first and second layers is formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, the first layer is formed of a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus.

The same applies to the case where a semiconductor film is used as the first layer of the gate electrode. However, an element selected from Ta, W, Ti, and Mo, or an alloy material or a compound material containing the above-described element as a main component has a large area. The resistance is about 10Ω or more, and is not necessarily suitable for manufacturing a display device having a screen size of 4 inch class or more. This is because, as the screen size increases, the length of wiring on the substrate necessarily increases, and the problem of signal delay time due to the influence of wiring resistance cannot be ignored.
Also, if the width of the wiring is increased to reduce the wiring resistance,
The area of the peripheral region other than the pixel portion increases, and the appearance of the display device is significantly impaired.

Therefore, in this embodiment, the gate wiring and the capacitor wiring are formed of a material mainly composed of aluminum (Al) or copper (Cu) for reducing the sheet resistance. That is, in this embodiment, the gate wiring is formed of a material different from that of the gate electrode.

A contact portion between the gate wiring 602 and the gate electrode 601 is provided outside the semiconductor layer as shown in FIG. Since Al may seep into a gate insulating film due to electromigration or the like, it is not appropriate to provide a gate wiring on a semiconductor layer. This contact does not require a contact hole, and is formed by overlapping a gate electrode and a gate wiring.

The manufacturing steps will be briefly described below.

First, according to the first embodiment, the same steps are used up to activation and hydrogenation. However, in the first embodiment, the electrodes and wirings indicated by 133 to 137 are simultaneously manufactured, but in the present embodiment, only the gate electrode 601 of each TFT is formed. The second electrode serving as one electrode of the storage capacitor
The semiconductor layers 600 and 612 are doped with an impurity element imparting n-type at the same concentration as the first impurity region.

Next, after the activation step, the gate wiring 60
2, 614, island-shaped source wirings 604, 616, 61
7. The capacitor wirings 603 and 613 and the wiring 608 of the driver circuit are formed of a low-resistance conductive material. The low-resistance conductive material is mainly composed of Al or Cu, and the gate wiring is formed of such a material. In this embodiment, an example using Al is shown, and an Al film containing 0.1 to 2% by weight of Ti is formed on the entire surface as a low-resistance conductive layer (not shown). The thickness is 200
To 400 nm (preferably 250 to 350 nm). Then, a predetermined resist pattern is formed and an etching process is performed to form gate wirings 602 and 614, island-shaped source wirings 604, 616 and 617, and capacitance wirings 603 and 61.
3. The wiring 608 of the driving circuit is formed. If these wirings are etched by wet etching using a phosphoric acid-based etching solution, they can be formed while maintaining the selectivity with the base.

Then, according to the first embodiment, a first interlayer insulating film and a second interlayer insulating film are formed. And the driving circuit 7
In step 06, a source wiring forming a contact with the source region of the island-shaped semiconductor layer and a drain wiring forming a contact with the drain region are formed. In the pixel portion 707, the pixel electrodes 606 and 607 and the connection electrodes 605 and 6
15 are formed. (FIG. 7) Due to this connection electrode 605, the island-shaped source wiring 604 is
17 and the pixel TFT 704 are electrically connected. Note that the storage capacitor 705 and the pixel electrode 607 belong to adjacent pixels. Further, an impurity element imparting n-type is added to the second semiconductor layer 600 functioning as one electrode of the storage capacitor 705 at the same concentration as that of the first impurity region. (The same layer as the gate insulating film) forms a storage capacitor.

As described above, the n-channel TFT 70
1, p-channel TFT 702, n-channel TFT 7
03 and a pixel portion 707 including a pixel TFT 704 and a storage capacitor 705 can be formed over the same substrate.

FIG. 6 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment.
The cross-sectional view cut along B 'corresponds to BB' shown in FIG.

According to the present embodiment, the gate wirings 602, 6
14. By forming the island-shaped source wirings 604, 616, 617 and the capacitance wirings 603, 613 from a low-resistance conductive material, the wiring resistance can be sufficiently reduced, and when combined with the second embodiment, the pixel portion (screen size) However, it is possible to realize an excellent display device of 4 inch class or more.

[Embodiment 4] In this embodiment, another example in which the TFT structure of the active matrix substrate is different from that of Embodiment 3 will be described with reference to FIG.

The active matrix substrate shown in FIG.
A logic circuit portion 855 having a first p-channel TFT 850 and a second n-channel TFT 851 and a second n
Sampling circuit section 8 composed of channel type TFT 852
A driving circuit 857 having a pixel circuit 56 and a pixel portion 858 having a pixel TFT 853 and a storage capacitor 854 are formed. The TFT of the logic circuit portion 855 of the driver circuit 857 forms a shift register circuit, a buffer circuit, or the like, and the TFT of the sampling circuit 856 is basically formed of an analog switch.

These TFTs are formed by providing a channel formation region, a source region, a drain region, an LDD region, and the like in the island-shaped semiconductor layers 803 to 806 on the base film 802 formed on the substrate 801. The underlayer and the island-shaped semiconductor layer were formed in Example 1.
It is formed in the same manner as described above. The gate electrodes 809 to 812 formed over the gate insulating film 808 are characterized by being formed so that the end portions have a tapered shape, and the LDD region is formed using this portion. Such a tapered shape is similar to that of the first embodiment in that W
The film can be formed by anisotropic etching technology.

The LDD region formed by using the tapered portion is provided for improving the reliability of the n-channel TFT, thereby preventing the deterioration of the on-current due to the hot carrier effect. In the LDD region, ions of the impurity element are accelerated by an electric field by an ion doping method, and are added to the semiconductor film through an end portion of the gate electrode and a gate insulating film near the end portion.

The first n-channel TFT 851 has a first LDD region 835 outside the channel forming region 832,
Second LDD region 834, source or drain region 8
33 are formed, and the first LDD region 835 is formed so as to overlap the gate electrode 810. Also, the first L
The n-type impurity element included in the DD region 835 and the second LDD region 834 is higher in the second LDD region 834 due to a difference in thickness of an upper gate insulating film and a gate electrode. The second n-channel TFT 852 has a similar structure, and includes a channel formation region 836, a first LDD region 839 overlapping with a gate electrode, a second LDD region 838, and a source or drain region 837. on the other hand,
The p-channel TFT 850 has a single drain structure, and impurity regions 829 to 831 to which a p-type impurity is added are formed outside the channel formation region 828.

In the pixel portion 858, an n-channel type TF
The pixel TFT formed of T has a multi-gate structure for the purpose of reducing off-current, and has a channel forming region 84.
0, a first LDD region 84 overlapping the gate electrode
Third, a second LDD region 842 and a source or drain region 841 are provided. The storage capacitor 854 includes an insulating layer formed of the same layer as the island-shaped semiconductor layer 807 and the gate insulating film 808, and a capacitor wiring 815.
An n-type impurity is added to the island-shaped semiconductor layer 807,
Since the resistivity is low, the voltage applied to the capacitor wiring can be kept low.

The interlayer insulating film is made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.
A first interlayer insulating film 816 having a thickness of 50 to 500 nm and a second interlayer insulating film 817 made of an organic insulating material such as polyimide, acrylic, polyimide amide, or BCB (benzocyclobutene) are formed. As described above, by forming the second interlayer insulating film with the organic insulating material, the surface can be satisfactorily planarized. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it has hygroscopicity and is not suitable as a protective film, it is preferable to form the first interlayer insulating film 816 in combination.

Thereafter, a resist mask having a predetermined pattern is formed, and a contact hole reaching a source region or a drain region formed in each of the island-shaped semiconductor layers is formed. The formation of the contact hole is performed by a dry etching method. In this case, CF ₄ , O ₂ ,
First, an interlayer insulating film made of an organic resin material is etched using a mixed gas of He, and then, the protective insulating film 146 is etched using CF ₄ and O ₂ as etching gases.
Further, by switching the etching gas to CHF ₃ and etching the gate insulating film in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed favorably.

Then, a conductive metal film is formed by sputtering or vacuum evaporation, and a resist mask pattern is formed.
Source and drain wirings 818-8 by etching
23, pixel electrodes 826 and 827, and connection electrodes 825 are formed. Thus, an active matrix substrate having a pixel portion having a pixel configuration as shown in FIG. 1 can be formed. Further, even when the active matrix substrate of this embodiment is used, the active matrix liquid crystal display device shown in Embodiment 2 can be manufactured.

[Embodiment 5] In this embodiment, another example in which the TFT structure of the active matrix substrate is different from that of Embodiment 3 will be described with reference to FIG.

The active matrix substrate shown in FIG.
A logic circuit portion 955 having a first p-channel TFT 950 and a second n-channel TFT 951 and a second n
Sampling circuit section 9 composed of channel type TFT 952
A driving circuit 957 having a pixel 56 and a pixel portion 958 having a pixel TFT 953 and a storage capacitor 954 are formed. The TFT of the logic circuit portion 955 of the driver circuit 957 forms a shift register circuit, a buffer circuit, or the like, and the TFT of the sampling circuit 956 is basically formed of an analog switch.

In the active matrix substrate shown in this embodiment, first, a base film 902 is formed on a substrate 901 with a thickness of 50 to 200 nm using a silicon oxide film, a silicon oxynitride film, or the like. Thereafter, island-like semiconductor layers 903 to 907 are formed from the crystalline semiconductor film formed by a laser crystallization method or a thermal crystallization method.
To form A gate insulating film 908 is formed thereover.
Then, the island-shaped semiconductor layer 9 forming the n-channel TFT is formed.
04, 905 and island-shaped semiconductor layer 907 forming a storage capacitor
Is selectively added at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ to impart an n-type impurity element typified by phosphorus (P).

Then, the gate electrodes 909 to 912, the gate wiring 914, the capacitor wiring 915, and the source wiring 913 are formed using a material containing W or Ta as a component. The gate wiring, the capacitance wiring, and the source wiring may be separately formed of a material having low resistivity such as Al as in the third embodiment. Then, 1 × 10 ¹⁹ to 1 × 10 ²¹ are formed in regions outside the island-shaped semiconductor layers 903 to 907 and the gate electrodes 909 to 912 and the capacitor wiring 915.
At a concentration of / cm ³ , an n-type impurity element typified by phosphorus (P) is selectively added. In this manner, the first n-channel TFT 951 and the second n-channel TFT 952 have channel forming regions 931 and 934 and LDD, respectively.
Regions 933, 936, source or drain region 93
2,935 are formed. The LDD region 939 of the pixel TFT 953 is formed in a self-aligned manner using the gate electrode 912, and is formed outside the channel forming region 937.
The source or drain region 938 is formed. First and second n
It is formed in the same manner as the channel type TFT.

As in the third embodiment, a first interlayer insulating film 916 made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, a polyimide, acrylic, polyimide amide, BCB (benzocyclo And a second interlayer insulating film 917 made of an organic insulating material such as butene. After that, a resist mask having a predetermined pattern is formed, and a contact hole reaching a source region or a drain region formed in each of the island-shaped semiconductor layers is formed. Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method to form source and drain wirings 918 to 923, pixel electrodes 926 and 927, and a connection electrode 925. Thus, an active matrix substrate having a pixel portion having a pixel structure as shown in FIG. 1 can be formed. Further, even when the active matrix substrate of this embodiment is used, the active matrix liquid crystal display device shown in Embodiment 2 can be manufactured.

The first n-channel TFT 951 of the logic circuit 955 has a GOL overlapping the gate electrode on the drain side.
The structure has a D region. The GOLD region alleviates a high electric field region generated near the drain region, prevents generation of hot carriers, and prevents deterioration of the TFT. The n-channel TFT having such a structure is suitable for a buffer circuit and a shift register circuit. On the other hand, the second n-channel TFT 952 of the sampling circuit 956 has a structure in which a GOLD region and an LDD region are provided on a source side and a drain side. The structure is intended to reduce the current. The pixel TFT 953 has an LDD structure, is formed with multiple gates, and has a structure for reducing off-state current. On the other hand, the p-channel type TFT is formed in a single drain structure, and has a channel forming region 92.
8, an impurity region 9 doped with a p-type impurity element
29 and 930 are formed.

As described above, in the active matrix substrate shown in FIG. 9, the TFTs constituting each circuit are optimized according to the specifications required by the pixel portion and the driving circuit, and the operating characteristics and reliability of each circuit are improved. In particular.

[Embodiment 6] In this embodiment, another example in which the pixel structure of the active matrix substrate is different is shown in FIGS.
This will be described with reference to FIG.

In this embodiment, an active matrix substrate having the pixel structure shown in FIGS. 10 and 11 can be obtained by changing only the mask pattern from that of the first embodiment.

The manufacturing process of this embodiment is almost the same as that of the first embodiment.

According to the first embodiment, the structure is formed up to the state shown in FIG. Next, the mask of the first embodiment is changed, and the gate electrode 1001, the capacitor electrode 1008, and the source line 100 are changed.
4 is formed by patterning.

The subsequent steps are performed in accordance with Embodiment 1, and FIG.
The processing up to the state is performed. Next, the mask of Example 1 is changed, and an impurity element imparting p-type is added to not only the p-channel TFT of the driving circuit but also the semiconductor layer serving as one electrode of the storage capacitor.

Next, according to the first embodiment, activation and formation of a first interlayer insulating film and a second interlayer insulating film are performed. Next, the contact holes are formed by changing the mask of the first embodiment. Next, the connection electrode 1 was changed by changing the mask of the first embodiment.
005, gate wirings 1002 and 1012, and pixel electrodes 1006 and 1007 are formed by patterning.

Thus, the pixel structure shown in FIG. 10 is obtained. 10 includes an island-shaped gate electrode 1001 and an island-shaped capacitance electrode 1008 arranged in the column direction.
Refers to what is connected. Also, a dotted line C in FIG.
A cross-sectional view taken along the line -C 'corresponds to a dotted line CC' in FIG. A sectional view taken along a dotted line DD ′ in FIG. 10 corresponds to a dotted line DD ′ in FIG.

In this embodiment, as shown in FIGS. 10 and 11, the island-shaped gate electrode 1001 is
4 and the capacitor electrode 1008 are formed on the gate insulating film at the same time. Further, the gate wiring 1002,
Reference numeral 1012 denotes the pixel electrodes 1006 and 1007, the connection electrode 1
Like 005, it is formed on the interlayer insulating film.

With such a structure, an end of the pixel electrode 1006 is mainly connected between the pixels by the source wiring 10.
04 can be shielded from light.

The storage capacity of the pixel electrode 1006 is such that the insulating film covering the second semiconductor layer is made of a dielectric material,
06, a second semiconductor layer connected to the gate wiring 101,
2 and a capacitor electrode 1008 connected thereto. The present embodiment is particularly effective for a panel having a small pixel size because the aperture ratio can be increased without providing the capacitor wiring as in the first embodiment.

In forming such a storage capacitor, it is preferable to add an impurity element imparting p-type to the second semiconductor layer.

This embodiment can be combined with the second embodiment.

[Embodiment 7] The structure of an active matrix type liquid crystal display device (FIG. 5) obtained by using Embodiment 2 is shown in FIG.
2 will be described with reference to the top view. Note that the same reference numerals are used for the portions corresponding to FIG.

A top view shown in FIG. 12A shows a pixel portion, a driving circuit, and an FPC (Flexible Printed Wiring Board: Flexib
le Printed Circuit)
3. Active matrix substrate 1 on which wiring 1104 and the like connecting external input terminals to the input section of each circuit are formed.
101 and a counter substrate 1 on which a color filter and the like are formed
102 are bonded together with a sealing material 568 interposed therebetween.

On the upper surface of the gate wiring side driving circuit 1105 and the source wiring side driving circuit 1106, a light shielding film 1107 formed by laminating a red color filter or a red and blue color filter on the counter substrate side is formed. The color filter 1 formed on the counter substrate side on the pixel portion 407
Reference numeral 108 denotes a color filter layer of each color of red (R), green (G), and blue (B) provided for each pixel. In actual display, a color display is formed by three colors of a red (R) color filter, a green (G) color filter, and a blue (B) color filter, and the arrangement of the color filters of these colors is arbitrary. Shall be.

FIG. 13 is a sectional view taken along line FF ′ of the external input terminal 1103 shown in FIG. The external input terminal is formed on the active matrix substrate side,
In order to reduce interlayer capacitance and wiring resistance and prevent a failure due to disconnection, a wiring 1109 formed in the same layer as a pixel electrode has a wiring 1111 formed in the same layer as a gate wiring with an interlayer insulating film 1110 interposed therebetween. Connecting.

The base film 1 is connected to the external input terminal.
An FPC including 112 and a wiring 1113 is attached with an anisotropic conductive resin 1114. Further reinforcing plate 111
5 increases the mechanical strength.

FIG. 13 (B) shows a detailed view of FIG.
2A is a cross-sectional view of the external input terminal shown in FIG. An external input terminal provided on the active matrix substrate side includes a wiring 1111 formed in the same layer as a gate wiring and a wiring 1109 formed in the same layer as a pixel electrode. Of course, this is an example showing the configuration of the terminal portion, and the terminal portion may be formed with only one of the wires. For example, when the wiring 1111 is formed using the same layer as the gate wiring, it is necessary to remove an interlayer insulating film formed thereover. Wiring 1109 formed in the same layer as the pixel electrode
According to the configuration shown in the first embodiment, the Ti film 1109a,
It has a three-layer structure of an Al film 1109b and a Sn film 1109c. FPC is base film 1112 and wiring 1
The wiring 1113 and the wiring 1109 formed in the same layer as the pixel electrode are made of a thermosetting adhesive 1114 and conductive particles 1116 dispersed therein. They are bonded with an adhesive to form an electrical connection structure.

On the other hand, FIG. 12B is a cross-sectional view of the external input terminal 1103 shown in FIG. Since the outer diameter of the conductive particles 1116 is smaller than the pitch of the wiring 1109, if the amount dispersed in the adhesive 1114 is set to an appropriate value, the wiring is electrically connected to the corresponding wiring on the FPC side without short-circuiting with the adjacent wiring. Can be formed.

The active matrix type liquid crystal display device manufactured as described above can be used as a display portion of various electronic devices.

This embodiment can be freely combined with any one of Embodiments 3 to 6.

[Embodiment 8] In this embodiment, another manufacturing method of the crystalline semiconductor layer for forming the semiconductor layer of the TFT of the active matrix substrate shown in Embodiment 1 will be described. In this embodiment, a crystallization method using a catalytic element disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 can be applied. An example in that case will be described below.

As in the first embodiment, a base film and an amorphous semiconductor layer are formed on a glass substrate to a thickness of 25 to 80 nm. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, an aqueous solution containing 10 ppm by weight of a catalytic element is applied by spin coating to form a layer containing the catalytic element. The catalytic elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), and platinum (P
t), copper (Cu), gold (Au) and the like. This catalyst element-containing layer 170 is formed by a sputtering method or a vacuum evaporation method in addition to the spin coating method, so that the layer of the catalyst element is 1 to 5 nm.
May be formed.

Then, in the crystallization step, first,
A heat treatment is performed at 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atom% or less. Then, using a furnace annealing furnace, 550-600 in a nitrogen atmosphere.
Thermal annealing is performed at 1 ° C. for 1 to 8 hours. Through the above steps, a crystalline semiconductor layer made of a crystalline silicon film can be obtained.

When an island-shaped semiconductor layer is manufactured from the crystalline semiconductor layer manufactured as described above, an active matrix substrate can be completed in the same manner as in the first embodiment. However, when a catalyst element that promotes crystallization of silicon is used in the crystallization step, a small amount (about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ) of a catalyst element remains in the island-shaped semiconductor layer. I do. Of course, the TFT can be completed in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing this catalytic element is phosphorus (P).
There is a means for utilizing the gettering action by

The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. Phosphorus required for gettering (P)
May be substantially the same as the impurity concentration of the high-concentration n-type impurity region.
The catalyst element can be segregated from the channel formation region of the FT and the p-channel TFT to the impurity region containing phosphorus (P) at the concentration. As a result, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ of a catalytic element segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

This embodiment can be freely combined with any one of Embodiments 1 to 7.

[Embodiment 9] C formed by carrying out the present invention
The MOS circuit and the pixel portion can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EC display). That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS.

FIG. 14A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 14B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6 and so on. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 14C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 14D shows a part of the head-mounted display (one side on the right), and includes a main body 2301, a signal cable 2302, a head fixing band 2303, and a display section 230.
4, including an optical system 2305, a display device 2306, and the like. The present invention can be used for the display device 2306.

FIG. 14E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 14F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 15A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904 and other driving circuits.

FIG. 15B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other driving circuits.

FIG. 15C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to eighth embodiments.

[Embodiment 10] In the embodiment 1, the first etching process for forming the conductive layer of the first shape was performed under one etching condition. However, the film thickness of the insulating film was reduced and the uniformity of the shape was reduced. In order to improve the etching, etching may be performed a plurality of times. In this embodiment, an example is described in which a first shape conductive layer is formed under two etching conditions in the first etching process.

Further, according to the present invention, a tapered shape is formed on both sides of a gate electrode, and LDDs are formed on both sides of a channel formation region.
Although a region is formed, this embodiment will be described with reference to FIG. 16 showing an enlarged cross-sectional view of one side near the gate electrode in a manufacturing process. The base film and the substrate are not shown for simplicity.

First, the same state as in FIG. 2A is obtained according to the first embodiment. However, in Example 1, Ta was used as the first conductive film, but in this example, TaN having extremely high heat resistance was used as the first conductive film. The first conductive film has a thickness of 20 to 100 nm, and the second conductive film has a thickness of 100 nm.
In this embodiment, the thickness may be 30 nm.
m TaN first conductive film and 370 nm thick W
A second conductive film made of was formed.

Next, a first shape mask 1205a made of resist is formed, and etching is performed by an ICP method to form a first shape second conductive layer 1204a. Here, a mixed gas composed of CF ₄ , Cl _2, and O ₂ is used as an etching gas having a high selectivity to TaN, so that the state shown in FIG. 16A can be obtained. Table 1 shows the relationship between various etching conditions and the etching rate of the second conductive layer (W), the etching rate of the first conductive layer (TaN), or the taper angle of the second conductive layer (W).

[0173]

[Table 1]

In the present specification, the term “taper angle” refers to
As shown in the upper right diagram of FIG. 16A, it indicates the angle formed between the horizontal plane and the side surface of the material layer.

The angle (taper angle α1) formed between the horizontal plane and the side surface of the second conductive layer (W) is determined by setting the first etching condition to, for example, any one of conditions 4 to 15 in Table 1. By doing so, it can be set freely within the range of 19 degrees to 70 degrees. The etching time may be appropriately set by the operator.

In FIG. 16A, reference numeral 1201 denotes a semiconductor layer; 1202, an insulating film; and 1203, a first conductive film.

Next, with the mask 1205a kept as it is, etching is performed under the second etching condition to form a first conductive layer 1203a having a first shape. When etching under the second etching condition,
The insulating film 1202 is also slightly etched to form the first shape insulating film 1202a. Here, a mixed gas composed of CF ₄ and Cl ₂ was used as an etching gas under the second etching condition. For example, any one of the conditions 1 to 3 in Table 1 may be used as the second etching condition. By performing the first etching treatment under the two etching conditions in this manner, a decrease in the thickness of the insulating film 1202 can be suppressed.

Next, a first doping process is performed. An impurity element which imparts one conductivity type to a semiconductor, in this case, phosphorus which imparts n-type is used by an ion doping method to form a first shape first conductive layer 1203a and a first shape second conductive layer 1204a. Is added to the semiconductor layer 1201 as a mask. (FIG. 16B) In FIG. 16B, the second
When the etching is performed under the etching condition of the above, the second conductive layer 1204a having the first shape is also slightly etched, but is minute, so that the second conductive layer 1204a is illustrated in the same shape as FIG.

Next, while the mask 1205a is left as it is, a second etching process is performed, and FIG.
The state shown in is obtained. In this embodiment, as the second etching process, after etching is performed under the first etching condition using a mixed gas of CF ₄ and Cl ₂ , the etching is further performed.
Etching was performed under the second etching condition using a mixed gas composed of F ₄ , Cl ₂ and O ₂ . These etching conditions may use any one of the conditions in Table 1 and appropriately set the etching time. Further, the width of each conductive layer in the channel length direction can be freely set according to the etching conditions. By the second etching process, the second shape mask 1205b and the second shape first conductive layer 1 are formed.
203b, a second-shaped second conductive layer 1204b, and a second-shaped insulating film 1202b are formed.

The second shape of the second conductive layer 1204b is as follows.
Forming a taper angle α2 larger than the taper angle α1,
The second shape first conductive layer 1203b forms a very small taper angle β. Note that the second shape of the first conductive layer 1203b can prevent deterioration of TFT characteristics due to intrusion of external light into a channel formation region. As in the present embodiment, although most of the light is reflected by the pixel electrode,
This is particularly effective in the case of a reflection type in which light applied to a gap between pixel electrodes may also be applied to a semiconductor layer.
Further, the taper angle γ is partially formed also in the second shape insulating film.

Next, after removing the mask 1205b,
A second doping process is performed. (FIG. 16D) In the second doping process, doping at a lower concentration than in the first doping process is performed. Here, phosphorus which imparts n-type is added to the semiconductor layer 1201 by an ion doping method using the second conductive layer 1204b having the second shape as a mask.

By the second doping process, impurity regions 1201a to 1201c are formed. Further, a semiconductor layer overlapping with the second conductive layer with the insulating film and the first conductive layer interposed therebetween is a channel formation region. Although not shown,
Impurity regions 1201a on both sides of the channel formation region
To 1201c are formed symmetrically.

In doping, as the thickness of the material layer located on the semiconductor layer increases, the depth at which ions are implanted decreases. Therefore, the first
The impurity region 1201c, which overlaps the conductive layer of FIG. 3, that is, the third impurity region (GOLD region) is affected by the tapered portion having the side surface with the taper angle β, and the concentration of the impurity element added to the semiconductor layer is reduced. Change. The impurity concentration decreases as the film thickness increases, and the impurity concentration increases as the film thickness decreases.

Similarly, the impurity region 1201b, that is, the second impurity region (LDD region) is affected by the thickness of the second shape insulating film 1202b, and the concentration of the impurity element added in the semiconductor layer is increased. Changes. That is, the concentration of the impurity element added to the semiconductor layer changes due to the influence of the film thickness of the tapered portion having the side surface of the taper angle γ and other tapered portions. Note that the impurity region 1201b which does not overlap with the first conductive layer has a higher concentration than the impurity region 1201c. Further, the impurity region 1201 in the channel length direction
The width of b is substantially equal to or wider than the impurity region 1201c.

The impurity region 1201a, that is, the first impurity region, becomes a high-concentration impurity region by being added by the second doping process in addition to the impurity concentration added by the first doping process, and becomes a source region or Functions as a drain region.

In the subsequent steps, the active matrix substrate may be manufactured according to the steps in FIG.

By the above method, the TFT of the pixel portion and the TFT of the driving circuit are formed.

This embodiment is similar to Embodiments 1 to 3 and 6 to 9
Can be freely combined with any one of the above.

Further, a gas mixture of SF ₆ and Cl ₂ was used in place of the etching gas (mixed gas of CF ₄ and Cl ₂ ) in this embodiment, or a mixture gas of CF ₄ , Cl ₂ and O ₂ was used. When a mixed gas of SF ₆ , Cl _2, and O ₂ is used instead of the gas, the selectivity with the insulating film 1202 is very high, so that film reduction can be further suppressed.

[0190]

According to the present invention, it is possible to realize a reflection type display device having a pixel structure realizing a high aperture ratio without increasing the number of masks and the number of steps.

[Brief description of the drawings]

FIG. 1 is a diagram showing a top view of a pixel portion of the present invention. (Example 1)

FIG. 2 is a diagram illustrating a manufacturing process of an active matrix substrate. (Example 1)

FIG. 3 is a diagram illustrating a manufacturing process of an active matrix substrate. (Example 1)

FIG. 4 is a diagram showing a manufacturing process of an active matrix substrate. (Example 1)

FIG. 5 is a diagram showing a cross-sectional structure diagram of an active matrix liquid crystal display device. (Example 2)

FIG. 6 is a diagram showing a top view of a pixel portion of the present invention. (Example 3)

FIG. 7 is a diagram showing a cross-sectional view of an active matrix substrate. (Example 3)

FIG. 8 is a diagram showing a cross-sectional view of an active matrix substrate. (Example 4)

FIG. 9 is a cross-sectional view of an active matrix substrate. (Example 5)

FIG. 10 is a top view illustrating a pixel portion of the present invention. (Example 6)

FIG. 11 is a cross-sectional view illustrating a pixel portion of the present invention. (Example 6)

12A and 12B are a top view and a cross-sectional view of an active matrix liquid crystal display device. (Example 7)

FIG. 13 is a cross-sectional view of an active matrix liquid crystal display device. (Example 7)

FIG. 14 illustrates an example of an electronic device. (Example 9)

FIG. 15 illustrates an example of an electronic device. (Example 9)

FIG. 16 is an enlarged cross-sectional view of a manufacturing step of an active matrix substrate.

Claims (32)

[Claims] A first semiconductor layer and a second semiconductor layer on an insulating surface; a first insulating film on the first semiconductor layer and the second semiconductor layer; A gate wiring overlapping with the first semiconductor layer; a capacitance wiring on the first insulating film located above the second semiconductor layer; an island-shaped source wiring on the first insulating film; A second insulating film covering the wiring, the capacitor wiring, and the island-shaped source wiring; and the island-shaped source wiring and the first wiring on the second insulating film.
A connection electrode connected to the semiconductor layer, and a pixel electrode connected to the first semiconductor layer on the second insulation film, wherein the pixel electrode sandwiches the second insulation film A semiconductor device overlapped with the island-shaped source wiring. 2. A semiconductor according to claim 1, wherein a plurality of said island-shaped source wirings are arranged for each pixel, and said island-shaped source wirings are respectively connected by said connection electrodes. apparatus. 3. The semiconductor device according to claim 1, wherein the pixel electrode overlaps the gate wiring with the second insulating film interposed therebetween. 4. A semiconductor device that holds liquid crystal between a first substrate, a second substrate, and a substrate on which the first substrate and the second substrate are bonded. A pixel portion including a thin film transistor and a driver circuit are provided over one substrate; the pixel portion includes a semiconductor layer, a first insulating film covering the semiconductor layer, wiring over the first insulating film, A second insulating film that covers the wiring, and an electrode on the second insulating film; and a red, blue, and green color filter corresponding to each pixel of the pixel portion on the second substrate. And a stacked film of the red color filter and the blue color filter on a second substrate is a light-shielding film overlapping with the thin film transistor on the first substrate. 5. The semiconductor device according to claim 4, wherein said wiring is a gate wiring, an island-shaped source wiring, and a capacitor wiring. 6. A storage capacitor according to claim 5, wherein said capacitor wiring and said semiconductor layer overlap each other with said first insulating film interposed therebetween, and a storage capacitor having said first insulating film as a dielectric is formed. A semiconductor device characterized by being performed. 7. The semiconductor device according to claim 4, wherein the electrodes are a pixel electrode connected to the semiconductor layer and a connection electrode connected to the island-shaped source wiring. Semiconductor device. 8. The device according to claim 4, wherein an interval between the first substrate and the second substrate is a distance between the red color filter, the blue color filter, and the green color filter. A semiconductor device which is held by a spacer made of a film. 9. A semiconductor device comprising: a first semiconductor layer and a second semiconductor layer on an insulating surface; a first insulating film on the first semiconductor layer and the second semiconductor layer; A first electrode overlapping the first semiconductor layer; a second electrode overlapping the second semiconductor layer on the first insulating film; a source wiring on the first insulating film; And a second insulating film covering the source wiring; a gate wiring connected to a first electrode on the second insulating film; a connection electrode connected to the source wiring and the first semiconductor layer; A pixel electrode connected to the first semiconductor layer on the second insulating film, wherein the pixel electrode overlaps the source line with the second insulating film interposed therebetween. Semiconductor device. 10. The semiconductor device according to claim 9, wherein the first electrode overlapping with the first semiconductor layer is a gate electrode. 11. The semiconductor device according to claim 9, wherein the first insulating film is used as a dielectric and the second semiconductor layer connected to the pixel electrode is connected to a gate wiring of an adjacent pixel. A semiconductor device, wherein a storage capacitor is formed with the second electrode. 12. The semiconductor device according to claim 9, wherein the first semiconductor layer includes an impurity element imparting one conductivity type to the semiconductor, and the second semiconductor layer includes the impurity element imparting one conductivity type. A semiconductor device comprising an impurity element imparting a conductivity type opposite to a mold to a semiconductor. 13. In any one of claims 1 to 12, wherein the gate wiring, poly-Si, W to which an impurity element imparting one conductivity type is doped, WSi _X, Al,
A semiconductor device comprising a film containing an element selected from Cu, Ta, Cr, or Mo as a main component or a stacked film thereof. 14. The second insulating film according to claim 1, wherein the second insulating film includes a first insulating layer containing silicon as a main component and a second insulating layer made of an organic resin material. A semiconductor device characterized by the above-mentioned. 15. A semiconductor device comprising: a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. The gate electrode has a first conductive layer having a tapered end portion as a lower layer, a second conductive layer having a width smaller than the first conductive layer as an upper layer, and the semiconductor layer having an insulating film interposed therebetween. A channel formation region overlapping with the second conductive layer, a third impurity region formed in contact with the channel formation region, and a second impurity region formed in contact with the third impurity region And the second
And a first impurity region formed in contact with the impurity region. 16. The semiconductor device according to claim 15, wherein said third impurity region overlaps with said first conductive layer with said insulating film interposed therebetween. 17. The method according to claim 15, wherein
The semiconductor device according to claim 1, wherein the first impurity region is a source region or a drain region. 18. The semiconductor device according to claim 15, wherein a region of the insulating film overlapping with the second impurity region includes a tapered portion. 19. The semiconductor device according to claim 15, wherein said TFT is an n-channel TFT. 20. The semiconductor device according to claim 15, wherein the TFT is a p-channel TFT. 21. A semiconductor layer on an insulating surface, a first insulating film covering the semiconductor layer, a source wiring on the first insulating film, and a first insulating film on the first insulating film. A gate electrode overlapping with the semiconductor layer, a second insulating film covering the gate electrode and the source wiring, a gate wiring connected to the gate electrode on the second insulating film, and a second insulating film on the second insulating film. A semiconductor device, comprising: a pixel electrode connected to the semiconductor layer. 22. The semiconductor device according to claim 1, wherein the semiconductor device is a reflection-type liquid crystal display device. 23. The semiconductor device according to claim 1, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, or an electronic game machine. Semiconductor device. 24. A first step of forming a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film on an insulating surface, and a step of forming a first semiconductor layer and a second semiconductor layer on the second semiconductor layer. A second step of forming a first insulating film; a gate wiring overlapping the first semiconductor layer on the first insulating film; and a capacitor wiring on the first insulating film located above the second semiconductor layer. A third step of forming an island-shaped source wiring on the first insulating film; and a fourth step of forming a second insulating film covering the gate wiring, the capacitor wiring, and the island-shaped source wiring. And a fifth step of forming a connection electrode connecting the island-shaped source wiring and the first semiconductor layer on the second insulating film, and a pixel electrode overlapping the island-shaped source wiring. A method for manufacturing a semiconductor device, comprising: 25. A method for manufacturing a semiconductor device in which liquid crystal is sandwiched between a pair of substrates, the method comprising forming a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film on a first substrate. A second step of forming a first insulating film on the first semiconductor layer and the second semiconductor layer; a gate wiring overlapping the first semiconductor layer on the first insulating film; A third step of forming a capacitance wiring on a first insulating film located above the second semiconductor layer and an island-shaped source wiring on the first insulating film; the gate wiring and the capacitance wiring And a fourth step of forming a second insulating film covering the island-shaped source wiring; and a connection electrode for connecting the island-shaped source wiring to the first semiconductor layer on the second insulating film; A fifth step of forming a pixel electrode overlapping the island-shaped source wiring; At the same time as forming the red, blue and green color filters corresponding to the respective pixel electrodes, a light-shielding film made of a laminated film of the red color filter and the blue color filter is overlapped with at least the first semiconductor layer. A sixth step of forming, and a seventh step of bonding the first substrate and the second substrate together
And a method for manufacturing a semiconductor device. 26. A first step of forming a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film on an insulating surface, and a step of forming a first semiconductor layer and a second semiconductor layer on the second semiconductor layer. (1) a second step of forming an insulating film; a first electrode overlapping the first semiconductor layer on the first insulating film; a second electrode overlapping the second semiconductor layer; A third step of forming; a fourth step of forming a second insulating film covering the first electrode, the second electrode, and the source wiring; and a step of forming the first electrode on the second insulating film. A fifth step of forming a gate wiring to be connected, a connection electrode connecting the first semiconductor layer and the source wiring, and a pixel electrode overlapping the source wiring. Method. 27. The semiconductor device according to claim 26, wherein the second semiconductor layer connected to the pixel electrode sandwiches the first insulating film and the second electrode connected to a gate wiring of an adjacent pixel. A method for manufacturing a semiconductor device, characterized by overlapping. 28. A method for manufacturing a semiconductor device in which liquid crystal is sandwiched between a pair of substrates, the method comprising forming a first semiconductor layer and a second semiconductor layer made of a crystalline semiconductor film on a first substrate. A first step, a second step of forming a first insulating film on the first semiconductor layer and the second semiconductor layer, and a first electrode overlapping the first semiconductor layer on the first insulating film And a third step of forming a second electrode overlapping the second semiconductor layer and a source wiring; and forming a second insulating film covering the first electrode, the second electrode, and the source wiring. A fourth step of forming, a gate wiring connected to the first electrode on the second insulating film, a connection electrode connecting the first semiconductor layer and the source wiring, and a pixel overlapping the source wiring. A fifth step of forming electrodes and red light corresponding to each pixel electrode on the second substrate. Forming a light-shielding film made of a laminated film of the red color filter and the blue color filter so as to simultaneously form the blue and green color filters and at least overlap the first semiconductor layer; Seventh bonding of the first substrate and the second substrate.
And a method for manufacturing a semiconductor device. 29. The semiconductor device according to claim 24, wherein the second insulating film is formed of a laminated film of a first insulating layer containing silicon as a component and a second insulating layer made of an organic resin material. A method for manufacturing a semiconductor device, comprising: 30. The semiconductor device according to claim 24, wherein the second insulating film includes a first insulating layer made of silicon oxide, silicon nitride, or silicon oxynitride, and polyimide, acrylic, polyamide, polyimide amide, or A method for manufacturing a semiconductor device, which is a stacked film with a second insulating layer made of benzocyclobutene. 31. A step of forming a semiconductor layer on an insulating surface; a step of forming an insulating film on the semiconductor layer; and a step of forming a first conductive layer and a second conductive layer on the insulating film. Forming a first impurity region by adding an impurity element imparting one conductivity type using the first conductive layer and the second conductive layer as a mask; and forming the first conductive layer and the second conductive layer. Forming a first conductive layer having a tapered portion and a second conductive layer by etching the conductive layer, and an impurity element imparting one conductivity type to the semiconductor layer through the insulating film. At the same time as forming the second impurity region, adding an impurity element imparting one conductivity type to the semiconductor layer by passing through the tapered portion of the first conductive layer, and adding the impurity element to an end of the semiconductor layer. Forming a third impurity region in which the impurity concentration increases toward The method for manufacturing a semiconductor device having a. 32. A step of forming a semiconductor layer on an insulating surface; a step of forming an insulating film on the semiconductor layer; and a step of forming a first conductive layer and a second conductive layer on the insulating film. Forming a first impurity region by adding an impurity element imparting one conductivity type using the first conductive layer and the second conductive layer as a mask; and forming the first conductive layer and the second conductive layer. Forming a first conductive layer having a tapered portion, a second conductive layer, and the insulating film partially having a tapered portion by etching the conductive layer and the insulating film; Adding an impurity element imparting one conductivity type to the semiconductor layer by passing through the insulating film having a second portion;
At the same time as forming the impurity region, an impurity element imparting one conductivity type is added to the semiconductor layer by passing through the tapered portion of the first conductive layer, and the impurity concentration is increased toward the end of the semiconductor layer. Forming a third impurity region to be increased.