JP2001246137A - Game machine, game system, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a game machine in which data stored with a backup power source can be erased. SOLUTION: A hall computer 90 is connected to a clear signal output circuit 84 mounted on a power source board 80 on each Pachinko machine via a signal line 90a. The clear signal output circuit 84 is connected to a main board 100 via a signal line 85a and to a dispense control board 200 via a signal line 85b. When a hall power source is turned on, a hall computer 90 outputs an initializing command to the clear signal output line 84 and which outputs a memory clear signal (erase signal) to the main board 100 and the dispense control board 200. Thus, backup data stored in the main board 100 and the dispense control board 200 can be erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine for controlling a game by a computer, a game system, and a recording medium on which a computer program for operating the game machine and the game system is recorded.

[0002]

2. Description of the Related Art Conventionally, as this type of gaming machine, for example, a pachinko machine shown in FIGS. 19 and 20 is known.
FIG. 19 is an explanatory front view of a conventional pachinko machine, and FIG.
FIG. 20 is an explanatory diagram of a back set of the pachinko machine shown in FIG.
As shown in FIG. 19, a conventional pachinko machine 500 stores a game board 502, a firing device 504 for firing a game ball to a game area of the game board 502, and a game ball to be supplied to the firing device 504. An upper tray 506 and a lower tray 508 for storing game balls that cannot be completely stored in the upper tray 506 are provided. In addition, on the game board 502, a special symbol display device 524, a prize winning opening 510, a right sleeve winning opening 512, a left sleeve winning opening 514, a first kind starting opening 516, a lower right winning opening 518, The lower left winning opening 520,
A special winning opening 526 is provided. Then, when the game ball fired from the firing device 504 wins the first kind starting port 516, the special symbol display device 524 displays the symbols in a fluctuating manner, and the stopped symbols are aligned with a predetermined symbol (for example, 777). A big hit occurs, and the special winning opening 526 is opened for a predetermined time. Then, when the opening time of the special winning opening 526 reaches a predetermined time or when the number of winnings to the special winning opening 526 reaches a predetermined number, the special winning opening 526 is closed. At this time, when a winning ball that has won the special winning opening 526 passes through a specific area 528 provided inside the special winning opening 526, the special winning opening 526 is continuously opened. In this manner, a predetermined number of rounds (for example, 16 rounds) can be played on the condition that the game ball passes through the specific area 528, with the round from opening to closing of the special winning opening 526 being one round.

[0003] Further, as shown in FIG.
The back set of 00 is provided with a back set mechanism plate 530, which includes a prize winning opening 510, a right sleeve winning opening 512, a left sleeve winning opening 514, a first type starting opening 516, a lower right winning opening 518, and a lower left winning prize. The winning ball that has won the mouth 520 or the like flows down the back ball path 532 along the path indicated by the arrow in the figure, gathers in the winning ball collecting gutter 524, and is guided to the winning ball detection switch 522. When the winning ball detection switch 522 detects a winning ball, a predetermined number of winning balls are paid out by a winning ball payout device (not shown). The winning ball detected by the winning ball detection switch 522 is increased by one by the operation of the winning ball cutting solenoid 534 each time the predetermined number of the winning balls are paid out.
Each piece is discharged downward.

[0004]

However, the conventional pachinko machine requires a structure such as a winning ball collecting gutter 524 and a winning ball cutting solenoid 534, so that the structure of the back set of the pachinko machine is complicated. Therefore, there has been a problem that the manufacturing efficiency is poor and it is difficult to save space. Further, since the winning ball cutting solenoid 534 frequently repeats the operation of discharging the winning balls one by one, there is also a problem that a failure due to abrasion or breakage of the operating portion is common. Further, the manufacturing cost of the above-mentioned structure is a factor that increases the manufacturing cost of the entire pachinko machine, which hinders the reduction of the manufacturing cost of the pachinko machine. Therefore, the present inventor has considered a configuration in which the number of winning balls and the number of winning balls are electrically stored in association with each other. According to this configuration, since the above-mentioned structure is unnecessary, the above-mentioned problems can be solved. However, the memorized number of winnings is lost due to power interruption or voltage drop, so even if power is restored, it is not possible to pay out the prize balls that should be paid out, which may be disadvantageous to the player. It turned out that there was. Therefore, the present inventor has considered a configuration in which a backup power supply is provided for holding a memory of the winning number when the power supply is cut off or the power supply voltage is reduced.

[0005] Further, if the power is cut off during the game due to a power failure or the like, when the power is restored, the game cannot be resumed from the game state at the time of the power cut, so that the player feels uncomfortable. In particular, when the power is cut off during a round based on a big hit or when the special symbol display device 524 variably displays the special symbol, the power supply is restarted from the middle of the round after the power is restored, or the special symbol is changed. Since the game cannot be restarted from the beginning, there is a risk that the player will be disadvantaged. Therefore,
The present inventor has considered a configuration in which a backup power supply for retaining storage of data for controlling a game is provided when the power supply is cut off or the power supply voltage decreases.

However, if the stored prize balls or winning spheres are rewritten due to static noise or fraudulent behavior, the power is cut off to erase the rewritten data. It turned out that the rewritten data could not be erased because the backup function worked. In addition, a jackpot may occur when a pachinko machine is tested and the final adjustment is performed before the pachinko hall is opened. In this case, prize ball data for paying out a predetermined number of prize balls is stored in the RAM. You. Therefore,
If the store is opened in such a state, a predetermined number of prize balls are paid out based on the memory in the RAM, and thus it has been found that the store may be disadvantaged. Furthermore, if the control data generated during the trial shooting before the store is opened is backed up, when the player plays the game at the time of opening the store, the game is started based on the backed up control data, which makes the player feel uncomfortable. There was a risk of learning.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to realize a gaming machine and a gaming system capable of erasing data stored by a backup power supply.

[0008]

In order to achieve the above object, according to the present invention, a control means for controlling a game and data generated during the game are stored. Storage means for storing the storage of the storage means by supplying a power supply for storage to the storage means when the voltage of the driving power supply supplied to the gaming machine drops to a predetermined voltage; Means, and erasing means for erasing the data stored and held by the memory holding means, wherein the control means can control the game by referring to the data stored and held by the memory holding means. A technical means called a gaming machine is used.

That is, data generated during the game, for example, data relating to the payout of prize balls (prize media) is stored in the storage means, and a pachinko machine (game machine) for paying out prize balls by referring to the stored data. In the case of), stored data may be rewritten due to static electricity noise or fraudulent activity. Even if such data is rewritten, the data is stored in the storage means by the erasing means. Since the data can be erased, it is possible to minimize the loss on the pachinko hall (game store) side due to the data rewriting. In addition, even if data related to the payout of prize balls (prize media) at the time of trial shooting before pachinko hall opening is backed up in the storage means, the backed up data can be erased by the erasing means, There is no fear that the store side will suffer any disadvantage due to the prize balls being paid out based on the backed up data. Furthermore, even if the control data for controlling the game generated during the trial shooting before the store is backed up, the backed up control data can be erased by the erasing means, so that the player can When playing a game, the game is started based on the backed-up control data, and the player does not feel uncomfortable.

According to the second aspect of the present invention, the control means for controlling the game, the storage means for storing data generated during the game, and the drive power supply voltage supplied to the game machine is reduced to a predetermined voltage. A storage holding unit that holds the storage of the storage unit by supplying power for storage holding to the storage unit when the storage unit decreases, and the control unit includes:
A gaming machine capable of controlling a game with reference to the data stored and held by the storage holding means, and an erasing means provided outside the gaming machine for erasing the data stored and held by the storage holding means And a technical means of a game system having the following.

That is, since the erasing means is provided outside the gaming machine, unlike the case where the erasing means is provided inside the gaming machine, the trouble of opening the inside of the gaming machine and operating the erasing means is reduced. Not required.

According to a third aspect of the present invention, in the gaming machine according to the first aspect, the erasing unit transmits an erasing signal for erasing the data stored and held by the storage holding unit to the storage unit. Technical means of doing so.

That is, by the software processing of transmitting the erasure signal to the storage means, the data stored and held by the storage means can be deleted.

According to a fourth aspect of the present invention, in the game system according to the second aspect, the erasing unit transmits an erasing signal for erasing the data stored and held by the storage and holding unit to the storage unit. Technical means of doing so.

That is, for example, when a plurality of gaming machines are installed, the data stored and held by the storage and holding means of each gaming machine is respectively processed by software processing of transmitting the erasing signal to each pachinko machine. Can be erased.

According to a fifth aspect of the present invention, in the gaming machine according to the third aspect, the erasing means transmits the erasing signal to the storage means when the driving power is turned on. Is used. According to a sixth aspect of the present invention, in the gaming system according to the fourth aspect, the erasing means includes a technical means for transmitting the erasing signal to the storage means when the driving power is turned on. Used.

That is, the data stored and held by the storage and holding means can be deleted by the software processing of transmitting an erasing signal to the storage means when the driving power of the gaming machine is turned on. When the drive power of each pachinko machine (game machine) is turned on when the power of the hall (game store) is turned on, the memory of each pachinko machine is stored by a simple operation of simply turning on the power of the pachinko hall at the time of opening the store. Each of the data stored and held by the holding means can be deleted. Therefore, even when busy preparing for the opening of the store, the data stored in each pachinko machine can be easily and quickly erased, which is convenient.

According to a seventh aspect of the present invention, in the gaming machine according to the third or fifth aspect, the erasing means comprises:
Technical means is used in which the erase signal is transmitted to the storage means when the drive power supply drops to a predetermined voltage. According to an eighth aspect of the present invention, in the gaming system according to the fourth or sixth aspect, the erasing means sends the erasing signal to the storage means when the driving power supply drops to a predetermined voltage. Use the technical means of transmitting.

That is, when the driving power supply drops to a predetermined voltage, the storage in the storage means is held by the storage holding means, and the storage can be erased by software processing of transmitting an erasure signal from the erasing means. . Therefore, by shutting off the drive power supply when closing stores,
Since the erasing signal is transmitted to the storage unit, the data stored and held by the storage and holding unit of each gaming machine can be deleted.

According to a ninth aspect of the present invention, in the gaming machine according to any one of the third, fifth and seventh aspects, the erasing means deletes the stored data. Technical means is used which includes erasing instruction means for instructing, and erasing executing means for outputting the erasing signal to the storage means on condition that erasing of the data is instructed by the erasing instruction means. Claim 1
According to the invention described in Item 0, in the gaming system according to any one of Claims 4, 6, and 8, the erasing means is an erasing instruction means for instructing erasing of the stored data. The gaming machine uses a technical means including: an erasure executing means for outputting the erasure signal to the storage means on condition that the data erasure is instructed by the erasure instruction means.

The erasure instruction means instructs erasure of data stored in the storage means, and the erasure execution means transmits an erasure signal to the storage means on condition that the erasure instruction means instructs erasure of the data. Output. In other words, the erasure signal is output directly to the erasure execution unit without directly transmitting the erasure signal to the storage unit, and the erasure execution unit outputs the erasure signal to the storage unit only after inputting the erasure instruction. For the purpose of preventing fraud, for example, pachinko machines (game machines)
Even if there is a regulation that prohibits the transmission of signals directly from the outside of the pachinko machine to the main board and the payout control board inside the pachinko machine, the pachinko machine must be temporarily It is possible to adopt a configuration in which an erasure instruction is output to the erasure execution means provided therein and an erasure signal is transmitted from the erasure execution means to the main board or the dispensing control board. Data can be erased.

According to an eleventh aspect of the present invention, in the gaming machine according to the ninth aspect, the erasure instruction storage means capable of storing the instruction from the erasure instruction means and outputting the stored instruction is provided. The erasure execution means includes a technical means for outputting the erasure signal to the storage means on condition that the instruction output from the erasure instruction storage means is input. Claim 1
According to a second aspect of the present invention, in the gaming system according to the tenth aspect, the gaming machine stores the instruction from the erasure instruction unit, and includes an erasure instruction storage unit capable of outputting the stored instruction. The erasure execution means includes a technical means for outputting the erasure signal to the storage means on condition that the instruction output from the erasure instruction storage means is input.

The erasure instruction storage means can store the erasure instruction output from the erasure instruction means and can output the stored erasure instruction. And the erasure execution means,
An erasure signal is output to the storage means on condition that the erasure instruction output from the erasure instruction storage means is input. That is, it is possible to store an erasure instruction and output the stored erasure instruction to the erasure executing means at a desired timing. Therefore, it is possible to set in advance so that the storage of the storage means is erased at a desired timing.

According to a thirteenth aspect of the present invention, in the gaming machine according to the ninth or eleventh aspect, the erasure instruction means stores the instruction in the erasure instruction storage means when the drive power is turned on. Use the technical means of outputting. According to a fourteenth aspect of the present invention, in the gaming system according to the tenth or twelfth aspect, the erasure instruction unit outputs the instruction to the erasure instruction storage unit when the driving power is turned on. Technical means of doing so.

In other words, the erasure instruction storage means can output the stored erasure instruction to the erasure execution means when the drive power is turned on. Therefore, the erasure instruction storage means performs a process of outputting the erasure instruction when the drive power is turned on. No need. In particular, if the erasure instruction is stored in the erasure instruction storage means before the drive power is turned on, the data stored in the storage means can be automatically erased when the drive power is turned on. There is no risk of forgetting to erase.

According to the invention described in claim 15, in claim 9,
14. The gaming machine according to claim 11, wherein the erasure instruction unit outputs the instruction to the erasure instruction storage unit when the driving power supply drops to a predetermined voltage, The erasure instruction storage means uses technical means for outputting the instruction to the erasure execution means when the drive power supply returns. According to a sixteenth aspect of the present invention, in the gaming system according to any one of the tenth, twelfth, and fourteenth aspects, the erasure instructing unit may be configured to reduce the drive power to a predetermined voltage. In such a case, a technical means is used in which the instruction is output to the erasure instruction storage means, and the erasure instruction storage means outputs the instruction to the erasure execution means when the driving power is restored.

When the drive power supply drops to a predetermined voltage, the erasure instruction means outputs an erasure instruction to the erasure instruction storage means, and when the drive power supply returns, the erasure instruction storage means outputs the erasure instruction to the erasure execution means. I do. Thus, the erasure executing means outputs the erasure signal to the storage means, so that the data stored in the storage means can be erased. That is, the reservation for erasing the data in the storage means when the drive power supply is restored,
Since it can be performed when the driving power supply drops to a predetermined voltage, there is no need to perform a process of outputting an erasure instruction when the driving power supply returns. Further, since the stored data can be automatically erased, there is no fear of forgetting to erase the data.

According to the seventeenth aspect, in the third aspect,
Claim 5, Claim 7, Claim 9, Claim 11, Claim 1
The gaming machine according to any one of claims 3 and 15, wherein the erasing means includes a designating means for designating a gaming machine which outputs the erasing signal, and The technical means of transmitting an erasure signal is used. In the game system according to the eighteenth aspect, in the gaming system according to any one of the fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth aspects, the erasing is performed. The means is provided with designating means for designating a gaming machine which outputs the erase signal, and uses technical means for transmitting the erase signal to the gaming machine designated by the designating means.

That is, since the data stored in the storage means of the designated gaming machine can be erased, for example, when an illegal act is performed on a specific gaming machine, only the gaming machine is designated. Since the data can be erased, there is no possibility of erasing data of other gaming machines.

According to the nineteenth aspect, in the third aspect,
Claim 5, Claim 7, Claim 9, Claim 11, Claim 1
The gaming machine according to any one of claims 3, 15 and 17, further comprising: a plurality of substrates provided with the storage means; and a power supply substrate for supplying power to the plurality of substrates. Technical means is used in which the erase signal is transmitted from the power supply board to each of the storage means. According to the twentieth aspect of the present invention, the fourth, sixth, eighth, tenth, twelfth, fourteenth, and fourteenth aspects of the present invention are described.
19. The gaming system according to claim 16, further comprising: a plurality of substrates including the storage unit; and a power supply substrate for supplying power to the plurality of substrates. Uses a technical means that is transmitted from the power supply board to each of the storage means.

That is, when a power supply board for supplying power to a plurality of boards having storage means is provided, the power supply board and each board are already connected by a line for supplying power or the like. Since the connection relationship between the substrates and each substrate is established, the line for transmitting the erase signal only needs to be added to the existing line, so that the cost required for transmitting the erase signal can be reduced.

[0032] In the invention described in claim 21, in the gaming machine according to claim 1, the erasing means is a connector for electrically disconnecting the storage power supply and the storage means. Use the technical means that there is. According to a twenty-second aspect of the present invention, in the gaming system according to the second aspect, the erasing means is a connector for electrically disconnecting the storage power supply and the storage means in a disconnectable manner. The technical means called.

That is, the power supply to the storage means is stopped by a relatively simple operation of disconnecting the connector for electrically disconnecting the power supply for storage and the storage means so that the storage means can be disconnected. The data stored in the means can be erased.

According to the twenty-third aspect of the present invention,
Claim 3, Claim 5, Claim 7, Claim 9, Claim 1
1, claim 13, claim 15, claim 17, and claim 19
22. A gaming machine according to claim 21, wherein said data is data relating to payout of a prize medium. Also, in the invention according to claim 24, claim 2, claim 4, claim 6, claim 8, claim 10, claim 12, claim 14, and claim 1 are provided.
6. In the gaming system according to any one of claim 18, claim 20, claim 20, and claim 22, the data is:
The technical means that the data is related to the payout of the prize medium is used.

That is, if the data held by the storage holding means is data relating to the payout of the prize medium, as described above, if the data is rewritten due to fraud, the prize medium is paid out illegally, Claims 1 and 2 may be disadvantageous on the side.
By using the technical means described in any of 2 above,
Since the data relating to the payout of the prize medium can be deleted, it is possible to minimize the loss on the hall side.

According to the twenty-fifth aspect of the present invention,
Claim 3, Claim 5, Claim 7, Claim 9, Claim 1
Claim 1, Claim 13, Claim 15, Claim 17, Claim 1
9. In the gaming machine according to any one of claims 21 and 23, a technical means is used in which the data is data for controlling a game. Claim 26
According to the invention described in the item (2), claim 2, claim 4, claim 6, claim 8, claim 10, claim 12, claim 14, claim 16, claim 18, claim 20, claim 22, and The gaming system according to claim 24,
The data uses technical means that is data for controlling a game.

That is, if the data held by the storage holding means is at least data for controlling a game, if the control data at the time of trial shooting before the store is backed up is performed as described above, the data is stored when the store is opened. Although the player feels a sense of discomfort that the game starts in the middle of the game, the data for controlling the game can be erased by using the technical means according to any one of claims 1 to 24. There is no fear of remembering.

According to the twenty-seventh aspect, in the first aspect,
Claim 3, Claim 5, Claim 7, Claim 9, Claim 1
Claim 1, Claim 13, Claim 15, Claim 17, Claim 1
In the game machine according to any one of claims 9, 21, 23, and 25, a technical means is used in which the power supply for storing and holding is a storage medium. Also,
According to the invention described in claim 28, claim 2, claim 4, claim 6, claim 8, claim 10, claim 12, or claim 1
4, Claim 16, Claim 18, Claim 20, Claim 2
2. In the gaming system according to any one of claims 24 and 26, a technical means is used in which the power source for storing and storing is a storage medium.

That is, since the power for holding the storage of the storage means is a power storage medium, even if the drive power supplied to the gaming machine fails, the power is supplied from the power storage medium to the storage means. Can be supplied. Note that the storage medium refers to a medium that can store electric charges, such as a capacitor or a battery.

According to the twenty-ninth aspect of the present invention, the control means for controlling the game, the storage means for storing data generated during the game, and the drive power supply voltage supplied to the game machine is reduced to a predetermined voltage. A storage holding means for holding the storage of the storage means by supplying a power for holding the storage to the storage means when the storage means is lowered; and an erasing means for erasing the data stored and held by the storage holding means. The control means is provided in a pachinko machine capable of controlling a game with reference to data stored and held by the storage and holding means, and is a recording medium on which a computer-readable program is recorded. A computer program for executing the erasing process for erasing the data stored and held by the storage holding unit is provided by the erasing unit. Using technical means that recorded by the recording medium.

That is, for example, as described in an embodiment of the present invention described later, a hall computer provided in a pachinko hall management room or the like reads a predetermined program from a recording medium such as a CD-ROM in which a computer program is recorded. It functions by reading a program, or an HDD (Hard Disk) on which the computer program is recorded.
Drive) or ROM, etc.
29. The gaming machine according to claim 1, which functions by reading a predetermined program from the recording medium, and uses a recording medium on which a computer program for executing the erasing process is recorded. Or a game system can be realized.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a gaming machine, a gaming system and a recording medium according to the present invention will be described below with reference to the drawings. In the following embodiments, a so-called first class pachinko machine will be described as an example of a gaming machine according to the present invention. First Embodiment [Overall Main Configuration] First, a main configuration of a pachinko machine according to the first embodiment will be described with reference to FIG. FIG. 1 is an explanatory diagram of the pachinko machine according to the first embodiment as viewed from the front. The pachinko machine 10 is provided with a front frame 11 so as to be openable and closable. A metal frame 12 is attached to the front frame 11 so as to be openable and closable. Mounted on Glass frame 1
A game board 14 is provided in the inside of 3. Front frame 11
A firing handle 15a for operating a firing motor (indicated by reference numeral 15e in FIG. 3) for firing a game ball to the game board 14 is rotatably attached to the lower right of the shooting handle 15a. A firing stop button 15b for stopping the firing operation is provided. On the left side of the game board 14, a guide rail 16 for guiding the shot game balls to the game area.
Is provided.

A keyhole decoration 17 having a keyhole 15 into which a key for opening and closing the glass frame 13 is inserted is provided on the right side of the front frame 11, and a frame lamp 18 a is provided above the front frame 11. A front plate 19 is provided under the glass frame 13, and a prize ball / lending ball supply port 20a to which a prize ball or a lending ball is supplied is formed on an upper left portion of the front plate 19, On the supply side of the prize ball / lending ball supply port 20a, an upper receiving tray 20 for storing prize balls or lending balls supplied from the prize ball / lending ball supply port 20a is attached. Below the upper tray 20, there is formed an outlet 21a for discharging a prize ball that has flowed in excess of the number that can be accommodated in the upper tray 20, a game ball discharged from the upper tray 20 by operating the upper tray ball removing lever 20b, and the like. Have been. On the discharge side of the discharge port 21a, a lower tray 21 for storing the game balls discharged from the discharge port 21a is provided. On the left side of the front frame 11, there is provided a device outside the gaming machine 22 such as a prepaid card unit having a slit 22a for inserting a prepaid card.

[Main Structure of the Game Board 14] Next, the game board 1
4 will be described with reference to FIG. A center case 30 is provided substantially at the center of the game board 14. The center case 30 has a prize entrance 31
And a normal symbol display device 34 including three LEDs, and 4 indicating the number of times the normal symbol display device 34 is operated.
A normal symbol storage display LED 35 composed of a plurality of LEDs, a special symbol display device 32 for variably displaying a plurality of symbols, for example, 0-9 special symbols on a liquid crystal display, and a display 4 for displaying the number of times the special symbol display device 32 has been started. And a special symbol storage display LED 36 composed of a plurality of LEDs.

On the left and right sides of the center case 30, a normal symbol operation gate 2 for operating the normal symbol display device 34 is provided.
6, 26 are provided. Below the center case 30, a first type starting port 27 having a function of operating the special symbol display device 32 is provided. Below the first type starting port 27, a stop symbol of the ordinary symbol display device 34 is provided. Ordinary electric accessory 28 that opens both wings when hit
Is provided. The opened ordinary electric accessory 28 has a function of starting the operation of the special symbol display device 32, similarly to the first type starting port 27. A variable winning device 40 which is activated when the stop symbol of the special symbol display device 32 hits the symbol is provided below the ordinary electric accessory 28.

The variable winning device 40 is provided with a large winning opening 41 in the form of a door which is opened when a hit occurs, and is openable. Are provided respectively. Further, inside the special winning opening 41, there is provided a specific area 42 having a function of continuously opening the special winning opening 41, and a specific area switch (reference numeral 42 in FIG. 3) for detecting a game ball passing through the specific area 42.
a) and a special winning opening switch (indicated by reference numeral 43a in FIG. 3) for counting the number P of game balls that have won the special winning opening 41.

In addition, the game board 14 has windmills 23, 23
, Sleeve entrance prize opening 24, 24, corner decoration lamp 18
b, 18b, a prize lamp 18c that lights up when a prize is won,
An out-of-ball lamp 18d that lights up when the ball runs out, side decoration lamps 18e, 18e, and an out port 45 for collecting game balls that did not win as out balls are provided.
Further, many nails 47 are driven into the game board 14, and the game balls fired on the game board 14 fall while dancing between the nails 47.

[Electrical Configuration of Pachinko Machine 10] Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. The pachinko machine 10 is provided with a main board 100, on which a microprocessor 110 is mounted. The microprocessor 110 has a main CP for executing game control.
U112 and a ROM 11 in which various control programs for the main CPU 112 to execute various controls are recorded.
And a RAM 116 for temporarily storing various data such as a control program read from the ROM 114 when the main CPU 112 executes various control programs and data relating to a big hit occurring during a game. Further, the RAM 116 backs up a command transmitted from the main CPU 112 to each board when the power is cut off due to a power failure or the like.

The following components are electrically connected to the main substrate 100. Power supply board 80, payout control board 200 for controlling payout of award balls, etc., special symbol display device 3
2. A lamp control device 75 for controlling lamps provided on the game board 14, a sound control device 79 for controlling a sound reproduction device (not shown) for reproducing sound effects during a game, etc., a first-type start of a game ball. A first-type start-up switch 27a for detecting the passage of the mouth 27, a game frame information terminal for transmitting game board information on winnings, big hits, etc. to a hall computer 90 (FIG. 5) provided in a pachinko hall management room or the like. The board 52, the board relay board 51, and the game frame relay board 55.

The payout control board 200 is equipped with a microprocessor 210 which operates by inputting a control command sent from the main board 100. The microprocessor 210 has a sub CPU which controls payout of award balls and the like.
212, a ROM 214 in which various control programs for the sub CPU 212 to execute control such as payout of prize balls, and a control program read from the ROM 214 when the sub CPU 212 executes various control programs and a game And a RAM 216 for temporarily storing various data such as the number of prize balls generated in the RAM. The payout control board 200 is electrically connected to the power supply board 80, the CR connection board 56, the firing motor drive board 15c for driving the firing motor 15e, the game frame information terminal board 52, and the payout relay board 55. I have.

The game frame relay board 53 has a full detection switch 2 for detecting that the lower tray 21 is full of prize balls.
1b and the sensor relay board 54 are electrically connected. The sensor relay board 54 is electrically connected to the prize ball payout sensors 62a and 62b and the payout relay board 55 provided in the prize ball unit 62. The prize ball unit 62
Prize ball payout sensors 62a, 62b and prize ball payout motor 6
2c. There are two prize ball payout mechanisms for efficiently paying out prize balls, and each payout mechanism is driven by a prize ball payout motor 62c. The prize ball payout sensor 62a is provided in one mechanism, and the prize ball payout sensor 62b is provided in the other mechanism. Detection signals from the prize ball payout sensors 62a and 62b are transmitted from the sensor relay board 54 to the main board 100 via the game frame relay board 53.
The CPU 120 counts the number of paid-out balls based on the signal.

The payout relay board 55 is electrically connected to a ball-off switch 61 for detecting that there is no longer a ball, a prize-ball payout motor 62c, and a ball-for-ball unit 63. The following components are electrically connected to the board-surface relay board 51. Ordinary electric accessory solenoid 28a for opening and closing the ordinary electric accessory 28, ordinary symbol display device 34, symbol actuation opening switch 26a, large winning opening switch 43a, and sleeve winning opening switch 24 for detecting winning in the sleeve winning opening 24.
a, a lower prize port switch 29a for detecting a prize to the lower prize port 29, a lower prize port switch 31a for detecting a prize to the lower prize port 31;

The special winning area solenoid 42b, the special winning area solenoid 43b, and the specific area switch 42a are electrically connected to the special winning opening relay board 50. The power supply board 80 is electrically connected to the CR connection board 56,
The CR connection board 56 is electrically connected to the gaming machine external device portion 22 including a frequency display board for displaying the remaining frequency of the prepaid card and a device for reading the prepaid card. The power supply board 80 is a 24 V AC (50 Hz / 6
(0 Hz) from the main power supply 70.

[Main Hardware Configuration] Next, FIG. 4 shows the main hardware configuration of the pachinko machine 10.
This will be described with reference to FIG. Here, the main CPU 112 of the main board 100 and the sub C of the payout control board 200
The hardware configuration of the interface between the PUs 212 will be described as an example. Main CP of main board 100
Various control commands output from U112
Output to the output port 120 via the PU bus 118;
The output various control commands are temporarily stored in the output buffer 126 via the main CPU parallel output port 124, and then stored in the input buffer 220 connected to the sub CPU 212. And the main CPU
The transfer signal output from the main CPU bus 1
When the trigger signal (TRG2) 226 of the sub CPU 212 is input from the sub-CPU 212 via the output port 122, the output buffer 128, and the input buffer 222, various control commands accumulated in the input buffer 220 are transmitted to the sub-CPU 212.
The data is input to the input port 224 of the sub CPU 212 via the parallel input port 228. And the sub CPU
The 212 performs analysis such as what the captured various control commands mean, and outputs an award ball payout command to the award ball unit 62 based on the analysis result. Note that the main CPU 1 of the main board 100
The hardware configuration between the sub-CPU 12 and the sub CPU mounted on a board other than the payout control board 200 is the same as the above-described configuration.

[Main Configuration of Power Supply Board 80, Power Supply Board 80
Next, the main configuration of the power supply board 80 and the connection relation between the power supply board 80 and each board will be described with reference to FIGS. FIG. 5 is an explanatory diagram showing a main configuration of the power supply board 80 together with a connection relationship with each substrate, and FIG. 6 is an explanatory diagram showing details of a connection relationship between the power supply substrate 80 and each substrate. As shown in FIG. 5, the 24 V AC current supplied from the main power supply 70 is converted to 32 V DC by the rectifier circuit 81 via the fuse F <b> 1 and supplied to the main board 100 and the payout control board 200, respectively. The 32 V direct current is supplied to the DC / DC converter 82.
The voltage is changed to 12V, and supplied to the main board 100, the special symbol display device 32, the lamp control device 75, the voice control device 79, and the payout control board 200, respectively. Also,
The AC 24 V of the main power supply 70 is connected to the CR through the fuse F2.
It is supplied to the connection board 56.

The 12 V DC supplied to the main board 100 is supplied to the board relay board 51 (FIG. 3), and drives the ordinary electric accessory solenoid 28a, the ordinary symbol display device 34 and the like. The 12V direct current supplied to the special symbol display device 32 drives the liquid crystal and the like of the special symbol display device, and the 12V direct current supplied to the lamp control device 75 uses LEDs such as the corner decoration lamp 18b and the winning lamp 18c. Turn on or blink lamps. The 12 V DC supplied to the audio control device 79 drives a speaker via an audio circuit,
The 12 V DC supplied to the payout control board 200 is supplied to the prize ball unit 62 and the ball lending unit 63 via the payout relay board 55, and drives the prize ball payout motor 62c and the like.

The DC current converted to 12V by the DC / DC converter 82 is converted to 5V by the DC / DC converter 83. The DC of 5V is supplied to the clear signal output circuit 84, the main board 100, and the special symbol display. It is supplied to the device 32, the lamp control device 75, the sound control device 79, and the payout control board 200, respectively. Main board 100
5V DC supplied to the microprocessor 110
The DC power of 5 V supplied to the payout control board 200 as the driving power supply of FIG. 3 serves as the driving power supply of the microprocessor 210 (FIG. 3). Also, special symbol display device 32,
The 5 V DC supplied to the lamp control device 75 and the audio control device 79 serves as a drive power supply for a microprocessor (not shown) provided in each device. That is, the power of each board is all supplied from a single power board 80, and the power board 80 controls the power of each board. For this reason, as compared with the conventional configuration in which the pressure is changed on each substrate,
Space for the transformer circuit can be omitted on each substrate. Further, even if the substrates use the same power supply voltage, the circuit design for supplying power can be simplified as compared with a conventional substrate in which the voltage is changed for each substrate.

As shown in FIG. 6, the power supply board 80 has no. 1-7 of 7
A pin connector CN2a is attached, and the connector CN2a is connected to the connector CN1 attached to the main board 100 by a cable L1. Cable L
A terminal CN2b for connecting to the connector CN2a is attached to one end of the connector 1, and a terminal (not shown) for connecting to the connector CN1 on the main board 100 is attached to the other end. In addition, the power supply board 80 has the No. for electrically connecting to the payout control board 200. 1-7 of 7
A pin connector CN3a is attached, and the connector CN3a is connected to the payout control board 2 by a cable L2.
00 is connected to the connector CN1 attached to the connector 00. A terminal CN3b for connection to the connector CN3a is attached to one end of the cable L2, and a terminal (not shown) for connection to the connector CN1 on the payout control board 200 is attached to the other end. .

Further, the power supply board 80 includes a connector CN.
7a, CN4a, CN5a, CN6a, CN1a are attached. The connector CN7a is connected to the CR connection board 56 by a cable L3.
Is connected to a connector CN7a at one end.
7b is attached, and a terminal (not shown) for connecting to the connector CN2 on the CR connection board 56 side is attached to the other end. The connector CN4a is connected to the cable L4
Is connected to a special symbol control board 32a provided in the special symbol display device 32, a terminal CN4b for connecting to the connector CN4a is attached to one end of the cable L4, and a special symbol control board is attached to the other end. A terminal (not shown) for connecting to the connector CN1 on the 32a side is attached.

The connector CN5a is connected to a lamp control board 75 provided in the lamp control device 75 by a cable L5.
a terminal CN5b for connecting to the connector CN5a is attached to one end of the cable L5, and the connector CN on the lamp control board 75a side is attached to the other end.
A terminal (not shown) for connecting to the terminal 1 is attached. The connector CN6a is connected to a voice control board 79a provided in the voice control device 79 by a cable L6. A terminal CN6b for connecting to the connector CN6a is attached to one end of the cable L6, and the other end is connected to the other end. A terminal (not shown) for connecting to the connector CN1 on the audio control board 79a side is attached. Connector C
N1a is connected to the main power supply 70 by a power cord L7, and one end of the power cord L7 has a connector CN1a.
A terminal CN1b for connection to the terminal is attached.

Since the cables L4 to L6 have the same number of terminal pins, a common cable can be used.
Therefore, it is possible to save the trouble of selecting a cable as compared with a case where cables having different numbers of terminal pins are used, so that the cable connection processing can be performed easily and in a short time. In addition, since the number of cables that can be used in common is large, the manufacturing cost can be reduced as compared with the case where many types of cables having different numbers of terminal pins are manufactured.

[Data Backup Function] Here, a function of backing up data stored in the RAM 116 built in the microprocessor 110 and the RAM 216 built in the microprocessor 210 is shown in FIGS.
7 (A) and FIG. 18 (A). FIG.
7 (A) shows the power supply board 80 and the microprocessor 110
FIG. 18A is an explanatory diagram showing a connection relationship between the power supply board 80 and the microprocessor 210. In the following description, the sub-substrate refers to each substrate other than the main substrate 100 and the payout control substrate 200.

As shown in FIG. 17A, the main substrate 100
Is connected to a voltage monitoring IC 120 for monitoring voltages of 12 V and 5 V, and the voltage monitoring IC 120
The output of 120 is the NMI of microprocessor 110
(Non-maskable interrupt) terminal. As shown in FIG. 18A, a payout control board 200 is also provided with a voltage monitoring IC 220 for monitoring voltages of 12 V and 5 V. The output of the voltage monitoring IC 220 is a microprocessor 210 NM
It is connected to the I (non-maskable interrupt) terminal. Further, a voltage monitoring IC (not shown) for monitoring 5 V is mounted on each sub-substrate, and each voltage monitoring IC is connected to a microprocessor mounted on the sub-substrate. I have.

As shown in FIG. 5, a diode D1 is connected in series to a power supply line 83a connecting the DC / DC converter 83 and the payout control board 200, and a capacitor C1 is connected to the output side of the diode D1. (A power source for storing data) are connected in parallel. DC / DC
A diode D2 is connected in series to a power supply line 83b connecting the converter 83 and the main board 100, and a capacitor C2 is connected to the output side of the diode D2.
(A power supply for storing data) are connected in parallel. Capacitors C1 and C2 are charged by a DC current of 5 V supplied from DC / DC converter 83, respectively.

The discharge current of the capacitor C1 is as shown in FIG.
As shown in (A), the power is supplied to the built-in RAM backup power supply terminal VBB of the microprocessor 110 via the backup power supply line L1a in the cable L1 (FIG. 6). That is, when the supply of AC 24 V from the main power supply 70 (FIG. 5) is stopped due to a power failure or the like, the power supply voltage monitoring IC 120 (FIG. 17A) detects a drop in the power supply voltage and replaces the DC / DC converter 83. Since the discharge current of the capacitor C1 is supplied to the microprocessor 210, the data related to the winning ball payout stored in the RAM 216 is backed up (stored and stored).

The discharge current of the capacitor C2 is as shown in FIG.
As shown in FIG. 8A, the microprocessor 21 is connected via the backup power supply line L2a in the cable L2.
0 is supplied to the internal RAM backup power supply terminal VBB. That is, when the supply of 24 V AC from the main power supply 70 (FIG. 5) is stopped due to a power failure or the like, the power supply voltage monitoring I
C220 (FIG. 18A) detects a drop in the power supply voltage,
Since the discharge current of the capacitor C2 is supplied to the microprocessor 110 instead of the DC / DC converter 83, the data stored in the RAM 116 is backed up (stored and stored). The data to be backed up includes, for example, the number of times the big winning opening is opened in the game when a big hit occurs, the number of winnings in the big winning opening, the number of rounds, the reach state before the big hit occurs, the pattern variation mode, the stop symbol The data generated during the game, such as the number of operating memories of the ordinary symbol display device 34, the number of starting memories of the special symbol display device 32, the reliability, the profitability, the probability at the time of probability variation, the symbol variation start interval during working hours, or , Main CP when power off
The control command (control data) and the like transmitted from the U112 to the payout control board 200 and each sub-board. In addition,
Assuming that the degree of reliability is, for example, a case where “7” is displayed in each of the three display areas of the special symbol display device 32 as a big hit, “7” is displayed in the two display areas, and the remaining one is displayed. "7" means the probability of stopping in the area.
Also, the profit level is the degree of profit that the player can obtain,
For example, when there is a difference in the number of prize balls to be paid out according to the type of big hit, it means the probability of occurrence of a big hit in which the most prize balls are paid out. In this embodiment, the capacitor C1 is an electric double layer capacitor with a nominal capacitance of 0.1 F and a rated voltage of 5.5V. The cables L1 to L6 are FPCs (flexible print circuits).

[Main control from power-on to power-off]
Next, main control from power-on to power-off will be described with reference to FIGS. FIG. 7 is a flowchart showing a flow of the RAM initialization processing 1 executed by the hall computer 90. FIG. 8 is a flowchart illustrating a flow of a program start process executed by the sub CPU 212, and FIG. 9 is a flowchart illustrating a flow of a main program process executed by the sub CPU 212. FIG. 10 is a flowchart showing the flow of a command input process executed by the sub CPU 212, and FIG.
3 is a flowchart illustrating a flow of an NMI interrupt process 1 executed by a 212. FIG. 12 is a timing chart showing the rise and fall of the power supply of each substrate. In the following description, the processing executed by the sub CPU 212 is R
The processing executed by the main CPU 112 is stored in the OM 214 as a computer program.
14 as a computer program.

(Startup of Power Supply) When the main power supply 70 (FIG. 5) is started up, 5 V is applied from the DC / DC converter 83 to each substrate.
Power is supplied. Then, when the voltage becomes equal to or higher than the minimum operating voltage of the voltage monitoring IC connected to the microprocessor mounted on each board, a system reset signal (low level) is output on all the boards and the board is stabilized. Subsequently, after a time Trs from when the 5V power supply reaches the voltage Vus, the system reset signal of the sub-substrate is released (low level to high level), and control of each sub-substrate is started. Then, 12V power is supplied to each substrate from the DC / DC converter 82, and after a time Trh from when the 12V power reaches the voltage Vuh, the system reset signal of the dispensing control substrate 200 is released, and the sub CPU 212 (FIG. 18A) Performs a security check. In this security check, it is checked whether or not there is any abnormality in the computer program recorded in the ROM 214.
Subsequently, when the security check is completed, the sub CPU
212 starts its operation.

The system reset signal of the main board 100 is released after a time Trm from when the 12V power supply reaches the voltage Vum, and the main CPU 112 of the main board 100 starts the operation after executing the security check. At this stage, the pachinko machine 10 is in a playable state. As described above, the sub-substrate, the payout control substrate 200, the main substrate 100
Control can be started in the order of
There is no omission of command reception from the main board 100 on all boards managed by 0.

(RAM Initialization Process 1 by Hall Computer) Here, the R
The AM initialization processing 1 will be described with reference to FIGS. As shown in FIG. 5, a hall computer 90 installed in a hall management room or the like is connected to a clear signal output circuit 84 mounted on a power supply board 80 of each pachinko machine 10 via a signal line 90a. The clear signal output circuit 84 is connected to the main board 100 via a signal line 85a, and is connected to the payout control board 2 via a signal line 85b.
00 is connected. Then, as shown in FIG. 7, when the hall computer 90 determines that the power of the hall is turned on (step (hereinafter abbreviated as S) 2: Ye)
s) The initialization command is output to the clear signal output circuit 84 of each pachinko machine 10 via the signal line 90a. Subsequently, the clear signal output circuit 84 outputs a memory clear signal (erase signal) to the main board 100 via the signal line 85a on condition that the initialization command output from the hall computer 90 is input. It outputs to the payout control board 200 via 85b. Note that the memory clear signal is valid for each substrate when it is at a high level, and is invalid when it is at a low level.

(Initialization processing of RAM 216 by sub CPU 212)
The initialization processing of No. 16 will be described with reference to FIG. The sub CPU 212 sets the interrupt prohibition (S10), and sets a stack pointer for holding the address of the main routine at the bottom of the address when shifting from the main routine to the subroutine (S12). Subsequently, the sub CPU 212 sets access permission to the RAM 216 (S14), and sets mode 2 to the interrupt mode (S14).
16). Subsequently, the sub CPU 212 sets an address to be used in mode 2 in the interrupt register (S1).
8) whether the check data in the RAM 216 is correct,
For example, it is determined whether or not A5A5H (S20).
If the check data is correct, for example, if it is A5A5H (S20: Yes), the clear signal output circuit 84
It is determined whether or not the memory clear signal output from FIG. 5 is at a high level (S21).

Subsequently, if the sub CPU 212 determines that the memory clear signal is not at the high level, that is, at the low level (S21: No), the sub CPU 212 clears (initializes) the area other than the backup area (storage holding area) in the RAM 216.
(S22). On the other hand, if the check data is incorrect (S20: No) or the memory clear signal is at a high level (S21: Yes), the RAM 216
After clearing (initializing) all the areas (e.g., 256 bytes) of the data in the check data (e.g., A5A5H)
Is stored (S24). That is, when the memory clear signal is at the high level, the winning data indicating the number of winnings, the data indicating the number of paying out prize balls, and the like, which are backed up (stored and stored) in the RAM 216, are deleted.

Subsequently, the sub CPU 212
Initialization of built-in devices such as a watchdog timer which is a timer for monitoring runaway of the 12 (S26)
Initial setting of the work area is performed (S28). Then sub CP
U212 sets the interrupt permission (S30), and this S3
Move to an infinite loop where 0 is repeated. Although not shown in the flowchart, the main CPU 112 of the main board 100 is not shown.
Determines whether or not the memory clear signal output from the clear signal output circuit 84 is at a high level in the program start process.
The data backed up (stored and stored) in 6, for example, data for reproducing the game state at the time of power-off after the power-down is erased. The data includes, for example, a control command for controlling the special symbol display device 32 (FIGS. 2 and 3), a control command for controlling the voice control device 79 (FIG. 3), and a control command for controlling the lamp control device 75 (FIG. 3). And so on.

(Main Program Processing of Sub CPU 212) Next, the flow of the main program processing executed by the sub CPU 212 of the payout control board 200 will be described with reference to FIG. This main program processing is performed by CTC
This is executed by a channel 3 interrupt of (timer counter) 218 (FIG. 18A). The sub CPU 212
Interrupt permission is set (S100), and the watchdog timer is restarted (S200). Then sub CPU
212 is a data and command output process (S300);
Input processing (S400), prize ball processing (S500) such as storage of the number of prize balls to be paid out and a payout command, and ball lending processing for controlling the ball lending unit 63 based on data from the CR connection board 56 (FIG. 3) ( S600) is executed.

(Command input processing of sub CPU 212)
Next, a flow of a command input process executed by the sub CPU 212 will be described with reference to FIG. This command input processing is executed by the channel 2 interrupt of the CTC 218. The sub CPU 212 inputs a control command such as a payout command sent from the main board 100 (S50), and checks the input control command (S52). For example, the control command is 2 bytes composed of an 8-bit signal, and is distributed to each byte. Subsequently, the sub CPU 212 determines whether the input control command is a control command meaning, for example, a command indicating a payout command of 5 prize balls, a command indicating a payout command of 15 prize balls, or the like. Analysis is performed (S54), and interruption permission is set (S56). As described above, the command input process is assigned to the channel 2 interrupt, and is executed in the second priority order following the NMI interrupt process described later. For example, the sub CPU 212 outputs a pulse to the winning ball payout motor 62c. Even if the main board sends a control command for paying out a prize ball, the control command can be analyzed with priority. Therefore, it is possible to eliminate a prize ball payout error or a delay in award ball payout due to a failure to receive a control command from the main board 100.

(Shutdown of Power Supply) When the main power supply 70 is cut off due to power cutoff at the end of pachinko hall business, power outage, power supply abnormality, etc., and the 12V power supply reaches the voltage Vdm (FIG. 12), the main board is turned off. A system reset signal is generated at 100 (from high level to low level). Then 12
When the V power supply reaches a voltage Vdh (for example, 10.3 V), N
An MI signal is generated and the NMI signal lasts for a time Tnmi. Data such as the number of prize balls is backed up in the RAM 216 during the time period Tnmi. At this time,
The discharge current of the capacitor C1 (FIG. 5) is applied to the backup power supply terminal VBB of the microprocessor 210 (FIG. 18).
(A)), the RAM 216 can back up (store and hold) data such as prize ball data. Further, the discharge current of the capacitor C2 (FIG. 5) is changed to the backup power supply terminal VBB of the microprocessor 110.
(FIG. 17A), the RAM 116
Data such as various control commands indicating a game state at the time of power-off can be backed up (stored and stored).

(NMI interrupt processing 1) Here, the sub CP
FIG. 11 shows NMI interrupt processing 1 executed by U212
This will be described with reference to FIG. When the NMI signal is generated, the sub CPU 212 sets access prohibition in the access register for the RAM 216 (S70). This interrupt process is executed with the highest priority over other interrupt processes. That is, by prohibiting access to the RAM 216,
The prize ball data stored in the RAM 216 is prevented from being rewritten. Although not shown in the flowchart, when the NMI signal is generated, the main CPU 112 also sets access prohibition in an access register for the RAM 116. This interrupt process is executed with the highest priority over other interrupt processes. In other words, by prohibiting the access to the RAM 116, the prize ball data stored in the RAM 116 is prevented from being rewritten.

For example, at the time of backing up the RAMs 116 and 216, if another interrupt process has already been executed and a new interrupt is prohibited, if the processing time of the other interrupt process becomes longer, Interrupt processing is permitted, and access to the RAMs 116 and 216 is prohibited in an attempt to prohibit access.
There is a possibility that some or all of the stored contents of the memory 16 may be destroyed. Therefore, the NMI interrupt process is used to set RAM1
By prohibiting the access to the
The storage contents of M116 and 216 are prevented from being destroyed. Then, as shown in FIG. 12, when the time Tnmi elapses, NM
The I signal stops, a system reset signal is generated on the main board 100, and the main board 100 is reset. Subsequently, a system reset signal is generated in the payout control board 200, and the payout control board 200 is reset. Subsequently, when the 5V power supply reaches the voltage Vds, a system reset signal is generated on the sub-substrate, and the sub-substrate is reset. Note that R
When the power is turned on during the period when the AM 116 is backed up, the main CPU 112
Then, various control commands indicating the game state at the time of power-off stored in the control unit 6 are output to the payout control board 200 and each sub-board, and the game is restarted from the middle of the game at the time of power-off. Also,
If the power is turned on while the RAM 216 is being backed up, the sub CPU 212
6, the prize ball payout motor 6 is referred to.
2c (FIG. 3) is driven to pay out award balls corresponding to the number of award balls.

[Effects of the First Embodiment] (Effects of Data Backup)
If the pachinko machine 10 of the embodiment is used, even if the main power supply 70 is cut off due to a power failure or the like, access to the RAMs 116 and 216 can be prohibited by the NMI interrupt processing. Game data or prize ball data stored in the RAM 216 can be prevented from being destroyed. Further, the RAM 1 built in the microprocessor 110 mounted on the main board 100 from the capacitor C2 serving as a backup power supply.
Since power can be supplied to the RAM 16, there is no possibility that data such as various control commands stored in the RAM 116 will be lost. Then, after the power is restored, the game can be restarted based on data such as various control commands stored in the RAM 116. Further, a RAM 2 built in a microprocessor 210 mounted on the dispensing control board 200 from a capacitor C1 serving as a backup power supply.
Since power can be supplied to the prize ball 16, there is no fear that the prize ball data stored in the RAM 216 will be lost. Then, after the power is restored, the prize balls corresponding to the number of prize balls stored in the RAM 216 can be paid out.

(Effect of Erasing Backup Data) When the pachinko machine 10 of the first embodiment is used,
When the power of the hall is turned on, the hall computer 90
From the clear signal output circuit 84 provided on the power supply board 80
The clear signal output circuit 84 outputs a memory clear signal to the main board 100 and the payout control board 200 by outputting the erase command to the RAM 116 and the payout control board 200 of the microprocessor 110 mounted on the main board 100. RAM of microprocessor 210
216 can be deleted. Therefore, even if data related to the payout of prize balls at the time of trial shooting before the opening of the pachinko hall or prize ball data rewritten due to static electricity noise or fraud is backed up in the RAM 216, the data is backed up. Since the stored data can be erased, there is no danger that the store side will suffer any disadvantage due to the prize balls being paid out based on the backed up data. In addition, it occurred during the test firing before opening,
Even when the control data for controlling the game is backed up in the RAM 116, the backed up control data can be deleted, so that when the player plays a game at the time of opening the store, the backed up control data The game is started based on the game, and the player does not feel uncomfortable. Further, by outputting an erasure command from the hall computer 90 to all the pachinko machines, the data backed up in all the pachinko machines can be simultaneously erased. An erasing process can be performed.

<Second Embodiment> Next, a second embodiment according to the present invention will be described with reference to FIGS. 8, 13 and 14. FIG. The pachinko machine according to the second embodiment is characterized in that it is possible to set in advance to clear the backup data in the RAM when the power is turned on. FIG. 13 is a flowchart showing the flow of the NMI interrupt process executed by the sub CPU 212, and FIG. 14 is a timing chart showing the rise and fall of the power supply of each board. Except for the NMI interrupt processing and the generation timing of the memory clear signal, the operation is the same as that of the first embodiment, and the description of the same parts will be omitted or simplified.

(NMI Interrupt Processing 2) Sub CPU 212
Determines that the memory clear signal output from the clear signal output circuit 84 (FIG. 5) provided on the power supply board 80 is at a high level when the NMI signal is generated (S66). If it is determined that the level is the level (S66:
Yes), S20 of the program start process shown in FIG.
Check data “A5A5” used in
0 ”(S68). Subsequently, the sub CPU 212
Sets access prohibition in the access register for the RAM 216 (S70). Although not shown in the flowchart, when the NMI signal is also generated by the main CPU 112, the clear signal output circuit 8 provided on the power supply board 80
4 (FIG. 5) is determined as to whether or not the memory clear signal is at a high level. If the memory clear signal is determined to be at a high level, the check data “A5A5” used in the program start process is replaced with “0000”. RA
Access prohibition is set in the access register for M116.

When the power supply 70 (FIGS. 3 and 5) is turned on, the sub CPU 212 executes the program start processing shown in FIG. 8, but the check data “A5A5” is changed to “0000” in S68 of the above-mentioned NMI processing. In S20, it is determined that the check data is not “A5A5” (S20: No), and R
All areas of the AM 216 (for example, 256 bytes) are all 0
After clearing (initialization), the check data A5A5H is stored (S24). That is, if the check data is "A
If it is not "5A5", the winning data indicating the number of winnings, the data indicating the number of paying out prize balls, and the like, which are backed up (stored and stored) in the RAM 216, are deleted. Although not shown in the flowchart, the main CPU 112 also checks the check data “A5A” in the program start process.
5 ”, and the entire area of the RAM 116 is set to 0
After clearing (initialization), the check data A5A5H is stored. That is, if the check data is not “A5A5”, the data is backed up (stored and stored) in the RAM 116.
Data such as various control commands indicating the game state at the time of power-off is erased.

[Effects of the Second Embodiment] As described above, if the pachinko machine according to the second embodiment is used, the check data is changed when the power is turned off, and the RAMs 116 and 216 are backed up when the power is turned on. Data can be cleared. Moreover, when the power supply rises,
Since the data backed up in the RAMs 116 and 216 can be automatically erased, there is no possibility that the data will be forgotten to be erased.

Third Embodiment Next, a third embodiment according to the present invention will be described with reference to FIGS. The pachinko machine according to the third embodiment is characterized in that a pachinko machine that clears the backup data in the RAM can be designated. FIG. 15 shows a hall computer 90.
Is a flowchart showing a flow of a RAM initialization process 2 executed by the sub CPU 212. FIG. 16 is a flowchart showing a flow of an initialization command input process executed by the sub CPU 212. Except for the RAM initialization processing 2 and the initialization instruction input processing, the configuration is the same as that of the above-described first embodiment, and the description of the same parts will be omitted or simplified.

If the hall computer 90 determines that the power of the hall has been turned on (S2: Yes), it performs a process of designating the machine number of the pachinko machine (S4). The specification of the unit number is performed by operating a numeric keypad of a keyboard provided in the hall computer 90, for example. Alternatively, a list of unit numbers is displayed on a screen of a monitor provided in the hall computer 90, and designation is performed by designating a desired unit number using a pointing device such as a mouse. Subsequently, the hall computer 90 executes S4
Then, an initialization instruction is output to the pachinko machine specified in the step (2) together with the machine number data indicating the machine number (S6).

Then, the sub CPU of the pachinko machine into which the initialization command output from the hall computer 90 is inputted.
Determines that an initialization command has been input (S402: Y
es) It is determined whether or not the machine number indicated by the machine number data input together with the initialization command matches its own machine number (S404). Next, when it is determined that the number matches the own number (S404: Yes), a memory clear signal is output to the RAM 216 (S406). Thereby, the winning data indicating the number of winnings, the data indicating the number of paying out prize balls, and the like, which are backed up (stored and stored) in the RAM 216, are deleted. Although not shown in the flow chart, the main CPU of the pachinko machine that has input the initialization command output from the hall computer 90 also determines that the initialization command has been input, and indicates the machine number data input together with the initialization command. It is determined whether or not the device number to be read matches its own device number. If it is determined that the device number matches its own device number, a memory clear signal is output to the RAM 116. As a result, data such as various control commands that are backed up (stored and held) in the RAM 116 and indicate the game state at the time of power-off are deleted.

[Effects of Third Embodiment] As described above, if the pachinko machine according to the third embodiment is used, it is possible to delete the data backed up (stored and held) in the RAM of the designated pachinko machine. For example, when an illegal act is performed on a specific gaming machine, the backup data in the RAM 216 can be erased by designating only that particular gaming machine. There is no risk of erasing.

<Fourth Embodiment> Next, a fourth embodiment according to the present invention will be described with reference to FIGS. 6, 17B and 18.
This will be described with reference to FIG. The pachinko machine according to the fourth embodiment is characterized in that the backup data in the RAM can be cleared by operating a switch. FIG.
(B) is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L1a, and FIG. 18 (B) is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L2a. In addition, except that the backup data in the RAM is erased by a switch operation without using the erase signal,
Since this is the same as the above-described first embodiment, the description of the same parts will be omitted or simplified.

As shown in FIG. 17B, the power supply board 80
The switch SW1 is connected in the middle of the backup power supply line L1a in the cable L1 (FIG. 6) for electrically connecting the power supply and the main board 100. Normally, when the switch SW1 which is closed (ON) for supplying backup power is opened (turned OFF), the built-in RAM backup of the microprocessor 110 is obtained from the capacitor C2 (FIG. 5) provided on the power supply board 80. Power supply terminal VB
B, the backup power supplied to
The data backed up in M116 (FIG. 17A) is deleted. As a result, data such as various control commands that are backed up (stored and held) in the RAM 116 and indicate the game state at the time of power-off are deleted.

As shown in FIG. 18B, the backup power supply line L in the cable L2 (FIG. 6) for electrically connecting the power supply board 80 and the dispensing control board 200 is provided.
The switch SW2 is connected in the middle of 2a. Normally, when the switch SW2 which is closed (ON) for supplying backup power is opened (turned OFF), the built-in RAM backup of the microprocessor 210 is obtained from the capacitor C1 (FIG. 5) provided on the power supply board 80. The backup power supplied to the power supply terminal VBB is cut off, and the data backed up in the RAM 216 (FIG. 18A) is erased. Thereby, RAM2
The winning data indicating the number of winnings, the data indicating the number of payouts of prize balls, and the like, which are backed up (stored and stored) in 16 are deleted.

[Effects of the Fourth Embodiment] As described above, if the pachinko machine according to the fourth embodiment is used, the switch S
With the simple operation of opening W1, the backup data in the RAM 116 can be erased, and the switch SW
The backup data in the RAM 216 can be erased by a simple operation of opening the RAM 2. Also, SW
1 and SW2 are selected and operated, so that the RAM 11
6 and 216 can be individually erased.

<Other Embodiments> (1) Remove the connector CN2b (FIG. 6) attached to one end of the cable L1 from the connector CN2a provided on the power supply board 80, or attach it to the other end of the cable L1. By disconnecting the connector (not shown) from the connector CN1 (FIG. 6) on the main board 100 side, the supply of the backup power from the capacitor C2 can be stopped. As a result, data such as various control commands indicating the game state at the time of power off and stored in the RAM 116 can be deleted. Further, the connector CN3b (FIG. 6) attached to one end of the cable L2 is detached from the connector CN3a provided on the power supply board 80, or the connector (not shown) attached to the other end of the cable L2 is dispensed. Connector C on board 200
By removing it from N1 (FIG. 6), the supply of backup power from the capacitor C1 can be stopped.
As a result, backup (storage retention) in the RAM 216 is performed.
Winning data indicating the number of winnings, data indicating the number of payouts of winning balls, and the like can be deleted.

(2) In the second embodiment, a case has been described in which the power is turned off so that the backup data is cleared when the power is turned on. However, the voltage of the drive power supplied to the pachinko machine is set to a predetermined value. When the voltage drops, the hall computer 90 outputs an erase command to the clear signal output circuit 84 before the NMI interrupt processing is executed, and the clear signal output circuit 84 sends an erase signal to the main board 100 and the payout control board 200. By outputting, R
The backup data of the AMs 116 and 216 can also be deleted. The hole computer 90 and the clear signal output circuit 84 in this configuration correspond to the erasing means according to the fourth aspect.

(3) In the first and second embodiments, the clear signal output circuit 84 sends an erase signal to the main board 100 and the payout control board 200 on condition that an erase command output from the hall computer 90 is input. Although the case of transmission has been described, the erasure signal may be directly output from the hall computer 90 to the main board 100 and the payout control board 200. The hall computer 90 in this configuration corresponds to the erasing means according to claim 5. (4) In the first to third embodiments, a case has been described in which the hall computer 90 outputs an erasure command to each pachinko machine. However, a computer for managing islands is provided for each island.
The computer can also output an erasure command to each of the pachinko machines constituting the island.

(5) In each of the above embodiments, the RAM 116 of the main board 100 and the R
The case where the backup data of the AM 216 is deleted has been described, but the sub CPUs provided in the special symbol display device 32, the voice control device 79, and the lamp control device 75, respectively.
However, if it has a function of backing up the data input or output by itself to the respective RAMs, it outputs an erasure signal from the clear signal output circuit 84 to each device to erase the data backed up in each RAM. You can also. (6) Further, in each of the above-described embodiments, the case where a capacitor is used as a backup power supply has been described as an example.
An electrically erasable ROM such as an EEPROM, a solid storage element such as an IC, a battery, a rechargeable battery, a chargeable solar battery, and the like can also be used. (7) In each of the above-described embodiments, the first-type pachinko machine has been described as an example of the gaming machine according to the present invention.
Of course, the present invention can be applied to other game machines such as a type 2 pachinko machine, a type 3 pachinko machine, other types of pachinko machines, and slot machines.

[Correspondence between Claims and Embodiments] The main CPU 112 corresponds to the control means according to claim 1 of the present invention, and the RAMs 116 and 216 correspond to the storage means. Further, the capacitors C1 and C2 correspond to the memory holding means, and the hall computer 90 and the clear signal output circuit 84 correspond to the erasing means. Further, the hall computer 90 corresponds to the erasure instructing means according to claim 10, and the clear signal output circuit 84 corresponds to the erasing executing means. Also,
The connectors CN2a, CN2b, CN3a, CN3b and CN1 correspond to the connector according to claim 21 or 22. Further, the capacitors C1 and C2 correspond to the storage medium according to claim 27 or 28, and
Reference numerals 114 and 214 correspond to the recording medium according to claim 29. In addition, the hall computer 90 and the pachinko machine 1
0 corresponds to the gaming system according to claim 2 of the present invention. Then, S2 executed by the hall computer 90
S6 (FIG. 7) and S2 executed by the sub CPU 212
0, S21 and S24 (FIG. 8) function as erasing means. S68 (FIG. 13) executed by the sub CPU 212 functions as an erasure instruction storage unit according to claim 11 or 12, and S20 and S24 function as erasure execution units. Further, the hall computer 90
S4 (FIG. 15) executed by the functioning unit functions as the specifying unit according to claim 17 or 18. Also, the sub CPU
Steps S20 and S24 executed by 212 correspond to an erasing process according to claim 29.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a pachinko machine according to an embodiment of the present invention as viewed from the front.

FIG. 2 is an explanatory diagram showing a main configuration of a game board 14 provided in the pachinko machine 10 shown in FIG.

FIG. 3 is an explanatory diagram showing an electrical configuration of the pachinko machine 10 by blocks.

FIG. 4 is an explanatory diagram showing a main hardware configuration of the pachinko machine 10;

FIG. 5 is an explanatory diagram showing a main configuration of a power supply board 80 together with a connection relationship with each board.

FIG. 6 is an explanatory diagram showing details of a connection relationship between a power supply board 80 and each board.

FIG. 7 is a flowchart showing a flow of a RAM initialization process 1 executed by the hall computer 90;

FIG. 8 is a flowchart illustrating a flow of a program start process executed by a sub CPU 212;

FIG. 9 is a flowchart illustrating a flow of a main program process executed by a sub CPU 212;

FIG. 10 is a flowchart illustrating a flow of a command input process executed by a sub CPU 212;

FIG. 11 is a flowchart showing a flow of NMI interrupt processing 1 executed by a sub CPU 212;

FIG. 12 is a timing chart showing the rise and fall of the power supply of each substrate.

FIG. 13 is a flowchart illustrating a flow of an NMI interrupt process executed by a sub CPU 212 in the second embodiment.

FIG. 14 is a timing chart showing the rise to fall of the power supply of each substrate.

FIG. 15 shows a hall computer 9 according to the third embodiment.
9 is a flowchart showing a flow of a RAM initialization process 2 executed by the CPU 0.

FIG. 16 is a flowchart illustrating a flow of an initialization command input process executed by a sub CPU 212;

FIG. 17A is an explanatory diagram showing a connection relationship between a power supply board 80 and a microprocessor 110, and FIG.
FIG. 7B is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L1a.

FIG. 18A is an explanatory diagram showing a connection relationship between a power supply board 80 and a microprocessor 210;
FIG. 8B is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L2a.

FIG. 19 is an explanatory front view of a conventional pachinko machine.

20 is an explanatory diagram of a back set of the pachinko machine shown in FIG.

[Explanation of symbols]

Reference Signs List 10 pachinko machine (game machine) 70 main power supply 80 power supply board 84 clear signal output circuit (erasing means) 90 hole computer (erasing means) 100 main board 112 main CPU (control means) 116 RAM (storage means) 200 payout control board 212 Sub CPU 216 RAM (storage means) C1, C2 Capacitor (storage holding means) CN1, CN2a, CN2b, CN3a, CN3b Connector (erasing means) SW1, SW2 Switch (erasing means)

Claims (29)

[Claims] 1. A control means for controlling a game, a storage means for storing data generated during the game, and the storage means when a voltage of a drive power supply supplied to the game machine drops to a predetermined voltage. A storage means for holding the storage of the storage means by supplying power for storage holding to the means; and an erasing means for erasing the data stored and held by the storage means, wherein the control means Is a game machine capable of controlling a game by referring to data stored and held by the storage and holding means. 2. A control means for controlling a game, a storage means for storing data generated during the game, and the storage means when a voltage of a drive power supply supplied to the game machine drops to a predetermined voltage. Storage means for holding the storage of the storage means by supplying power for storage holding to the means, wherein the control means refers to the data stored and held by the storage means to play a game. A gaming system, comprising: a controllable gaming machine; and erasing means provided outside the gaming machine, for erasing the data stored and held by the storage holding means. 3. The gaming machine according to claim 1, wherein the erasing unit transmits an erasing signal for erasing the data stored and held by the storage unit to the storing unit. 4. The gaming system according to claim 2, wherein said erasing means transmits an erasing signal for erasing said data stored and held by said storage and holding means to said storage means. 5. The gaming machine according to claim 3, wherein said erasing means transmits said erasing signal to said storage means when said drive power is turned on. 6. The gaming system according to claim 4, wherein said erasing means transmits said erasing signal to said storage means when said driving power is turned on. 7. The gaming machine according to claim 3, wherein said erasing means transmits said erasing signal to said storage means when said driving power supply drops to a predetermined voltage. 8. The gaming system according to claim 4, wherein said erasing means transmits said erasing signal to said storage means when said driving power supply drops to a predetermined voltage. 9. The erasing means includes: erasing instruction means for instructing erasure of the stored data; and storing the erasure signal on the condition that the erasure instruction means instructs erasure of the data. The gaming machine according to any one of claims 3, 5, and 7, further comprising an erasure execution unit that outputs the information to a unit. 10. The erasing means includes erasing instruction means for instructing erasure of the stored data, and the gaming machine confirms that the erasing instruction has been issued by the erasing instruction means. 9. The gaming system according to claim 4, further comprising: an erasure execution unit that outputs the erasure signal to the storage unit as a condition. 11. An erasure instruction storage means for storing the instruction from the erasure instruction means and capable of outputting the stored instruction, wherein the erasure execution means outputs the erasure instruction from the erasure instruction storage means. 10. The gaming machine according to claim 9, wherein the erasing signal is output to the storage means on condition that the instruction is input. 12. The gaming machine stores the instruction from the erasure instruction means,
Erasing instruction storing means capable of outputting the stored instruction, wherein the erasing executing means stores the erasing signal on condition that the instruction output from the erasing instruction storing means is input. 11. An output to a computer.
A gaming system according to item 1. 13. The gaming machine according to claim 9, wherein said erasure instruction means outputs said instruction to said erasure instruction storage means when said drive power is turned on. 14. The game system according to claim 10, wherein said erasure instruction means outputs said instruction to said erasure instruction storage means when said drive power is turned on. 15. The erasure instruction means outputs the instruction to the erasure instruction storage means when the drive power supply drops to a predetermined voltage. The erasure instruction storage means, when the drive power supply returns, 14. The apparatus according to claim 9, wherein the instruction is output to the erasing unit.
The gaming machine described in one. 16. The erasure instruction means outputs the instruction to the erasure instruction storage means when the drive power supply drops to a predetermined voltage. The erasure instruction storage means, when the drive power supply returns, 15. The gaming system according to claim 10, wherein the instruction is output to the erasure execution unit. 17. The apparatus according to claim 17, wherein said erasing means includes designation means for designating a gaming machine which outputs said erasure signal, and transmits said erasure signal to said gaming machine designated by said designation means. The gaming machine according to any one of claim 3, claim 5, claim 7, claim 9, claim 11, claim 13, and claim 15. 18. The apparatus according to claim 18, wherein said erasing means includes designation means for designating a gaming machine which outputs said erasure signal, and transmits said erasure signal to said gaming machine designated by said designation means. A game system according to any one of claims 4, 6, 8, 10, 12, 14, and 16. 19. A semiconductor device comprising: a plurality of substrates provided with the storage unit; and a power supply substrate for supplying power to the plurality of substrates. The erase signal is transmitted from the power supply substrate to each of the storage units. Claim 3, Claim 5, Claim 7, Claim 9, Claim 11, Claim 13, and Claim 1
The gaming machine according to any one of claims 5 and 17. 20. A semiconductor device comprising: a plurality of substrates each including the storage unit; and a power supply substrate that supplies power to the plurality of substrates. The erasing signal is transmitted from the power supply substrate to each of the storage units. Claim 4, Claim 6, Claim 8, Claim 10, Claim 12, Claim 14, Claim 16
A game system according to any one of claims 18 to 18. 21. The gaming machine according to claim 1, wherein said erasing means is a connector for removably electrically connecting said storage power supply and said storage means. 22. The gaming system according to claim 2, wherein the erasing means is a connector for electrically disconnecting the storage power supply and the storage means in a disconnectable manner. 23. The method according to claim 1, wherein the data is data relating to payout of a prize medium.
Claim 5, Claim 7, Claim 9, Claim 11, Claim 1
The gaming machine according to any one of claim 3, claim 15, claim 17, claim 19, and claim 21. 24. The method according to claim 2, wherein the data is data relating to payout of a prize medium.
A game system according to any one of claims 6, 8, 10, 10, 12, 14, 16, 16, 18, 20, and 22. 25. The data as claimed in claim 1, wherein the data is data for controlling a game. The gaming machine according to any one of claim 15, claim 17, claim 19, claim 21, and claim 23. 26. The data as claimed in claim 2, wherein the data is data for controlling a game.
A game system according to any one of claims 16, 18, 18, 20, 22, and 24. 27. The storage device according to claim 1, wherein the storage power source is a storage medium.
Claim 7, Claim 9, Claim 11, Claim 13, Claim 15, Claim 17, Claim 19, Claim 21, Claim 2
The gaming machine according to any one of claims 3 and 25. 28. The storage device according to claim 2, wherein the power source for storing and storing is a storage medium.
The game system according to any one of claims 8, 10, 10, 12, 14, 16, 18, 18, 20, 22, 24, and 26. 29. A control means for controlling a game, a storage means for storing data generated during the game, and said storage means when a voltage of a drive power supply supplied to the game machine drops to a predetermined voltage. Storage holding means for holding the storage of the storage means by supplying power for storage holding to the means,
Erasing means for erasing the data stored and held by the memory holding means, wherein the control means controls the game by referring to the data stored and held by the memory holding means. Provided,
A recording medium on which a computer readable program is recorded, wherein a computer program for executing an erasing process for erasing the data stored and held by the storage holding unit is recorded. A recording medium characterized by the above-mentioned.