JP2001198333A - Pachinko machine and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pachinko machine in which a discharge control circuit can correctly input control commands outputted from a main control circuit. SOLUTION: At the start-up of a main power source 70, 5 V power source is supplied to each substrate from a DC/DC converter 83 and when it exceeds the minimum operation voltage of a voltage monitoring IC connected to the microprocessor mounted on each substrate, a system reset signal is outputted to stabilize the voltage at all the substrates. Then the time Trs after the 5 V power source reached the voltage Vus, the system reset signal of a subordinate substrate is canceled and the control of each subordinate substrate is started. Then the 12 V power source is supplied form a DC/DC converter 82 to each substrate, the system reset signal of the discharge substrate 200 is canceled the time Trh after the 12 V power source reached the voltage Vuh and the reset system reset signal of the main substrate 100 is canceled the time Trm after the 12 V power source reached the voltage Vum.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko machine for controlling a game by a computer.

[0002]

2. Description of the Related Art Conventionally, as a pachinko machine of this type, when a game ball passes through a predetermined area, a plurality of symbols are variably displayed by a symbol display device, and when a stop symbol is aligned with a predetermined symbol, a big hit is hit. It is known that a large amount of prize balls can be paid out by generating and opening a special winning opening a plurality of times. In such a pachinko machine, a large number of circuits for controlling a game are used. For example, a main control circuit equipped with a CPU that determines whether or not a big hit has occurred, a payout control circuit that receives a payout control command from the main control circuit and controls payout of award balls, and a symbol control that performs display control of symbols. Circuit, voice control circuit for controlling sound effects during the game, etc.
A lamp control circuit or the like that controls an LED that is turned on at the time of winning or a decorative LED is used. In addition, a relay board for relaying a signal and a power supply is provided between predetermined circuits. The power supplied from the main power supply is first supplied to the main control circuit, and the main control circuit transforms the voltage to a voltage required for each circuit, and supplies the transformed voltage from the main control circuit to each circuit. .

[0003]

However, in the above-described conventional pachinko machine, if the main control circuit to which power is supplied first starts control first, and then the payout control circuit starts control, for example, When the power returns after a power failure,
If the payout control circuit has not yet started the control at the timing of transmitting data and control commands from the main control circuit to the payout control circuit, the payout control circuit may not be able to receive some or all of the data and control commands. There is. Therefore, if the data is data indicating the number of prize balls to be paid out, the correct number of prize balls cannot be paid out, or the control command is a command for driving the prize ball payout motor. If so,
The prize ball payout motor may not be driven normally. That is, the conventional pachinko machine has a problem that the payout control circuit may not be able to accurately input data and commands output from the main control circuit.

The present invention has been made to solve the above-mentioned problem, and has as its object to realize a pachinko machine in which a payout control circuit can accurately input data and commands output from a main control circuit. .

[0005]

In order to achieve the above object, according to the present invention, a main control circuit for outputting a control command and a main control circuit for outputting a control command are provided. A payout control circuit that controls the prize ball payout device when the control command is input, and generates and supplies power required for the main control circuit and the payout control circuit to each circuit. A control means for starting the control of the main control circuit after the control is started.

The control means supplies power necessary for a main control circuit for outputting a control command and a payout control circuit for controlling a prize ball payout device when the control command output from the main control circuit is input. It generates and supplies it to each circuit, and starts control of the main control circuit after starting control of the payout control circuit. In other words, the payout control circuit that inputs the control command can start the control before the main control circuit that outputs the control command, so that the payout control circuit is a part of the control command output from the main control circuit. Or, there is no possibility that all of them cannot be entered.

According to a second aspect of the present invention, in the pachinko machine according to the first aspect, the control means terminates the control of the payout control circuit after ending the control of the main control circuit. Is used.

That is, for example, when a payout control circuit is provided with a storage medium for storing the number of prize balls to be paid out, if the main control circuit terminates the control before the payout control circuit, the power supply The award ball count data was sent from the main control circuit to the payout control circuit at the time of interruption, but it may not be received by the payout control circuit and may not be stored in the storage medium, but the control of the main control circuit is terminated. After that, the control of the payout control circuit can be ended, so that the above situation can be avoided.

According to a third aspect of the present invention, in the pachinko machine according to the first or second aspect, a prize ball data storage medium for storing data indicating the number of prize balls to be paid out,
After the control of the main control circuit is completed, a technical means including an access prohibiting means for prohibiting an access to the award ball data storage medium for a predetermined time is used.

That is, the access prohibiting means indicates the number of prize balls after the control of the main control circuit in order to prohibit the access to the prize ball data storage medium for a predetermined time after the control of the main control circuit is completed. There is no danger of data being rewritten.

According to a fourth aspect of the present invention, in the pachinko machine according to the third aspect, a technical means is used in which a backup power supply for backing up data stored in the award ball data storage medium is provided.

That is, even if the power is cut off, the data stored in the prize ball data storage medium can be backed up. Therefore, when the power is restored, the data stored in the prize ball data storage medium is restored. The correct number of prize balls can be paid out based on the data.

According to a fifth aspect of the present invention, in the pachinko machine according to any one of the first to fourth aspects, the payout control circuit performs control after checking that it functions normally. Use the technical means of getting started.

In other words, the payout control circuit starts control after checking that it functions normally, and therefore can detect an abnormality in its function. For example, a payout control circuit is provided with a recording medium for storing data indicating the number of prize balls to be paid out, and when the data is illegally rewritten, by clearing the data to 0, the prize due to improper prize. Dispensing of the ball can be prevented.

According to a sixth aspect of the present invention, in the pachinko machine according to any one of the first to fifth aspects, the main control circuit performs control after checking that it functions normally. Use the technical means of getting started.

In other words, the main control circuit starts control after checking that it functions normally, and therefore can detect an abnormality in its function. For example, when the main control circuit includes a recording medium on which a computer program to be executed by the main control circuit is recorded, it is possible to detect an abnormality in the computer program.

In the invention according to claim 7, a main control circuit for outputting a control command, a payout control circuit for receiving the control command output from the main control circuit and controlling a prize ball payout device, A power supply circuit for generating a power supply necessary for the main control circuit and the payout control circuit and supplying the power supply to each circuit, provided in a pachinko machine, wherein the control of the main control circuit and the payout control circuit is started. A technical means of a recording medium in which a computer program for controlling at least one of the order and the control end order is recorded is used.

That is, a pachinko machine that controls a game by a computer can execute a computer program recorded on a recording medium such as a ROM provided in the pachinko machine, as described in an embodiment of the present invention described later.
Since the PU functions when executed, the pachinko machine according to any one of claims 1 to 6 can be realized by using a recording medium such as a ROM in which the computer program is recorded.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Hereinafter, an embodiment of a pachinko machine according to the present invention will be described with reference to the drawings. In the following embodiment, a so-called first-class pachinko machine will be described as an example of the pachinko machine according to the present invention. [Overall Main Configuration] First, the main configuration of the pachinko machine of this embodiment will be described with reference to FIG.
FIG. 1 is an explanatory view of the pachinko machine of this embodiment as viewed from the front. The pachinko machine 10 is provided with a front frame 11 so as to be openable and closable. A metal frame 12 is attached to the front frame 11 so as to be openable and closable. Mounted on A game board 14 is provided inside the glass frame 13. At the lower right of the front frame 11, a firing motor (FIG. 3) for firing game balls to the game board 14.
Firing handle 1 for operating the
5a is rotatably mounted, and on the left side of the game board 14, a guide rail 16 for guiding the shot game balls to the game area is provided. The firing handle 15a has
A firing stop button 15b for stopping the firing operation is provided.

On the right side of the front frame 11, there is provided a keyhole decoration 17 having a keyhole 15 into which a key for opening and closing the glass frame 13 is inserted. Above the front frame 11, a frame lamp 18a is provided. A front plate 19 is provided under the glass frame 13, and a prize ball / lending ball supply port 20a to which a prize ball or a lending ball is supplied is formed on an upper left portion of the front plate 19, On the supply side of the prize ball / lending ball supply port 20a, an upper receiving tray 20 for storing prize balls or lending balls supplied from the prize ball / lending ball supply port 20a is attached. Below the upper tray 20, there is formed an outlet 21a for discharging a prize ball that has flowed in excess of the number that can be accommodated in the upper tray 20, a game ball discharged from the upper tray 20 by operating the upper tray ball removing lever 20b, and the like. Have been. On the discharge side of the discharge port 21a, a lower tray 21 for storing the game balls discharged from the discharge port 21a is provided. On the left side of the front frame 11, there is provided a device outside the gaming machine 22 such as a prepaid card unit having a slit 22a for inserting a prepaid card.

[Main Configuration of Game Board 14] Next, the game board 1
4 will be described with reference to FIG. A center case 30 is provided substantially at the center of the game board 14. The center case 30 has a prize entrance 31
And a normal symbol display device 34 including three LEDs, and 4 indicating the number of times the normal symbol display device 34 is operated.
A normal symbol storage display LED 35 composed of a plurality of LEDs, a special symbol display device 32 for variably displaying a plurality of symbols, for example, 0-9 special symbols on a liquid crystal display, and a display 4 for displaying the number of times the special symbol display device 32 has been started. And a special symbol storage display LED 36 composed of a plurality of LEDs.

On the left and right sides of the center case 30, there are ordinary symbol operation gates 2 for operating the ordinary symbol display device 34.
6, 26 are provided. Below the center case 30, a first type starting port 27 having a function of operating the special symbol display device 32 is provided. Below the first type starting port 27, a stop symbol of the ordinary symbol display device 34 is provided. Ordinary electric accessory 28 that opens both wings when hit
Is provided. The opened ordinary electric accessory 28 has a function of starting the operation of the special symbol display device 32, similarly to the first type starting port 27. A variable winning device 40 which is activated when the stop symbol of the special symbol display device 32 hits the symbol is provided below the ordinary electric accessory 28.

The variable winning device 40 is provided with a large winning opening 41 in the form of a door which is opened when a hit occurs. The winning winning opening 41 can be opened and closed. Are provided respectively. Further, inside the special winning opening 41, there is provided a specific area 42 having a function of continuously opening the special winning opening 41, and a specific area switch (reference numeral 42 in FIG. 3) for detecting a game ball passing through the specific area 42.
a) and a special winning opening switch (indicated by reference numeral 43a in FIG. 3) for counting the number P of game balls that have won the special winning opening 41.

In addition, the game board 14 has windmills 23, 23
, Sleeve entrance prize opening 24, 24, corner decoration lamp 18
b, 18b, a prize lamp 18c that lights up when a prize is won,
An out-of-ball lamp 18d that lights up when the ball runs out, side decoration lamps 18e, 18e, and an out port 45 for collecting game balls that did not win as out balls are provided.
Further, many nails 28 are driven into the game board 14, and the game balls fired on the game board 14 fall while disturbing between the nails 28.

[Electrical Configuration of Pachinko Machine 10] Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. The pachinko machine 10 is provided with a main board 100, on which a microprocessor 110 is mounted. The microprocessor 110 has a main CP for executing game control.
U112 and a ROM 11 in which various control programs for the main CPU 112 to execute various controls are recorded.
And a RAM 116 for temporarily storing various data such as a control program read from the ROM 114 when the main CPU 112 executes various control programs and data relating to a big hit occurring during a game.

The following components are electrically connected to the main substrate 100. Power supply board 80, payout control base 200 for controlling payout of award balls, etc., special symbol display device 3
2. A lamp control device 75 for controlling lamps provided on the game board 14, a sound control device 79 for controlling a sound reproduction device (not shown) for reproducing sound effects during a game, etc., a first type start of a game ball. A first-type start-up switch 27a for detecting the passage of the mouth 27; a game frame information terminal board 5 for transmitting game board information relating to winnings, big hits, etc. to a computer (not shown) provided in a pachinko hall management room or the like;
2, a board relay board 51 and a game frame relay board 53.

The payout control board 200 is equipped with a microprocessor 210 that operates by inputting a control command sent from the main board 100. The microprocessor 210 has a sub CPU that controls payout of prize balls and the like.
212, a ROM 214 in which various control programs for the sub CPU 212 to execute control such as payout of prize balls, and a control program read from the ROM 214 when the sub CPU 212 executes various control programs and a game And a RAM 216 for temporarily storing various data such as the number of prize balls generated in the RAM. In addition, the power supply board 80, the CR connection board 56, the firing motor drive board 15c for driving the firing motor 15e, the game frame information terminal board 52, and the payout relay board 55 are electrically connected to the payout control board 200. I have.

The game frame relay board 53 has a full detection switch 2 for detecting that the lower tray 21 is full of prize balls.
1b and the sensor relay board 54 are electrically connected. The sensor relay board 54 is electrically connected to the prize ball payout sensors 62a and 62b and the payout relay board 55 provided in the prize ball unit 62. The prize ball unit 62
Prize ball payout sensors 62a, 62b and prize ball payout motor 6
2c. There are two prize ball payout mechanisms for efficiently paying out prize balls, and each payout mechanism is driven by a prize ball payout motor 62c. The prize ball payout sensor 62a is provided in one mechanism, and the prize ball payout sensor 62b is provided in the other mechanism. Detection signals from the prize ball payout sensors 62a and 62b are transmitted from the sensor relay board 54 to the main board 100 via the game frame relay board 53.
To the payout control board 200 via the payout relay board 55. And the payout control board 20
The sub CPU 212 mounted on the prize ball payout sensor 6
The detection signals transmitted from 2a and 62b are taken in, and the number of awarded prize balls is counted. For example, sub CPU2
12 subtracts “1” from the value of the area in the RAM 216 storing 15 payout balls every time the detection signal is taken.

The payout relay board 55 is electrically connected to a ball-off switch 61 for detecting that the ball is no longer available, a prize-ball payout motor 62c, and a ball-for-ball unit 63. The following components are electrically connected to the board-surface relay board 51. Ordinary electric accessory solenoid 28a for opening and closing the ordinary electric accessory 28, ordinary symbol display device 34, gate switch 26 provided on the ordinary symbol actuation gate 26
a, a special winning opening switch 43a, a sleeve winning opening switch 24a detecting a winning in the sleeve winning opening 24, a lower winning opening switch 29a detecting a winning in the lower winning opening 29, and detecting a winning in the natural winning opening 31. The winning opening switch 31a and the winning opening relay board 50.

A special winning area solenoid 42b, a special winning area solenoid 43b, and a specific area switch 42a are electrically connected to the special winning opening relay board 50. The power supply board 80 is electrically connected to the CR connection board 56,
The CR connection board 56 is electrically connected to the gaming machine external device portion 22 including a frequency display board for displaying the remaining frequency of the prepaid card and a device for reading the prepaid card. The power supply board 80 is a 24 V AC (50 Hz / 6
(0 Hz) from the main power supply 70. In addition,
In this embodiment, a proximity switch is used as the gate switch 26a, each winning opening switch, and the prize ball payout sensor.

[Main Hardware Configuration] Next, FIG. 4 shows the main hardware configuration of the pachinko machine 10.
This will be described with reference to FIG. Here, the main CPU 112 of the main board 100 and the sub C of the payout control board 200
The hardware configuration of the interface between the PUs 212 will be described as an example. Main CP of main board 100
Various control commands output from U112
Output to the output port 120 via the PU bus 118;
The output various control commands are temporarily stored in the output buffer 126 via the main CPU parallel output port 124, and then stored in the input buffer 220 connected to the sub CPU 212. And the main CPU
The transfer signal output from the main CPU bus 1
When the trigger signal (TRG2) 226 of the sub CPU 212 is input from the sub-CPU 212 via the output port 122, the output buffer 128, and the input buffer 222, various control commands accumulated in the input buffer 220 are transmitted to the sub-CPU 212.
The data is input to the input port 224 of the sub CPU 212 via the parallel input port 228. And the sub CPU
The 212 performs analysis such as what the captured various control commands mean, and outputs an award ball payout command to the award ball unit 62 based on the analysis result. Note that the main CPU 1 of the main board 100
The hardware configuration between the sub-CPU 12 and the sub CPU mounted on a board other than the payout control board 200 is the same as the above-described configuration.

[Main Configuration of Power Supply Board 80, Power Supply Board 80
Next, the main configuration of the power supply board 80 and the connection relation between the power supply board 80 and each board will be described with reference to FIGS. FIG. 5 is an explanatory diagram showing a main configuration of the power supply board 80 together with a connection relationship with each substrate, and FIG. 6 is an explanatory diagram showing details of a connection relationship between the power supply substrate 80 and each substrate. As shown in FIG. 5, the 24 V AC current supplied from the main power supply 70 is converted to 32 V DC by the rectifier circuit 81 via the fuse F <b> 1 and supplied to the main board 100 and the payout control board 200, respectively. The 32 V direct current is supplied to the DC / DC converter 82.
To 12V. The 12 V DC is applied to the main board 100, the special symbol display device 32, and the lamp control device 7.
5, are supplied to the voice control device 79 and the payout control board 200, respectively. Further, the AC 24 V of the main power supply 70 is supplied to the CR connection substrate 56 through the 24 V line 85 via the fuse F2.

The 32 V DC supplied to the main board 100 is supplied to the board relay board 51 (FIG. 3) to drive the ordinary motor accessory solenoid 28a. Special symbol display device 32
12V DC supplied to the lamp controller 75 drives the liquid crystal and the like of the special symbol display, and the 12V DC supplied to the lamp control device 75 converts the corner decoration lamp 18b and the winning lamp 18c.
Lights or flashes. The 12 V DC supplied to the voice control device 79 drives the speaker via the voice circuit, and the 12 V DC supplied to the payout control board 200.
V direct current is transmitted to the prize ball unit 6 via the payout relay board 55.
2 and the ball rental unit 63, and the prize ball payout motor 62
drive c and the like. Further, the 32 V direct current supplied to the payout control board 200 is supplied to the ball letting unit 63 (FIG. 3) via the payout relay board 69, and a solenoid for operating a shutter member that divides the supplied ballpark by a predetermined number is operated. Drive.

The DC current converted to 12V by the DC / DC converter 82 is converted to 5V by the DC / DC converter 83. The 5V DC is supplied to the main board 100, the special symbol display device 32, and the lamp control device. 7
5, are supplied to the voice control device 79 and the payout control board 200, respectively. The 5 V DC supplied to the main board 100 serves as a drive power supply for the microprocessor 110 (FIG. 3), and the 5 V DC supplied to the payout control board 200 serves as a drive power supply for the microprocessor 210 (FIG. 3). The 5 V DC supplied to the special symbol display device 32, the lamp control device 75, and the audio control device 79 serves as a drive power supply for a microprocessor (not shown) provided in each device.

That is, the power of each board is supplied from a single power board 80, and the power board 80 controls the power of each board. For this reason, even if the board configuration is different for each manufacturing model, it is only necessary to wire the power supply line from the power board 80 to each board, so that the power supply path and the transformer circuit of each board are different for each manufacturing model. There is no need to design. Therefore, since the degree of freedom in designing the substrate can be increased, the production yield of the pachinko machine can be improved. Further, since it is not necessary to provide a transformer circuit for each substrate, it is possible to save the space of the substrate.

As shown in FIG. 6, the power supply board 80 has the No. for supplying power to the main board 100. A 6-pin connector CN2a of 1 to 6 is attached, and this connector CN2a is connected to a connector CN1 attached to the main board 100 by a cable L1. Cable L1
Has a terminal C for connecting to the connector CN2a.
N2b is attached, and a terminal (not shown) for connecting to the connector CN1 on the main board 100 side is attached to the other end. The power supply board 80 has the No. for supplying power to the payout control board 200. An 8-pin connector CN3a of 1 to 8 is attached, and the connector CN3a is connected to the payout control board 200 by a cable L2.
Is connected to the connector CN1 attached to the. A terminal CN3b for connection to the connector CN3a is attached to one end of the cable L2, and a terminal (not shown) for connection to the connector CN1 on the payout control board 200 is attached to the other end. .

Further, the power supply board 80 includes a connector CN.
7a, CN4a, CN5a, CN6a, CN1a are attached. The connector CN7a is connected to the CR connection board 56 by a cable L3.
Is connected to a connector CN7a at one end.
7b is attached, and a terminal (not shown) for connecting to the connector CN2 on the CR connection board 56 side is attached to the other end. The connector CN4a is connected to the cable L4
Is connected to a special symbol control board 32a provided in the special symbol display device 32, a terminal CN4b for connecting to the connector CN4a is attached to one end of the cable L4, and a special symbol control board is attached to the other end. A terminal (not shown) for connecting to the connector CN1 on the 32a side is attached.

The connector CN5a is connected to a lamp control board 75 provided in the lamp control device 75 by a cable L5.
a terminal CN5b for connecting to the connector CN5a is attached to one end of the cable L5, and the connector CN on the lamp control board 75a side is attached to the other end.
A terminal (not shown) for connecting to the terminal 1 is attached. The connector CN6a is connected to a voice control board 79a provided in the voice control device 79 by a cable L6. A terminal CN6b for connecting to the connector CN6a is attached to one end of the cable L6, and the other end is connected to the other end. A terminal (not shown) for connecting to the connector CN1 on the audio control board 79a side is attached. Connector C
N1a is connected to the main power supply 70 by a power cord L7, and one end of the power cord L7 has a connector CN1a.
A terminal CN1b for connection to the terminal is attached.

Since the cables L4 to L6 have the same number of terminal pins, a common cable can be used. Therefore, it is possible to save the trouble of selecting a cable as compared with a case where cables having different numbers of terminal pins are used, so that the cable connection processing can be performed easily and in a short time. In addition, since the number of cables that can be used in common is large, the manufacturing cost can be reduced as compared with the case where many types of cables having different numbers of terminal pins are manufactured.

[Voltage Monitoring Function] Next, a function of monitoring the voltage of the power supplied from the power supply board 80 to each board will be described with reference to FIGS. 5, 6 and 7B.
FIG. 7B is an explanatory diagram illustrating a main configuration of the power supply voltage monitoring IC. As shown in FIG. 5, the power supply board 80 is provided with a power supply voltage monitoring IC 84 for monitoring the voltage of the power supply supplied to each board. Power supply voltage monitoring IC84
Are 32V line 86, 12V line 87, 5V line 8 from voltage detection lines A1, A2 and A3, respectively.
8 is detected. The power supply voltage monitoring IC 84 is shown in FIG.
As shown in (B), an A / D conversion circuit 84a that converts a voltage detected from the 32V line 86 into a digital signal,
A / D conversion circuit 84b for converting the voltage detected from the 12V line 87 into a digital signal, and A / D conversion circuit 8 for converting the voltage detected from the 5V line 88 into a digital signal
4c. Each A / D conversion circuit is connected to a CPU 84e. The CPU 84e takes in a digital signal output from each A / D conversion circuit, calculates a voltage, and determines a voltage drop or the like based on the calculated value. I do. The CPU 84e is connected to each board, outputs a RESET signal to each board according to the determination result, and resets the board that has dropped to a predetermined voltage.

[Data Backup Function] Next, a function of backing up data stored in the RAM 216 built in the microprocessor 210 will be described with reference to FIGS. 5 and 7A. FIG. 7A is an explanatory diagram showing a connection relationship between the power supply board 80 and the microprocessor 210. In the following description, the sub-substrate refers to each substrate other than the main substrate 100 and the payout control substrate 200. As shown in FIG. 5, the DC / DC converter 8
Power supply line 8 for connecting 3 to payout control board 200
A diode D1 is connected in series to 3a, and a capacitor C1 as a backup power supply is connected in parallel to the output side of the diode D1. This capacitor C1
Is charged by a 5 V DC current supplied from the DC / DC converter 83. The discharge current of the capacitor C1 is supplied to the built-in RAM backup power supply terminal VB of the microprocessor 210 via the backup power supply line L2a in the cable L2 as shown in FIG.
B.

As shown in FIG. 7A, one of the outputs of the voltage monitoring IC 84 is a microprocessor 210
NMI (Non-Maskable Interrupt) terminal. Here, the connector CN3b (FIG. 6) attached to one end of the cable L2 is removed from the connector CN3a provided on the power supply board 80, or a connector (not shown) attached to the other end of the cable L2 is dispensed. By disconnecting from the connector CN1 (FIG. 6) on the control board 200 side, the supply of the backup power from the capacitor C1 can be stopped. Thereby, the RAM 21
Even if data important for paying out prize balls stored in 6 is rewritten due to electrostatic noise or fraud, the supply of backup power can be stopped quickly and easily. Can be minimized to a minimum. In this embodiment, the capacitor C1 is an electric double-layer capacitor, and has a nominal capacitance of 0.1 F and a rated voltage of 5.5 V. The cables L1 to L6 are FPCs (flexible print circuits).

[Main Control of Power Supply and Discharge Control Board] Next, control of the power supply of each board and main control of the discharge control board 200 will be described with reference to FIGS.
FIG. 8 is a flowchart showing the flow of a program start process executed by the sub CPU 212, and FIG.
6 is a flowchart illustrating a flow of a main program process executed by a PU 212. FIG. 10 is a flowchart illustrating a flow of a command input process executed by the sub CPU 212, and FIG. 11 is a flowchart illustrating a flow of an NMI interrupt process executed by the sub CPU 212. FIG.
5 is a timing chart showing the rise and fall of the power supply of each substrate.

(Startup of Power Supply) When the main power supply 70 (FIG. 5) is started up, 5 V is applied from the DC / DC converter 83 to each substrate.
Power is supplied. Then, when the voltage becomes equal to or higher than the minimum operating voltage of the voltage monitoring IC connected to the microprocessor mounted on each board, a system reset signal (low level) is output on all the boards and the board is stabilized. Subsequently, after a time Trs from when the 5V power supply reaches the voltage Vus, the system reset signal of the sub-substrate is released (low level to high level), and control of each sub-substrate is started. Then, 12V power is supplied to each board from the DC / DC converter 82, and after a time Trh from when the 12V power reaches the voltage Vuh, the system reset signal of the dispensing control board 200 is released, and the sub CPU 212 (FIG. 7A) Performs a security check. In this security check, it is checked whether or not there is any abnormality in the computer program recorded in the ROM 214. Subsequently, when the security check is completed, the sub CPU 2
12 starts the operation.

(Program Start Process of Sub CPU 212) Here, the program start process executed by the sub CPU 212 will be described with reference to FIG. Sub C
The PU 212 sets the interrupt prohibition (step (hereinafter, referred to as “step”).
10), a stack pointer for holding the address of the main routine when shifting from the main routine to the subroutine is set at the bottom of the address (S12). Subsequently, the sub CPU 212
Access permission is set (S14), and the interrupt mode is set to mode 2 (S16). Subsequently, the sub CPU 21
2 sets the address to be used in mode 2 in the interrupt register (S18), and determines whether the check data in the RAM 216 is correct, for example, A5A5H (S20), and if the check data is correct (S20). S
20: Yes), the area other than the backup area in the RAM 216 is cleared to 0 (initialization). If the check data is not correct (S20: No), all the area (for example, 256 bytes) of the RAM 216 is cleared to 0 (initialization). ) And store the check data (for example, A5A5H) (S24).

Subsequently, the sub CPU 212
Initialization of built-in devices such as a watchdog timer which is a timer for monitoring runaway of the 12 (S26)
Initial setting of the work area is performed (S28). Then sub CP
U212 sets the interrupt permission (S30), and this S3
Move to an infinite loop where 0 is repeated. Then, as shown in FIG. 12, the time Trm after the 12V power supply reaches the voltage Vum.
Later, the system reset signal of the main board 100 is released,
The main CPU 112 of the main board 100 starts the operation after executing the security check. At this stage, the pachinko machine 10 is in a playable state. As described above, since control can be started in the order of the sub-substrate, the payout control substrate 200, and the main substrate 100, a command reception omission from the main substrate 100 occurs in all the substrates managed by the main substrate 100. Never do.

(Main Program Processing of Sub CPU 212) Here, the flow of the main program processing executed by the sub CPU 212 of the payout control board 200 will be described with reference to FIG. This main program processing is performed by CTC
(Timer counter) 218 (FIG. 7A) is executed by a channel 3 interrupt. The sub CPU 212 sets interruption permission (S100) and restarts the watchdog timer (S200). Then, sub CPU2
Reference numeral 12 denotes data and command output processing (S300), input processing (S400), prize ball processing (S500) such as storage of the number of prize balls to be paid out and a payout command, and data from the CR connection board 56 (FIG. 3) A ball lending process (S600) for controlling the ball lending unit 63 is executed based on this.

(Command Input Processing of Sub CPU 212)
Next, a flow of a command input process executed by the sub CPU 212 will be described with reference to FIG. This command input processing is executed by the channel 2 interrupt of the CTC 218. The sub CPU 212 inputs a control command such as a payout command sent from the main board 100 (S50), and checks the input control command (S52). For example, the control command is 2 bytes composed of an 8-bit signal, and is distributed to each byte. Subsequently, the sub CPU 212 determines whether the input control command is a control command meaning, for example, a command indicating a payout command of 5 prize balls, a command indicating a payout command of 15 prize balls, or the like. Analysis is performed (S54), and interruption permission is set (S56). As described above, the command input process is assigned to the channel 2 interrupt, and is executed in the second priority order following the NMI interrupt process described later. For example, the sub CPU 212 outputs a pulse to the winning ball payout motor 62c. Even if the main board sends a control command for paying out a prize ball, the control command can be analyzed with priority. Therefore, it is possible to eliminate a prize ball payout error or a delay in award ball payout due to a failure to receive a control command from the main board 100.

(Shutdown of power supply) Main power supply 70 is shut down due to power interruption, power outage, or power supply abnormality at the end of pachinko hall business, and when 12V power supply reaches voltage Vdm, system reset to main board 100 is performed. A signal is generated (high level → low level). Subsequently, when the 12 V power supply reaches the voltage Vdh (for example, 10.3 V), an NMI signal is generated, and this NMI signal continues for a time period Tnmi. During this time Tnmi, data such as the number of award balls
It is backed up to AM 216. At this time, the discharge current of the capacitor C1 (FIG. 5) is
Is supplied to the backup power supply terminal VBB (FIG. 7A), so that the RAM 216 can keep storing data such as prize ball data. Gate switch 2
6a and the operating voltage of each winning opening switch are set on the main board 10
Since 0 is set lower than the resetting voltage Vdm, even if the voltage of the main board 100 decreases, it is possible to detect that the game ball has passed through the symbol operating port and that a winning is achieved. There is no danger that people will suffer disadvantages. Further, since the operating voltage of the prize ball payout sensors 62a and 62b is set lower than the voltage Vdh reset by the payout control board 200, the payout control board 200 is set to the voltage Vdh.
Even in the case where the number drops to dh, the number of award balls can be accurately counted.

(NMI Interrupt Processing of Sub CPU 212)
Here, the NMI interrupt processing executed by the sub CPU 212 will be described with reference to FIG. Sub CPU 212
Sets the access prohibition in the access register for the RAM 216 when the NMI signal is generated (S7).
0). This interrupt process is executed with the highest priority over other interrupt processes. In other words, by prohibiting access to the RAM 216, the prize ball data stored in the RAM 216 is prevented from being rewritten.

For example, at the time of backing up the RAM 216, if another interrupt process has already been executed and a new interrupt has been disabled, and if the processing time of the other interrupt process becomes longer, an interrupt is thereafter issued. If processing is permitted and access to the RAM 216 is to be prohibited, it may be too late to destroy part or all of the stored contents of the RAM 216. Therefore, NMI
By prohibiting access to the RAM 216 by interrupt processing, destruction of the storage contents of the RAM 216 is prevented. When the time Tnmi has elapsed, the NMI signal stops, a system reset signal is generated in the payout control board 200, and the payout control board 200 is reset. That is, after the main board 100 is reset, the payout control board 2
Since the system reset is performed at 00, it is possible to avoid a situation in which the prize ball data transmitted from the main board 100 to the payout control board 200 when the power is turned off cannot be stored in the RAM 216. Subsequently, when the 5V power supply reaches the voltage Vds, a system reset signal is generated on the sub-substrate, and the sub-substrate is reset. If the power is turned on while the RAM 216 is being backed up, the sub CPU
Reference numeral 212 refers to the number of award balls stored in the RAM 216, drives the award ball payout motor 62c (FIG. 3), and pays out the award balls corresponding to the number of award balls.

(Power supply monitoring process) Next, the power supply voltage monitoring I
The flow of the power supply voltage monitoring process executed by the CPU 84e provided in the C84 will be described with reference to the flowchart of FIG. Here, a case where the voltage of the 12V line 87 is monitored will be described as an example. C
When the PU 84e takes in a timing signal from a timer (not shown) and determines that it is the timing to detect the power supply voltage (S80: Yes), the PU 84e controls each A / D conversion circuit via the control line 84f (FIG. 7B). A control signal is sent to the server (S82). Each of the A / D conversion circuits that take in the control signal takes in current from each voltage line, converts the voltage value of the taken current into a digital signal,
84e.

The CPU 84e calculates the voltage V2 by counting the received digital signals, and determines whether the voltage V2 is equal to or lower than a predetermined voltage (S86). here,
The predetermined voltage is, for example, the minimum operating voltage required for the functioning of the board, and is 10.3 V for a board with a 12 V power supply, for example. Subsequently, the CPU 84e sets the voltage V
If 2 is 10.3 V or less (S86: Yes),
RESET to each board functioning with 12V power supply
A signal is transmitted (S88), and a notification LED 89 (FIG. 5) provided at a predetermined location of the pachinko machine 10 (for example, on a board for transmitting a RESET signal or at a location visible from the outside of the pachinko machine 10) is lit. (S9
0). By turning on the notification LED 89, it is possible to report that a non-functioning substrate has occurred due to a decrease in the power supply voltage. For this reason, a measure for restoring the function of the substrate can be performed at an early stage. When the power supply voltage is restored to a normal voltage, a reset release signal is sent from the power supply voltage monitoring IC 84 to each of the reset substrates, the reset state of each substrate is released, and each substrate resumes control.

As described above, if the pachinko machine 10 of the first embodiment is used, the system reset of the payout control board 200 can be performed by utilizing the voltage rising characteristic of the 12V power supply supplied by the DC / DC converter 82. Since the system reset of the main board 100 can be canceled after the cancellation, for example, when the power is restored after a power failure, a part or all of the prize ball data or the prize ball payout control command sent from the main board 100 is reset. Dispensing control board 200
There is no risk of being unable to input. Therefore, there is no possibility that an accurate number of prize balls cannot be paid out or the prize ball payout motor 62c cannot be normally driven. Further, since one power supply voltage monitoring IC 84 monitors the power supply voltage of each board and detects an abnormality of a certain voltage, each board to which the voltage is supplied can be simultaneously reset or the reset state can be canceled. The control timing of each substrate can be controlled with high accuracy. In addition, since it is not necessary to provide a power supply voltage monitoring IC for each substrate, it is possible to save space for each substrate.

Further, since there is a single power supply means for supplying power to each substrate, even if the substrate configuration is different for each manufacturing model, it is only necessary to wire a power supply line from the power supply substrate to each substrate. Therefore, it is not necessary to design a power supply path, a transformer circuit of each substrate, and the like for each manufacturing model. Therefore, since the degree of freedom in designing the substrate can be increased, the production yield of the pachinko machine can be improved. Further, since it is not necessary to provide a transformer circuit for each substrate, it is possible to save the space of the substrate. Note that the main CPU 112 or the sub CPU 212 may monitor the voltage. In this case, the voltage monitoring may be independent of other processing, or may be interrupt processing.

[Second Embodiment] Next, a pachinko machine according to a second embodiment of the present invention will be described with reference to FIGS. The pachinko machine according to the second embodiment includes:
It is characterized in that control start and control end of each substrate are performed by software. FIG. 14 shows a board control I for controlling each board.
It is explanatory drawing which shows the main structures of C. FIG. 15 is a flowchart showing a flow of a control start process executed by the CPU 302 shown in FIG. 14, and FIG. 16 is a flowchart showing a flow of a control end process executed by the CPU 302.

As shown in FIG. 14, the board control IC 300
Converts the voltage fetched from the 12V line and the 5V line into digital signals using A / D conversion circuits 84b and 84c, respectively, and CPU 302 fetches the digital signals from each A / D conversion circuit and stores them in ROM 304. Each voltage value is calculated according to the computer program, and the control start order and control end order of each board are controlled. RAM 306 is a work area or CPU
It is used for temporary storage of the operation value 302. CP
U302 sends a reset signal or a reset release signal to each substrate when executing a program.

(Control Start Processing) The CPU 302 detects that power has been supplied from the main power supply 70 (S700: Y).
es) When it is detected that the voltage V1 taken from the 5V line 88 has risen to 5V (S702: Yes), a system reset signal is sent to each substrate (S704). Subsequently, when the CPU 302 detects that the elapsed time T1 from sending the system reset signal to each board has reached a preset time Trs (S706: Yes),
The system reset signal sent to the sub circuit board is released (S708). Subsequently, the CPU 302 detects that the voltage V2 taken from the 12V line 87 has risen to the voltage Vus (S710: Yes), and the elapsed time T2 from the rise of the voltage V2 to the voltage Vus is a preset time. T
When it is detected that rh has been reached (S712: Yes), the system reset signal sent to the payout control board 200 is released (S714).

Subsequently, the CPU 302 sets the voltage V2 to the voltage V.
um is detected (S716: Yes), and when it is detected that the elapsed time T3 from the rise of the voltage V2 to the voltage Vum has reached a preset time Trm (S7).
18: Yes), the system reset signal sent to the main board 100 is released (S720). Thus, C
The PU 302 can control the control start timing of each board by detecting the voltages of the 5V line 88 and the 12V line 87. Further, by changing the times Trs, Trh, Trm and the voltages Vus, Vum set in the computer program, the control start timing of each board can be easily changed.

(Control end processing) The CPU 302 detects that the power supply from the main power supply 70 has stopped (S80).
0: Yes), the voltage V2 taken from the 12V line 87
Is detected to drop to a preset voltage Vdm (S802: Yes), a system reset signal is sent to the main board (S804). Subsequently, the CPU 302
It is detected that the voltage V2 has dropped to the preset voltage Vdh (S806: Yes), and it is determined that the elapsed time T3 from the drop of the voltage V2 to the voltage Vdh has reached the preset time Tnmi. When it is detected (S808: Ye
s) A system reset signal is sent to the payout control board 200 (S810). The above-described NMI interrupt process is executed at the timing when the voltage V2 drops to the voltage Vdh,
The backup process of the RAM 216 is executed during the period of time Tmni.

Subsequently, when the CPU 302 detects that the voltage V1 taken from the 5V line 88 has dropped to the preset voltage Vds (S812: Yes), it sends a system reset signal to the sub-substrate (S814). ).
As described above, the CPU 302 controls the 5V lines 88 and 12
By detecting the voltage of the V line 87, the control end timing of each substrate can be controlled. Also, the voltages Vdm, Vds set in the computer program
, The control end timing of each substrate can be easily changed. Further, by changing the voltage Vdh, the timing of executing the NMI interrupt process can be changed, and by changing the time Tnmi, the period for performing the backup process can be changed. The control start processing or the control end processing described above may be configured to be executed by the main CPU 112, the sub CPU 212, or the CPU provided on the sub-assembled board.

[Correspondence between Claims and Embodiments] The microprocessor 110 corresponds to the main control circuit according to claim 1, the microprocessor 210 corresponds to the payout control circuit, and the power supply board 80 corresponds to the control means. I do. Also, RAM
216 corresponds to the prize ball data storage medium according to claim 3,
The capacitor C1 corresponds to the backup power supply according to claim 4. The ROM 304 corresponds to the recording medium according to claim 7. Further, S70 of FIG. 11 executed by the sub CPU 212 functions as an access prohibiting unit according to claim 3, and S700 to S700 of FIG.
720 functions as the control means according to claim 1;
S800 to S814 function as the control means according to claim 2.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a pachinko machine according to an embodiment of the present invention as viewed from the front.

FIG. 2 is an explanatory diagram showing a main configuration of a game board 14 provided in the pachinko machine 10 shown in FIG.

FIG. 3 is an explanatory diagram showing an electrical configuration of the pachinko machine 10 by blocks.

FIG. 4 is an explanatory diagram showing a main hardware configuration of the pachinko machine 10;

FIG. 5 is an explanatory diagram showing a main configuration of a power supply board 80 together with a connection relationship with each board.

FIG. 6 is an explanatory diagram showing details of a connection relationship between a power supply board 80 and each board.

FIG. 7A is an explanatory diagram showing a connection relationship between a power supply board 80 and a microprocessor 210;
(B) is an explanatory view showing a main configuration of a power supply voltage monitoring IC.

FIG. 8 is a flowchart illustrating a flow of a program start process executed by a sub CPU 212;

FIG. 9 is a flowchart illustrating a flow of a main program process executed by a sub CPU 212;

FIG. 10 is a flowchart illustrating a flow of a command input process executed by a sub CPU 212;

FIG. 11 is a flowchart illustrating a flow of an NMI interrupt process executed by a sub CPU 212;

FIG. 12 is a timing chart showing the rise and fall of the power supply of each substrate.

FIG. 13 is a flowchart illustrating a flow of a power supply voltage monitoring process executed by a CPU 84e.

FIG. 14 is an explanatory diagram illustrating a main configuration of a board control IC that controls each board.

FIG. 15 is a flowchart illustrating a flow of a control start process executed by a CPU 302 illustrated in FIG. 14;

FIG. 16 is a flowchart illustrating a flow of a control termination process executed by a CPU 302;

[Explanation of symbols]

 10 Pachinko machine 70 Main power supply 80 Power supply board (control means) 100 Main board 110 Microprocessor (Main control circuit) 112 Main CPU 200 Payout control board 210 Microprocessor (Payout control circuit) 212 Sub CPU 216 RAM (Prizeball data storage medium) ) 304 ROM (recording medium) C1 capacitor (backup power supply)

Claims (7)

[Claims] A main control circuit that outputs a control command; a payout control circuit that controls a prize ball payout device when the control command output from the main control circuit is input; a main control circuit and a payout control A pachinko machine, comprising: a control unit for generating power required for each circuit and supplying the power to each circuit, and starting control of the main control circuit after starting control of the payout control circuit. . 2. The pachinko machine according to claim 1, wherein the control means terminates the control of the payout control circuit after ending the control of the main control circuit. 3. A prize ball data storage medium for storing data indicating the number of prize balls to be paid out, and prohibiting access to the prize ball data storage medium for a predetermined time after ending the control of the main control circuit. The pachinko machine according to claim 1, further comprising an access prohibiting unit that performs the operation. 4. The pachinko machine according to claim 3, further comprising a backup power supply for backing up data stored in the prize ball data storage medium. 5. The pachinko machine according to claim 1, wherein the payout control circuit starts control after checking that the payout control circuit itself functions normally. 6. The pachinko machine according to claim 1, wherein the main control circuit starts control after checking that the main control circuit itself functions normally. 7. A main control circuit for outputting a control command,
A payout control circuit that controls the prize ball payout device when the control command output from the main control circuit is input, and power supplies required for the main control circuit and the payout control circuit are generated and supplied to the respective circuits. A recording medium provided in a pachinko machine having a power supply circuit, wherein a computer program for controlling at least one of a control start order and a control end order of the main control circuit and the payout control circuit is recorded. recoding media.