JP2001246133A - Game machine and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a game machine in which monitoring of the power source voltage of each board can be standardized to enable the control timing of each board to be precisely controlled. SOLUTION: A power source voltage monitoring IC 84 to monitor the power source voltage supplied to each board is equipped on a power source board 80 and detects voltages of a 32V line 86, a 12v line 87, and a 5V line 88 respectively from a voltage detecting lines A1, A2, and A3. When a detected voltage comes to a prescribed voltage, the power source voltage monitoring IC 84 outputs a reset signal to each board and, when a prescribed time is elapsed, each reset signal is released in the order of a sub-board, a dispense control board 20, and a main board 100. When the detected voltage is out of normal range, the power source voltage monitoring IC 84 sends the reset signal to the each board to which the detected voltage is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine controlled by a computer, such as a pachinko machine, and a recording medium on which a computer program for causing the game machine to function is recorded.

[0002]

2. Description of the Related Art Conventionally, as a gaming machine of this type, when a game ball passes through a predetermined area, a plurality of symbols are variably displayed by a symbol display device, and when a stop symbol is aligned with a predetermined symbol, a big hit is won. There is known a pachinko machine that can pay out a large amount of prize balls by generating the prize holes and opening a large winning opening a plurality of times. In such a pachinko machine, a large number of circuit boards for controlling a game are used. For example, a main board on which a CPU that determines whether or not a big hit is mounted, a payout control board that controls payout of award balls, a special symbol control board that controls display of a special symbol, and a sound effect during a game are controlled. Voice control board, LED and decorative LED that light up when winning
For example, a lamp control board or the like for controlling the operation is used.
In addition, a relay board for relaying a signal and a power supply is provided between the predetermined boards. The power supplied from the main power supply is directly supplied to each substrate, or supplied to each substrate via a relay substrate, and each substrate is transformed into a voltage required by the substrate. Also, a power supply voltage monitoring IC is provided for each board, and when the power supply voltage is out of the set voltage value (normal range), the board is kept in a reset state (initial state), and when the power supply voltage returns to the normal range, the reset state is released. To resume control. Further, when the power supply is started, each substrate starts resetting when the power supply voltage supplied to itself becomes a predetermined voltage, and then releases the reset when a predetermined time has elapsed, thereby starting up the substrate. Decide the order or the order of the shutdown.

[0003]

However, if there is an accuracy error in the set voltage value of the power supply voltage monitoring IC provided for each board between the boards that use the same power supply voltage, Since the timings of the abnormality determination and the normality determination are shifted, the timing of resetting each substrate and the timing of canceling the reset may be shifted. If such a timing shift occurs, for example, a problem arises that normal processing cannot be performed because a part or all of a command transmitted from one substrate cannot be received by the other substrate. That is, in the conventional pachinko machine, it is difficult to make the power supply voltage monitoring the same standard, so that it is difficult to control the control timing of each board with high accuracy. Further, the configuration in which the power supply voltage monitoring IC is provided for each substrate hinders the space saving of each substrate. Further, when the voltage supplied to each substrate fluctuates, the timing at which the voltage monitored by the power supply voltage monitoring IC reaches the reset voltage or the reset release voltage is shifted, so that the reset or reset release timing is shifted. For example, in a gaming machine that controls a game by transmitting a control command from a main board to a payout control board, a special symbol control board, a voice control board, and a ramp control board, when the power is restored after a power failure or other power interruption, the main If a board other than the board rises later than the main board, a situation occurs in which the other board cannot normally receive the control command transmitted from the main board, and there is a problem that the game is not smoothly restarted.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the power supply voltage monitoring for each board can be made to have the same standard, so that the control timing of each board can be controlled with high precision. The aim is to realize a gaming machine that can.

[0005]

In order to achieve the above object, according to the present invention, a plurality of substrates including a main substrate having a function of determining whether or not a hit has occurred are provided. A single power supply unit for generating power required for a predetermined substrate among the plurality of substrates and supplying the power to each substrate; and a voltage of the power supplied to the predetermined substrate by the power supply unit. And a single power supply voltage monitoring means for monitoring.

That is, since the power supply voltage monitoring means for monitoring the voltage of the power supply supplied to a predetermined substrate among the plurality of substrates including the main substrate is single, the same reference voltage for monitoring the power supply voltage is provided for each predetermined substrate. Therefore, the control timing of each predetermined substrate can be controlled with high accuracy. In addition, since it is not necessary to provide a power supply voltage monitoring IC for each predetermined substrate, it is possible to save space for each predetermined substrate. Also, since there is a single power supply means for supplying power to each predetermined substrate, even if the substrate configuration is different for each manufacturing model, only a power supply line is connected from the power supply substrate to each predetermined substrate. Therefore, there is no need to design a power supply path and a transformer circuit for each predetermined substrate for each manufacturing model. Therefore, since the degree of freedom in designing a board can be increased, the production yield of a game machine (for example, a pachinko machine) can be improved. Further, since it is not necessary to provide a transformer circuit for each substrate, it is possible to save the space of the substrate.

According to a second aspect of the present invention, in the gaming machine according to the first aspect, when a predetermined board among the plurality of boards receives a reset instruction, the predetermined board resets its own circuit. The power supply voltage monitoring means uses a technical means for instructing the predetermined substrate to reset when the monitored voltage becomes a predetermined voltage.

In other words, instead of each board independently monitoring the power supply voltage supplied to itself and resetting itself when the monitored voltage reaches a predetermined voltage, a single power supply voltage monitoring means is used. Is configured to issue a reset instruction to each board when the voltage monitored by the board becomes a predetermined voltage, there is no possibility that the reset timing of each board is shifted. Therefore, for example, in the case of a configuration in which each substrate is reset and then started when the voltage supplied to itself after the reset reaches a predetermined voltage and rises, the reset timing affects the reset release timing. It is important that there is no shift in the reset timing, but since there is no shift in the timing, it is possible to reduce the possibility that the subsequent reset release timing will shift. Therefore, for example, in a gaming machine that controls a game by transmitting a command from one board to another board, the board that transmits the command rises later than the board that receives the command, so that the command Although it is important to prevent the occurrence of a reception error, as described above, since the timing of reset release of each board is not likely to be shifted, the possibility of occurrence of a command reception error can be reduced. .

According to a third aspect of the present invention, in the gaming machine according to the first or second aspect, when a predetermined board out of the plurality of boards receives an instruction to release reset, the board itself becomes a predetermined one. The power supply voltage monitoring means uses a technical means of instructing the predetermined substrate to release the reset when the monitored voltage becomes a predetermined voltage.

In other words, each substrate independently monitors the power supply voltage supplied to itself, and resets itself when the monitored voltage reaches a predetermined voltage. Since the reset release instruction is issued to each substrate when the voltage monitored by the means becomes a predetermined voltage, there is no possibility that the timing of reset release of each substrate is shifted. Therefore, for example, in the case of a configuration in which each substrate is reset when the voltage supplied to itself reaches a predetermined voltage, the reset timing affects the reset release timing,
It is important that the reset timing does not shift, but even if the reset timing shifts, the reset release timing may shift because the power supply voltage monitoring means controls the reset release of each board. There is no. Therefore, for example, in a gaming machine that controls a game by transmitting a command from one board to another board, the board that transmits the command rises later than the board that receives the command, so that the command It is important to prevent a reception error from occurring, but as described above, there is no possibility that the reset release timing of each board will be shifted, so that there is no possibility that a command reception error will occur. In particular, if the power supply voltage monitoring means instructs each board to perform both reset and reset release, it is possible to control both reset and reset release of each board in a unified manner. It is possible to control the reset and the reset release sequence with high accuracy by eliminating the shift in the reset release timing.

According to a fourth aspect of the present invention, in the gaming machine according to any one of the first to third aspects, a predetermined board of the plurality of boards receives an instruction of reset release. At this time, each of its own circuits is reset and the power supply voltage monitoring means measures the elapsed time from when the monitored voltage reaches a predetermined voltage, and the measured time reaches the predetermined time. In this case, a technical means of instructing the predetermined substrate to release reset is used.

In other words, the power supply voltage monitoring means determines the timing of instructing each substrate to release the reset based on the time. Therefore, even when the operating voltage of the power supply voltage monitoring means fluctuates, the influence of the fluctuation is not affected. An instruction for reset release can be given to each board at an accurate timing without receiving it.

According to a fifth aspect of the present invention, in the gaming machine according to any one of the first to fourth aspects, the predetermined substrate is electrically connected to the power supply unit and the power supply voltage monitoring unit. , And at least one of the terminals attached to both ends of a predetermined wire among the wires for making the connection is technical means that they are common.

That is, at least one of the terminals attached to both ends of the predetermined line among the lines for electrically connecting the predetermined substrate and the power supply means and the power supply voltage monitoring means respectively is common. Therefore, since it is possible to save the trouble of selecting a line as compared with a case where a terminal having a different terminal is used for each predetermined line, connection processing of each predetermined line can be performed easily and in a short time. Further, since the number of wires that can be used in common is large, the manufacturing cost can be reduced as compared with a case where several types of wires having different terminals are manufactured.

According to the present invention, a plurality of substrates including a main substrate having a function of judging whether or not a hit occurs, and a power supply required for a predetermined substrate among the plurality of substrates are generated. A computer provided with a single power supply means for supplying each substrate and a single power supply voltage monitoring means for monitoring the voltage of the power supplied to the predetermined substrate by the power supply means; Is a recording medium on which a readable computer program is recorded, wherein the power supply voltage monitoring means instructs a reset to the predetermined substrate when the monitored voltage becomes a predetermined voltage, or A technical means of a recording medium on which a computer program for executing a process of instructing reset cancellation to the substrate is used.

That is, for example, as described in an embodiment of the invention described later, a game machine (for example, a pachinko machine)
Functions because the CPU executes a computer program recorded on a recording medium such as a ROM.
By using a recording medium such as a ROM in which a computer program for executing the above processing is recorded,
The gaming machine according to claims 1 to 5 can be realized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a gaming machine according to the present invention will be described below with reference to the drawings. In the following embodiments, a so-called first class pachinko machine will be described as an example of a gaming machine according to the present invention. [Overall Main Configuration] First, the overall main configuration of the pachinko machine of this embodiment will be described with reference to FIG. FIG.
FIG. 1 is an explanatory view of a pachinko machine of this embodiment as viewed from the front. The pachinko machine 10 is provided with a front frame 11 so as to be openable and closable. A metal frame 12 is attached to the front frame 11 so as to be openable and closable.
Is mounted to be openable and closable. A game board 14 is provided inside the glass frame 13. On the lower right of the front frame 11, a firing handle 15 for operating a firing motor (indicated by reference numeral 15e in FIG. 3) for firing game balls to the game board 14.
a is rotatably mounted, and a guide rail 16 is provided on the left side of the game board 14 for guiding a shot game ball to a game area. The firing handle 15a is provided with a firing stop button 15b for stopping the firing operation.

A keyhole decoration 17 having a keyhole 15 into which a key for opening and closing the glass frame 13 is inserted is provided on the right side of the front frame 11, and a frame lamp 18a is provided above the front frame 11. A front plate 19 is provided under the glass frame 13, and a prize ball / lending ball supply port 20a to which a prize ball or a lending ball is supplied is formed on an upper left portion of the front plate 19, On the supply side of the prize ball / lending ball supply port 20a, an upper receiving tray 20 for storing prize balls or lending balls supplied from the prize ball / lending ball supply port 20a is attached. Below the upper tray 20, there is formed an outlet 21a for discharging a prize ball that has flowed in excess of the number that can be accommodated in the upper tray 20, a game ball discharged from the upper tray 20 by operating the upper tray ball removing lever 20b, and the like. Have been. On the discharge side of the discharge port 21a, a lower tray 21 for storing the game balls discharged from the discharge port 21a is provided. On the left side of the front frame 11, there is provided a device outside the gaming machine 22 such as a prepaid card unit having a slit 22a for inserting a prepaid card.

[Main Structure of the Game Board 14] Next, the game board 1
4 will be described with reference to FIG. A center case 30 is provided substantially at the center of the game board 14. The center case 30 has a prize entrance 31
And a normal symbol display device 34 including three LEDs, and 4 indicating the number of times the normal symbol display device 34 is operated.
A normal symbol storage display LED 35 composed of a plurality of LEDs, a special symbol display device 32 for variably displaying a plurality of symbols, for example, 0-9 special symbols on a liquid crystal display, and a display 4 for displaying the number of times the special symbol display device 32 has been started. And a special symbol storage display LED 36 composed of a plurality of LEDs.

On the left and right sides of the center case 30, a normal symbol operation gate 2 for operating the normal symbol display device 34 is provided.
6, 26 are provided. Below the center case 30, a first type starting port 27 having a function of operating the special symbol display device 32 is provided. Below the first type starting port 27, a stop symbol of the ordinary symbol display device 34 is provided. Ordinary electric accessory 28 that opens both wings when hit
Is provided. The opened ordinary electric accessory 28 has a function of starting the operation of the special symbol display device 32, similarly to the first type starting port 27. A variable winning device 40 which is activated when the stop symbol of the special symbol display device 32 hits the symbol is provided below the ordinary electric accessory 28.

The variable winning device 40 is provided with a large winning opening 41 in the form of a door which is opened when a hit occurs, and which is openable and closable on both sides of the large winning opening 41. Are provided respectively. Further, inside the special winning opening 41, there is provided a specific area 42 having a function of continuously opening the special winning opening 41, and a specific area switch (reference numeral 42 in FIG. 3) for detecting a game ball passing through the specific area 42.
a) and a special winning opening switch (indicated by reference numeral 43a in FIG. 3) for counting the number P of game balls that have won the special winning opening 41.

In addition, the game board 14 has windmills 23, 23
, Sleeve entrance prize opening 24, 24, corner decoration lamp 18
b, 18b, a prize lamp 18c that lights up when a prize is won,
An out-of-ball lamp 18d that lights up when the ball runs out, side decoration lamps 18e, 18e, and an out port 45 for collecting game balls that did not win as out balls are provided.
In addition, many nails 25 are driven into the game board 14, and the game balls fired on the game board 14 fall while dancing between the nails 25.

[Electrical Configuration of Pachinko Machine 10] Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. The pachinko machine 10 is provided with a main board 100, on which a microprocessor 110 is mounted. The microprocessor 110 has a main CP for executing game control.
U112 and a ROM 11 in which various control programs for the main CPU 112 to execute various controls are recorded.
And a RAM 116 for temporarily storing various data such as a control program read from the ROM 114 when the main CPU 112 executes various control programs and data relating to a big hit occurring during a game.

The following components are electrically connected to the main substrate 100. Power supply board 80, payout control base 200 for controlling payout of award balls, etc., special symbol display device 3
2. A lamp control device 75 for controlling lamps provided on the game board 14, a sound control device 79 for controlling a sound reproduction device (not shown) for reproducing sound effects during a game, etc., a first type start of a game ball. A first-type start-up switch 27a for detecting the passage of the mouth 27; a game frame information terminal board 5 for transmitting game board information relating to winnings, big hits, etc. to a computer (not shown) provided in a pachinko hall management room or the like;
2. The board relay board 51 and the game frame relay board 55.

The payout control board 200 has a microprocessor 210 which operates by inputting a control command sent from the main board 100. The microprocessor 210 has a sub CPU which controls payout of award balls and the like.
212, a ROM 214 in which various control programs for the sub CPU 212 to execute control such as payout of prize balls, and a control program read from the ROM 214 when the sub CPU 212 executes various control programs and a game And a RAM 216 for temporarily storing various data such as the number of prize balls generated in the RAM. In addition, the power supply board 80, the CR connection board 56, the firing motor drive board 15c for driving the firing motor 15e, the game frame information terminal board 52, and the payout relay board 55 are electrically connected to the payout control board 200. I have.

The game frame relay board 53 has a full detection switch 2 for detecting that the lower tray 21 is full of prize balls.
1b and the sensor relay board 54 are electrically connected. The sensor relay board 54 is electrically connected to the prize ball payout sensors 62a and 62b and the payout relay board 55 provided in the prize ball unit 62. The prize ball unit 62
Prize ball payout sensors 62a, 62b and prize ball payout motor 6
2c. There are two prize ball payout mechanisms for efficiently paying out prize balls, and each payout mechanism is driven by a prize ball payout motor 62c. The prize ball payout sensor 62a is provided in one mechanism, and the prize ball payout sensor 62b is provided in the other mechanism. Detection signals from the prize ball payout sensors 62a and 62b are transmitted from the sensor relay board 54 to the main board 100 via the game frame relay board 53.
The CPU 120 counts the number of paid-out balls based on the signal.

The payout relay board 55 is electrically connected with a ball-out-of-lending switch 61 for detecting that the ball-lending has run out, a prize-ball payout motor 62c, and a ball-lending unit 63. The following components are electrically connected to the board-surface relay board 51. Ordinary electric accessory solenoid 28a for opening and closing the ordinary electric accessory 28, ordinary symbol display device 34, symbol actuation opening switch 26a, large winning opening switch 43a, and sleeve winning opening switch 24 for detecting winning in the sleeve winning opening 24.
a, a lower prize port switch 29a for detecting a prize to the lower prize port 29, a lower prize port switch 31a for detecting a prize to the lower prize port 31;

A special winning area solenoid 42b, a special winning area solenoid 43b, and a specific area switch 42a are electrically connected to the special winning opening relay board 50. The power supply board 80 is electrically connected to the CR connection board 56,
The CR connection board 56 is electrically connected to the gaming machine external device portion 22 including a frequency display board for displaying the remaining frequency of the prepaid card and a device for reading the prepaid card. The power supply board 80 is a 24 V AC (50 Hz / 6
(0 Hz) from the main power supply 70.

[Main Hardware Configuration] Next, the main hardware configuration of the pachinko machine 10 is shown in FIG.
This will be described with reference to FIG. Here, the main CPU 112 of the main board 100 and the sub C of the payout control board 200
The hardware configuration of the interface between the PUs 212 will be described as an example. Main CP of main board 100
Various control commands output from U112
Output to the output port 120 via the PU bus 118;
The output various control commands are temporarily stored in the output buffer 126 via the main CPU parallel output port 124, and then stored in the input buffer 220 connected to the sub CPU 212. And the main CPU
The transfer signal output from the main CPU bus 1
When the trigger signal (TRG2) 226 of the sub CPU 212 is input from the sub-CPU 212 via the output port 122, the output buffer 128, and the input buffer 222, various control commands accumulated in the input buffer 220 are transmitted to the sub-CPU 212.
The data is input to the input port 224 of the sub CPU 212 via the parallel input port 228. And the sub CPU
The 212 performs analysis such as what the captured various control commands mean, and outputs an award ball payout command to the award ball unit 62 based on the analysis result. Note that the main CPU 1 of the main board 100
The hardware configuration between the sub-CPU 12 and the sub CPU mounted on a board other than the payout control board 200 is the same as the above-described configuration.

[Main Configuration of Power Supply Board 80, Power Supply Board 80
Next, the main configuration of the power supply board 80 and the connection relation between the power supply board 80 and each board will be described with reference to FIGS. FIG. 5 is an explanatory diagram showing a main configuration of the power supply board 80 together with a connection relationship with each substrate, and FIG. 6 is an explanatory diagram showing details of a connection relationship between the power supply substrate 80 and each substrate. As shown in FIG. 5, the 24 V AC current supplied from the main power supply 70 is converted to 32 V DC by the rectifier circuit 81 via the fuse F <b> 1 and supplied to the main board 100 and the payout control board 200, respectively. The 32 V direct current is supplied to the DC / DC converter 82.
To 12V. The 12 V DC is applied to the main board 100, the special symbol display device 32, and the lamp control device 7.
5, are supplied to the voice control device 79 and the payout control board 200, respectively. Further, the AC 24 V of the main power supply 70 is supplied to the CR connection substrate 56 through the 24 V line 85 via the fuse F2.

The 32 V DC supplied to the main board 100 is supplied to the board relay board 51 (FIG. 3) to drive the ordinary electric accessory solenoid 28a. Special symbol display device 32
12V DC supplied to the lamp controller 75 drives the liquid crystal and the like of the special symbol display, and the 12V DC supplied to the lamp control device 75 converts the corner decoration lamp 18b and the winning lamp 18c.
Lights or flashes. The 12 V DC supplied to the voice control device 79 drives the speaker via the voice circuit, and the 12 V DC supplied to the payout control board 200.
V direct current is transmitted to the prize ball unit 6 via the payout relay board 55.
2 and the ball rental unit 63, and the prize ball payout motor 62
drive c and the like. Further, the 32 V direct current supplied to the payout control board 200 is supplied to the ball letting unit 63 (FIG. 3) via the payout relay board 69, and a solenoid for operating a shutter member that divides the supplied ballpark by a predetermined number is operated. Drive.

The DC current converted to 12 V by the DC / DC converter 82 is converted to 5 V by the DC / DC converter 83, and the 5 V DC is supplied to the main board 100, the special symbol display device 32, and the lamp control device. 7
5, are supplied to the voice control device 79 and the payout control board 200, respectively. The 5 V DC supplied to the main board 100 serves as a drive power supply for the microprocessor 110 (FIG. 3), and the 5 V DC supplied to the payout control board 200 serves as a drive power supply for the microprocessor 210 (FIG. 3). The 5 V DC supplied to the special symbol display device 32, the lamp control device 75, and the audio control device 79 serves as a drive power supply for a microprocessor (not shown) provided in each device.

That is, the power of each board is supplied from a single power board 80, and the power board 80 controls the power of each board. For this reason, even if the board configuration is different for each manufacturing model, it is only necessary to wire the power supply line from the power board 80 to each board, so that the power supply path and the transformer circuit of each board are different for each manufacturing model. There is no need to design. Therefore, since the degree of freedom in designing the substrate can be increased, the production yield of the pachinko machine can be improved. Further, since it is not necessary to provide a transformer circuit for each substrate, it is possible to save the space of the substrate.

As shown in FIG. 6, the power supply board 80 has a No. for supplying power to the main board 100. A 6-pin connector CN2a of 1 to 6 is attached, and this connector CN2a is connected to a connector CN1 attached to the main board 100 by a cable L1. Cable L1
Has a terminal C for connecting to the connector CN2a.
N2b is attached, and a terminal (not shown) for connecting to the connector CN1 on the main board 100 side is attached to the other end. The power supply board 80 has the No. for supplying power to the payout control board 200. An 8-pin connector CN3a of 1 to 8 is attached, and the connector CN3a is connected to the payout control board 200 by a cable L2.
Is connected to the connector CN1 attached to the. A terminal CN3b for connection to the connector CN3a is attached to one end of the cable L2, and a terminal (not shown) for connection to the connector CN1 on the payout control board 200 is attached to the other end. .

Further, the power supply board 80 includes a connector CN.
7a, CN4a, CN5a, CN6a, CN1a are attached. The connector CN7a is connected to the CR connection board 56 by a cable L3.
Is connected to a connector CN7a at one end.
7b is attached, and a terminal (not shown) for connecting to the connector CN2 on the CR connection board 56 side is attached to the other end. The connector CN4a is connected to the cable L4
Is connected to a special symbol control board 32a provided in the special symbol display device 32, a terminal CN4b for connecting to the connector CN4a is attached to one end of the cable L4, and a special symbol control board is attached to the other end. A terminal (not shown) for connecting to the connector CN1 on the 32a side is attached.

The connector CN5a is connected to a lamp control board 75 provided in the lamp control device 75 by a cable L5.
a terminal CN5b for connecting to the connector CN5a is attached to one end of the cable L5, and the connector CN on the lamp control board 75a side is attached to the other end.
A terminal (not shown) for connecting to the terminal 1 is attached. The connector CN6a is connected to a voice control board 79a provided in the voice control device 79 by a cable L6. A terminal CN6b for connecting to the connector CN6a is attached to one end of the cable L6, and the other end is connected to the other end. A terminal (not shown) for connecting to the connector CN1 on the audio control board 79a side is attached. Connector C
N1a is connected to the main power supply 70 by a power cord L7, and one end of the power cord L7 has a connector CN1a.
A terminal CN1b for connection to the terminal is attached.

Further, since the cables L4 to L6 have the same number of terminal pins, a common cable can be used. Therefore, it is possible to save the trouble of selecting a cable as compared with a case where cables having different numbers of terminal pins are used, so that the cable connection processing can be performed easily and in a short time. In addition, since the number of cables that can be used in common is large, the manufacturing cost can be reduced as compared with the case where many types of cables having different numbers of terminal pins are manufactured.

[Voltage Monitoring Function] Next, the function of monitoring the voltage of the power supplied from the power supply board 80 to each board will be described with reference to FIGS. 5, 6 and 7B.
FIG. 7B is an explanatory diagram illustrating a main configuration of the power supply voltage monitoring IC. As shown in FIG. 5, the power supply board 80 is provided with a power supply voltage monitoring IC 84 for monitoring the voltage of the power supply supplied to each board. Power supply voltage monitoring IC84
Are 32V line 86, 12V line 87, 5V line 8 from voltage detection lines A1, A2 and A3, respectively.
8 is detected. The power supply voltage monitoring IC 84 is shown in FIG.
As shown in (B), an A / D conversion circuit 84a that converts a voltage detected from the 32V line 86 into a digital signal,
A / D conversion circuit 84b for converting a voltage detected from 12V line 87 to a digital signal, and A / D conversion circuit 8 for converting a voltage detected from 5V line 88 to a digital signal
4c and a CPU 84e.

The CPU 84e includes a ROM 84h and an RA
Built-in M84i. The ROM 84h stores a computer program executed by the CPU 84e.
The AM 84i temporarily stores the calculation results and processing results of the CPU 84e. Each A / D conversion circuit is connected to a CPU 84e. The CPU 84e fetches a digital signal output from each A / D conversion circuit, calculates a voltage according to a voltage calculation program stored in a ROM 84h, Based on the calculated value, it is determined whether the voltage has increased or decreased to a predetermined voltage. Further, the CPU 84e measures the elapsed time from the time of the above determination using a clock signal. And the CPU 84e
Is connected to each substrate, and outputs a RESET signal to each substrate or cancels the RESET signal according to the above determination result.

[Data Backup Function] Next, a function of backing up data stored in the RAM 216 built in the microprocessor 210 will be described with reference to FIGS. 5 and 7A. FIG. 7A is an explanatory diagram showing a connection relationship between the power supply board 80 and the microprocessor 210. In the following description, the sub-substrate refers to each substrate other than the main substrate 100 and the payout control substrate 200. As shown in FIG. 5, the DC / DC converter 8
Power supply line 8 for connecting 3 to payout control board 200
A diode D1 is connected in series to 3a, and a capacitor C1 as a backup power supply is connected in parallel to the output side of the diode D1. This capacitor C1
Is charged by a 5 V DC current supplied from the DC / DC converter 83. The discharge current of the capacitor C1 is supplied to the built-in RAM backup power supply terminal VBB of the microprocessor 210 via the backup power supply line L2a in the cable L2 as shown in FIG.

As shown in FIG. 7A, one of outputs of the voltage monitoring IC 84 is a microprocessor 210.
NMI (Non-Maskable Interrupt) terminal. Here, the connector CN3b (FIG. 6) attached to one end of the cable L2 is removed from the connector CN3a provided on the power supply board 80, or a connector (not shown) attached to the other end of the cable L2 is dispensed. By disconnecting from the connector CN1 (FIG. 6) on the control board 200 side, the supply of the backup power from the capacitor C1 can be stopped. Thereby, the RAM 21
Even if data important for paying out prize balls stored in 6 is rewritten due to electrostatic noise or fraud, the supply of backup power can be stopped quickly and easily. Can be minimized to a minimum. In this embodiment, the capacitor C1 is an electric double-layer capacitor, and has a nominal capacitance of 0.1 F and a rated voltage of 5.5 V. The cables L1 to L6 are FPCs (flexible print circuits).

[Main Control of Power Supply and Discharge Control Board] Next, control of the power supply of each board and main control of the discharge control board 200 will be described with reference to FIGS. 8 to 12 and FIG. FIG. 8 is a flowchart showing the flow of a program start process executed by the sub CPU 212.
FIG. 9 is a flowchart showing the flow of the main program processing executed by the sub CPU 212. FIG. 10 shows sub C
FIG. 11 is a flowchart illustrating a flow of a command input process executed by the PU 212, and FIG. 11 is a flowchart illustrating a flow of an NMI interrupt process executed by the sub CPU 212. FIG. 12 is a timing chart showing the rise and fall of the power supply of each substrate. FIG. 14 is a flowchart showing the flow of the circuit operation start process executed by the CPU 84e of the power supply voltage monitoring IC 84.

(Startup of Power Supply) When the main power supply 70 (FIG. 5) is started, 5V power is supplied from the DC / DC converter 83 (FIG. 5) to the power supply voltage monitoring IC 84.
Power supply voltage monitoring IC 84 from DC / DC converter 82
Is supplied with 12V power. The supplied 5V power is supplied to the 12V power supply by the A / D conversion circuit 84c (FIG. 7B).
The power is converted into a digital signal by the A / D conversion circuit 84b. Those digital signals are respectively taken into the CPU 84e via the output line 84f,
The PU 84e calculates a voltage based on the taken digital signal. Then, the CPU 84e includes an A / D conversion circuit 84c.
V5 calculated based on the digital signal taken from
Is higher than or equal to a voltage Vmin set in advance as the minimum operating voltage of the power supply voltage monitoring IC (step (hereinafter abbreviated as S) 100).

Subsequently, the CPU 84e determines that the voltage V5 is
If it is determined that it is not less than min (S100: Yes), R
ESET signals 1 to 5 (low level) are output to the corresponding substrate (S102). The RESET signal 1 is to the lamp control board 75a (FIG. 6), the RESET signal 2 is to the voice control board 79a, and the RESET signal 3 is to the special symbol control board 32a.
RESET signal 4 to the payout control board 200
The ET signal 5 is output to the main board 100, respectively. Subsequently, the CPU 84e determines whether or not the voltage V5 has become equal to or higher than the sub-substrate rise detection voltage Vus (S104). The sub-substrate rise detection voltage Vus is a voltage for detecting a reference timing for measuring the time Trs until the timing to release the reset of the sub-substrate (FIG. 12). When determining that the voltage V5 has become equal to or higher than the voltage Vus (S104: Yes), the CPU 84e starts measuring the time Trs. The signals 1 to 3 are released (S108). Thereby, the lamp control board 7
5a, voice control board 79a and special symbol control board 32
a is released from the reset state, and the control command transmitted from the main board 100 becomes receivable (low level → high level).

Subsequently, the CPU 84e operates the A / D conversion circuit 8
It is determined whether the voltage V12 calculated based on the digital signal fetched from 4b is equal to or higher than the payout control board rise detection voltage Vuh (S110). The payout control board rise detection voltage Vuh is the voltage V12 when the reset of the sub-form board is released.
This is a voltage for detecting a reference timing for measuring a time Trh from when the sub-substrate is reset to when the dispensing control board 200 is reset (FIG. 1).
2). When the CPU 84e determines that the voltage V12 has become equal to or higher than the voltage Vuh (S110: Yes), the CPU 84e starts measuring the elapsed time Trh from when the reset of the sub-assembled substrate is released, and the measured time T becomes equal to or longer than the time Trh. If it is determined that it has become (S112: Yes), the RESET signal 4 is released (S114). Thereby, the payout control board 200
Is reset, and the control command transmitted from the main board 100 becomes receivable (low level → high level). At this time, the sub CPU 21 of the payout control board 200
2 (FIG. 7A) executes a security check. In this security check, it is checked whether or not there is any abnormality in the computer program recorded in the ROM 214. Subsequently, when the security check ends, the sub CPU 212 starts operating.

Subsequently, the CPU 84e determines whether or not the voltage V12 is equal to or higher than the main board rise detection voltage Vum (S1).
16). The main board rise detection voltage Vum is the payout control board 20
0 is a voltage V12 when the reset is released, and is a voltage for detecting a reference timing for measuring a time Trm from the reset release of the payout control board 200 to the reset release of the main board 100 (FIG. 12). . And CPU
84e, when it is determined that the voltage V12 has become equal to or higher than the voltage Vum (S116: Yes), measurement of the elapsed time Trm from when the dispensing control board 200 is reset is started,
When it is determined that the measured time T has become equal to or longer than the time Trm (S118: Yes), the RESET signal 5 is released (S120). As a result, the reset of the main board 100 is released, and the main CPU 112 (FIG. 4) executes a security check. In this security check, R
A check is made as to whether there is any abnormality in the computer program recorded in the OM 114. Subsequently, when the security check is completed, the sub CPU 212 starts the operation, and becomes capable of transmitting a control command to the payout control board 200 and the sub-formed board (from low level to high level).

Incidentally, an IC chip constituting the microprocessor 210 of the payout control board 200 and the main board 10
The time required to execute its own security check due to a difference in type from the IC chip constituting the microprocessor 110 of the “0”, or due to a variation in characteristics even for the same IC chip. , The two microprocessors may be different. For example, the microprocessor 110 is
If the time required to execute its own security check is shorter than that of the main board 100, the security check of the main board 100 ends while the payout control board 200 is executing the security check. There is a possibility that the output control board 200 cannot receive the output command. When such a situation occurs, for example, when the power is restored after a power failure, when paying out award balls based on the backed up winning data, the payout control board 200 transmits the payout control command of the payout control command transmitted from the board 100. There is a possibility that the reception fails and the prize balls cannot be paid out, or the number of prize balls paid out becomes incorrect. But,
If the time Trm is set to a time sufficient for the payout control board 200 to execute its own security check, the main board 100 becomes operable after the payout control board 200 becomes operable. , Payout control board 2
00 does not fail to receive the control command transmitted from the main board 100. Therefore, the correct number of payout balls can be paid out after the power is restored.

(Program Start Process of Sub CPU 212) Here, a program start process executed by the sub CPU 212 will be described with reference to FIG. Sub C
The PU 212 sets interrupt prohibition (S10), and sets a stack pointer for holding the address of the main routine at the bottom of the address when shifting from the main routine to the subroutine (S12). Then sub CP
The U212 sets access permission to the RAM 216 (S14), and sets the interrupt mode to mode 2 (S1).
6). Subsequently, the sub CPU 212 sets an address to be used in mode 2 in the interrupt register (S18).
It is determined whether the check data in the RAM 216 is correct, for example, whether it is A5A5H (S20). If the check data is correct (S20: Yes), the RAM 2
Clear other than the backup area in 16 to 0 (initialization)
If the check data is not correct (S20: N
o), the entire area of the RAM 216 (for example, 256 bytes)
Are all cleared to 0 (initialization) and check data (for example, A5A5H) is stored (S24). Subsequently, the sub CPU 212 initializes a built-in device such as a watchdog timer which is a timer for monitoring runaway of the sub CPU 212 (S26), and initializes a work area (S28). Subsequently, the sub CPU 212 sets interruption permission (S30), and shifts to an infinite loop in which this S30 is repeated. Then, the system reset signal of the main board 100 is released after a time Trm after the 12V power supply reaches the voltage Vum, and the main CPU 112 of the main board 100 starts the operation after executing the security check. At this stage, the pachinko machine 10 is in a playable state. As described above, since control can be started in the order of the sub-substrate, the payout control substrate 200, and the main substrate 100, a command reception omission from the main substrate 100 occurs in all the substrates managed by the main substrate 100. Never do.

(Main Program Processing of Sub CPU 212) Here, the flow of the main program processing executed by the sub CPU 212 of the payout control board 200 will be described with reference to FIG. This main program processing is performed by CTC
This is executed by a channel 3 interrupt of (timer counter) 218 (FIG. 7). The sub CPU 212 sets interruption permission (S100) and restarts the watchdog timer (S200). Subsequently, the sub CPU 212
Is based on data from the output process (S300), input process (S400), storage of the number of prize balls to be paid out and prize ball processing (S500) such as a payout command, and data from the CR connection board 56 (FIG. 3). A ball lending process (S600) for controlling the ball lending unit 63 is executed.

(Command Input Processing of Sub CPU 212)
Next, a flow of a command input process executed by the sub CPU 212 will be described with reference to FIG. This command input processing is executed by the channel 2 interrupt of the CTC 218. The sub CPU 212 inputs a control command such as a payout command sent from the main board 100 (S50), and checks the input control command (S52). For example, the control command is 2 bytes composed of an 8-bit signal, and is distributed to each byte. Subsequently, the sub CPU 212 determines whether the input control command is a control command meaning, for example, a command indicating a payout command of 5 prize balls, a command indicating a payout command of 15 prize balls, or the like. Analysis is performed (S54), and interruption permission is set (S56). As described above, the command input process is assigned to the channel 2 interrupt, and is executed in the second priority order following the NMI interrupt process described later. For example, the sub CPU 212 outputs a pulse to the winning ball payout motor 62c. Even if the main board sends a control command for paying out a prize ball, the control command can be analyzed with priority. Therefore, it is possible to eliminate a prize ball payout error or a delay in award ball payout due to a failure to receive a control command from the main board 100.

(Shutdown of power supply) The main power supply 70 is shut down due to power cutoff, power outage, or power supply abnormality at the end of pachinko hall business, and when the 12V power supply reaches the voltage Vdm, the system is reset to the main board 100. A signal is generated (high level → low level). Subsequently, when the 12 V power supply reaches the voltage Vdh (for example, 10.3 V), an NMI signal is generated, and this NMI signal continues for a time period Tnmi. During this time Tnmi, data such as the number of award balls
It is backed up to AM 216. At this time, the discharge current of the capacitor C1 (FIG. 5) is
Is supplied to the backup power supply terminal VBB (FIG. 7), so that the RAM 216 can maintain the storage of data such as prize ball data. (NMI Interrupt Process of Sub CPU 212) Here, the NMI interrupt process executed by the sub CPU 212 is shown in FIG.
This will be described with reference to FIG. When the NMI signal is generated, the sub CPU 212 sets access prohibition in the access register for the RAM 216 (S70). This interrupt process is executed with the highest priority over other interrupt processes. In other words, by prohibiting access to the RAM 216, the prize ball data stored in the RAM 216 is prevented from being rewritten.

For example, if another interrupt process has already been executed at the time of backing up the RAM 216 and a new interrupt has been prohibited, and if the processing time of the other interrupt process becomes longer, an interrupt is thereafter issued. If processing is permitted and access to the RAM 216 is to be prohibited, it may be too late to destroy part or all of the stored contents of the RAM 216. Therefore, NMI
By prohibiting access to the RAM 216 by interrupt processing, destruction of the storage contents of the RAM 216 is prevented. When the time Tnmi has elapsed, the NMI signal stops, a system reset signal is generated in the payout control board 200, and the payout control board 200 is reset. Then, 5
When the V power supply reaches the voltage Vds, a system reset signal is generated on the sub-substrate, and the sub-substrate is reset. If the power is turned on while the RAM 216 is being backed up, the sub CPU 212
The prize ball payout motor 62c (FIG. 3) is driven with reference to the prize ball number stored in the 216, and the prize ball corresponding to the prize ball number is paid out.

(Power supply monitoring process) Next, the power supply voltage monitoring I
The flow of the power supply voltage monitoring process executed by the CPU 84e provided in the C84 will be described with reference to the flowchart of FIG. Here, a case where the voltage of the 12V line 87 is monitored will be described as an example. C
When the PU 84e fetches a timing signal from a timer (not shown) and determines that it is the timing to detect the power supply voltage (S80: Yes), the PU 84e sends each A / D conversion circuit via the control line 84g (FIG. 7B). A control signal is sent to the server (S82). Each of the A / D conversion circuits taking in the control signal takes in current from each voltage line, converts the voltage value of the taken current into a digital signal,
84e.

Then, the CPU 84e calculates the voltage V1 by counting the received digital signal, and determines whether the voltage V1 is equal to or lower than a predetermined voltage (S86). here,
The predetermined voltage is, for example, the minimum operating voltage required for the functioning of the board, and is 10.3 V for a board with a 12 V power supply, for example. Subsequently, the CPU 84e sets the voltage V
If 1 is 10.3 V or less (S86: Yes),
RESET to each board functioning with 12V power supply
A signal is transmitted (S88), and a notification LED 89 (FIG. 5) provided at a predetermined location of the pachinko machine 10 (for example, on a board for transmitting a RESET signal or at a location visible from the outside of the pachinko machine 10) is lit. (S9
0). By turning on the notification LED 89, it is possible to report that a non-functioning substrate has occurred due to a decrease in the power supply voltage. For this reason, a measure for restoring the function of the substrate can be performed at an early stage. When the power supply voltage is restored to a normal voltage, a reset release signal is sent from the power supply voltage monitoring IC 84 to each of the reset substrates, the reset state of each substrate is released, and each substrate resumes control.

[Effects of Embodiment] (1) As described above, if the pachinko machine 10 of this embodiment is used, one power supply voltage monitoring IC 84 monitors the power supply voltage of each board, and a certain voltage abnormality is detected. Is detected, each substrate to which the voltage is supplied can be simultaneously reset or the reset state can be released, so that the control timing of each substrate can be controlled with high accuracy. Moreover, since there is no need to provide a power supply voltage monitoring IC for each board,
Space saving of each substrate can be achieved.

(2) Also, each board independently monitors the power supply voltage supplied to itself, and does not reset itself when the monitored voltage reaches a predetermined voltage. Since the RESET signal is transmitted from the power supply voltage monitoring IC 84 to each board when the voltage monitored by the IC 84 reaches a predetermined voltage, each board can be reset at the same time. And RESE
The release of the T signal is also performed by the power supply voltage monitoring IC 84 in a unified manner, and the sub-substrate, the dispensing control substrate 200, and the main substrate 100 are reset-released in this order, and the main substrate 100 is reset at the latest timing. Also, there is no possibility that the control command transmitted from the main board 100 cannot be received by the payout control board 200 and the sub-formed board.

(3) Further, in the above embodiment, the sub-substrate rise detection voltage Vus and the payout control substrate rise detection voltage V
Although the case where the respective voltage values of uh and the main board rise detection voltage Vum are different from each other has been described, the reset of the sub-substrate, the payout control board 200, and the main board 100 is instructed by the control of the power supply voltage monitoring IC 84. Even in the case where the respective voltage values are set to be the same, it can be specified that the voltage rises in the order of the sub-substrate, the payout control substrate 200, and the main substrate 100. That is, the start-up order of each substrate can be defined by software processing. Therefore, even if there is a slight variation in the time required for security check and the circuit operation time between each board, the order of starting each board can be specified regardless of the variation. The accuracy of the rise timing can be improved. Further, since the power supply voltage monitoring IC 84 determines the timing of instructing each substrate to release the reset based on the time, even if the operating voltage of the power supply voltage monitoring IC 84 fluctuates, it is affected by the fluctuation. Without this, an instruction for reset release can be issued to each board at an accurate timing.

(4) Further, since there is a single power supply means for supplying power to each substrate, a power supply line is provided from the power supply substrate to each substrate even if the substrate configuration is different for each manufacturing model. Since only wiring is required, there is no need to design a power supply path and a transformer circuit for each board for each manufacturing model. Therefore, since the degree of freedom in designing the substrate can be increased, the production yield of the pachinko machine can be improved. Further, since it is not necessary to provide a transformer circuit for each substrate, it is possible to save the space of the substrate. The main CPU 112 or the sub CPU 212
The voltage can be monitored by using this function. In this case, the voltage monitoring may be independent of other processing, or may be interrupt processing.

[Other Embodiments] (1) In the above embodiment, the case where the CPU 84e performs both resetting and resetting of each board has been described. However, only resetting is performed. It is also possible to detect a rise in the voltage and release the reset itself when the detected voltage reaches a predetermined voltage. (2) Further, the CPU 84e performs only the reset release of each board, and the reset is configured such that each board detects its own voltage rise and resets itself when the detected voltage reaches a predetermined voltage. You can also. (3) Further, in each of the above-described embodiments, the first-type pachinko machine is described as an example of the gaming machine according to the present invention, but the second-type pachinko machine, the third-type pachinko machine, and other types of pachinko machines are described. Of course, the present invention can be applied to other game machines such as a pachinko machine or a slot machine.

[Correspondence between Claims and Embodiments] The power supply board 80 functions as power supply means, and the power supply voltage monitoring IC 84 functions as power supply voltage monitoring means. Also,
The ROM 84h functions as the recording medium according to claim 6. Then, S100 to S12 executed by the CPU 84e.
0 functions as the power supply voltage monitoring means according to claim 2 and corresponds to the processing according to claim 6.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a pachinko machine according to an embodiment of the present invention as viewed from the front.

FIG. 2 is an explanatory diagram showing a main configuration of a game board 14 provided in the pachinko machine 10 shown in FIG.

FIG. 3 is an explanatory diagram showing an electrical configuration of the pachinko machine 10 by blocks.

FIG. 4 is an explanatory diagram showing a main hardware configuration of the pachinko machine 10;

FIG. 5 is an explanatory diagram showing a main configuration of a power supply board 80 together with a connection relationship with each board.

FIG. 6 is an explanatory diagram showing details of a connection relationship between a power supply board 80 and each board.

FIG. 7A is an explanatory diagram showing a connection relationship between a power supply board 80 and a microprocessor 210;
(B) is an explanatory view showing a main configuration of a power supply voltage monitoring IC.

FIG. 8 is a flowchart illustrating a flow of a program start process executed by a sub CPU 212;

FIG. 9 is a flowchart illustrating a flow of a main program process executed by a sub CPU 212;

FIG. 10 is a flowchart illustrating a flow of a command input process executed by a sub CPU 212;

FIG. 11 is a flowchart illustrating a flow of an NMI interrupt process executed by a sub CPU 212;

FIG. 12 is a timing chart showing the rise and fall of the power supply of each substrate.

FIG. 13 is a flowchart illustrating a flow of a power supply voltage monitoring process executed by a CPU 84e.

FIG. 14 is a flowchart illustrating a flow of a circuit operation start process executed by a CPU 84e of a power supply voltage monitoring IC 84;

[Explanation of symbols]

 Reference Signs List 10 pachinko machine (game machine) 70 main power supply 80 power supply board (power supply means) 84 power supply voltage monitoring IC (power supply voltage monitoring means) 84e ROM (recording medium) 100 main board 112 main CPU 200 payout control board 212 sub CPU CN1 , CN3a, CN3b Connector (terminal)

Claims (6)

[Claims] 1. A plurality of substrates including a main substrate having a function of determining whether or not a hit has occurred, and a power source required for a predetermined substrate among the plurality of substrates is generated and supplied to each substrate. And a single power supply voltage monitoring means for monitoring the voltage of the power supplied to the predetermined substrate by the power supply means. 2. The method according to claim 1, wherein the predetermined substrate among the plurality of substrates is:
Upon receiving a reset instruction, resetting the circuits included therein, and the power supply voltage monitoring means instructs the predetermined substrate to reset when the monitored voltage becomes a predetermined voltage. The gaming machine according to claim 1, wherein: 3. A predetermined substrate among the plurality of substrates,
Upon receiving a reset release instruction, each of the circuits included therein is reset released, and the power supply voltage monitoring unit releases the reset to the predetermined substrate when the monitored voltage becomes a predetermined voltage. The gaming machine according to claim 1 or 2, wherein the game machine is instructed. 4. A predetermined substrate among the plurality of substrates,
Upon receiving the reset release instruction, each of the circuits included therein is released from the reset, and the power supply voltage monitoring unit measures a time until the timing to instruct the predetermined substrate to release the reset, and measures the measurement time. The gaming machine according to any one of claims 1 to 3, wherein when a predetermined time has elapsed, a reset release instruction is issued to the predetermined substrate. 5. The predetermined board is electrically connected to the power supply means and the power supply voltage monitoring means, respectively, and terminals of terminals attached to both ends of a predetermined wire among the wires for making the connection. The gaming machine according to any one of claims 1 to 4, wherein at least one of them is common. 6. A plurality of substrates including a main substrate having a function of determining whether or not a hit has occurred, and a single power supply required to generate a power supply required for a predetermined substrate among the plurality of substrates and to supply the power to each substrate A power supply means, and a single power supply voltage monitoring means for monitoring the voltage of the power supply supplied to the predetermined substrate by the power supply means, a computer program readable by a computer A recording medium in which the power supply voltage monitoring means instructs a reset to the predetermined board or a reset release to the predetermined board when a monitored voltage becomes a predetermined voltage. A recording medium on which a computer program for executing a process to be executed is recorded.