JP2002085774A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine having a structure for a control program and control data that can be easily used on other models. SOLUTION: In a control data area, a built-in device register setting table and a CTC and PIO setting table are in the front. A working space and work area setting table is stored next. The working space and work area setting table is a table for setting an initial value of the working space and work area (RAM) used by a CPU during the execution of game control and setting the set value of an work area in each condition during the progression of a game. Data, the common use of which among a plurality of models is improbable are arranged in the rear in a storage area to store control data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, and a slot machine in which a game is played according to a player's operation.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is in a state that is advantageous for a player who is likely to win a hit ball, or is in a state that is advantageous for the player. In other words, the right is to be generated, or the condition for paying out premium game media is easily established. Further, when a predetermined amount of game balls or coins are awarded or points are added in accordance with establishment of predetermined conditions such as winning, these are referred to as value or valuable value.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a big hit.

[0006] The game progress in the gaming machine is controlled by game control means including a game control microcomputer and the like. The game control microcomputer performs game control according to a program stored in the ROM.

When predetermined data is set in the ROM and the game control microcomputer performs game control, RO
The use of data stored in M makes it possible to save the ROM capacity and facilitate maintenance of the program. A lot of control data is used for game control, but if such control data is described in a program, it is necessary to use a long (large number of bytes) instruction code and the program is difficult to read. Because it becomes. Note that typical control data in the game control include data indicating a pattern of variable display of symbols, data indicating a control command for control means other than the game control means, data indicating the number of winning balls according to winning, and the like. .

[0008]

If data corresponding to various control data and the like is stored in the ROM, the program structure can be easily viewed by referring to the data in the ROM in the program. Become.
As a result, it becomes easy to divert the program to another model. This is because, when diverted to another model, there is a high possibility that only the data set in the data area of the ROM needs to be changed without changing the program itself. However, when the number of prize balls is changed in accordance with a prize, it is sufficient to simply change the data indicating the number of prizes, but when it is necessary to change a relatively large amount of data, the program may be changed. May need to be changed.
For example, when the number of types of variable display patterns increases or decreases, the size of the data area in which each data indicating each variable display pattern is set changes. Then, the starting address of the following data in the ROM changes. As a result, it is necessary to change the reference address in the instruction that refers to the data set in the area following the data area in which the data indicating the variable display pattern is set. That is, the program needs to be changed.

Therefore, the present invention has a structure relating to a control program and control data which further reduces the possibility of having to change a program when diverted to another model and makes it easier to divert to another model. It is intended to provide a gaming machine.

[0010]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can play a predetermined game, and uses a control program and control data (for example, control data stored in a ROM) whose contents do not change due to the progress of the game. Equipped with a microcomputer that performs control, control data that is commonly used by multiple models is located at the front of the storage area that stores control data, and may be commonly used by multiple models Is characterized in that the control data having a low value is arranged at the rear of the storage area for storing the control data. Note that the front part is an area having a relatively small address in a storage area of a predetermined size for storing control data, and the rear part is an area closer to the final address in the storage area.

The control data commonly used by a model having a function of renting out game media in response to a player's operation and a model having no function of renting out game media (so-called cash machine) is control data. Is preferably arranged at the front of the storage area for storing

[0012] The storage area for storing the control data may be arranged such that an empty area is located at the rearmost position in the storage area.

When the microcomputer has a built-in device other than the CPU, the control data for initial setting of the register of the built-in device is preferably arranged at the front of the storage area.

The control data for initial setting of the work area used when the microcomputer executes the control program is preferably arranged at the front of the storage area.

The game control means includes a game control means including a microcomputer for controlling the progress of the game, and an electric component control means for controlling electric components provided in the game machine in accordance with a command from the game control means. May be configured so that data of a command output to the electric component control means is arranged between a front part and a rear part (hereinafter also referred to as an intermediate part) in a storage area for storing control data. .

The control data for creating a command output from the game control means to the electric component control means includes at least control data for initial setting of a register of a built-in device and control data for initial setting of a work area. You may comprise so that it may be arrange | positioned after data.

The gaming machine includes a variable display device capable of variably displaying the identification information, and starts variably displaying the identification information in response to a condition for starting the change, and the display result of the identification information is a predetermined display. A gaming machine that can be controlled to a specific gaming state that is advantageous to the player on condition that the mode is set, and the control data relating to the display result of the identification information is:
It may be configured to be arranged at an intermediate part in a storage area for storing control data.

The control data relating to the display result of the identification information is arranged at least after the control data for initial setting of the register of the built-in device and the control data for initial setting of the work area. It may be.

In the case where the gaming machine is a gaming machine that can be controlled to a special gaming state in which the probability that the display result of the identification information becomes a specific display mode is increased, control data relating to the transition to the special gaming state is provided. May be arranged at the rear of the storage area.

[0020]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section (special symbol display device) 9 for variably displaying a plurality of types of symbols and an ordinary symbol display (ordinary symbol display device) 10 using 7-segment LEDs are provided. A variable display device 8 is provided. In the variable display section 9, for example, "left", "middle",
There are three symbol display areas of "right". Variable display device 8
Is provided with a passage gate 11 for guiding a hit ball. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
Below, is provided a start winning storage display 18 having four displays for displaying the number of winning balls entering the start winning port 14. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls into the respective winning ports 19 and 24 is determined by setting the corresponding winning port switches 19a and 19a.
19b, 24a and 24b. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the number displayed on the symbol display 10 normally changes. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17,
If the change of the symbol can be started, the symbol in the variable display section 9 starts rotating. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol = small hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball dispensing device covered with a prize ball case 40A.

On the back side of the gaming machine, a variable display control unit 29 including a symbol control board for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. . In addition, a payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted, and a hitting ball launching device that shoots a hitting ball into the game area 7 using the rotational force of a motor are provided. Furthermore, the decoration lamp 25, the game effect LED 28a,
Lamp control board 3 for sending signals to gaming effect lamps 28b and 28c, award ball lamp 51 and ball out lamp 52.
5. A sound control board 70 for controlling sound generation from the speaker 27 and a launch control board 91 for controlling the hit ball launching device are also provided.

Further, DC30V, DC21V, DC1
A power supply board 910 on which a power supply circuit for generating 2V and 5V DC is mounted is provided, and a terminal board 1 provided with terminals for outputting various information to the outside of the gaming machine is provided above.
60 are installed. The terminal board 160 has at least a ball-out terminal for introducing the output of the ball-out detection switch and outputting it externally, a prize-ball terminal for externally outputting the prize ball number signal, and a predetermined number of ball lending. A ball lending terminal for externally outputting the generated ball lending signal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided.

In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are transmitted to the game effect LEDs 28a, game effect lamps 28b, 28 provided on the frame side.
c, an illuminated relay board A77 for supplying to the prize ball lamp 51 and the ball cut lamp 52 is shown, but other relay boards are provided as needed for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The balls stored in the ball storage tank 38 pass through the guide gutter 39, pass through the ball cut detectors (ball cut switches) 187a and 187b, and are dispensed through the ball supply gutters 186a and 186b, as shown in FIG. The device 97 is reached. The ball out switches 187a and 187b are switches for detecting the presence or absence of a game ball in the game ball passage.
67 is also provided. Hereafter, the ball out switch 187
a, 187b may be expressed as a ball-out switch 187.

The game balls paid out from the ball payout device 97 are supplied to the hitting plate 3 provided on the front of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed.

A large number of premium balls are paid out based on the winning, and the hitting ball supply tray 3 is filled up.
When the game balls are further paid out after reaching 5, the game balls are guided to the surplus ball tray 4 via the surplus ball passage 46. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In that state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hit ball firing device 34 also stops.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a firing control board 91, and a symbol control board 80.
Hereinafter, the payout control board 37, the lamp control board 35,
The sound control board 70 and the symbol control board 80 may be referred to as electric component control boards. Control means including a microcomputer mounted on the electric component control board may be referred to as electric component control means. Among the electric components controlled by the electric component control means, those related to the game effect are effect components. The lamp control board 35, the sound control board 70, and the symbol control board 80 are also examples of the effect component control board. The electric component control means (lamp control means, sound control means, and display control means) mounted on the lamp control board 35, the sound control board 70, and the symbol control board 80 are also examples of the effect component control means.

On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, a starting port switch 17, a V count switch 2
2, count switch 23, winning opening switch 19a, 1
9b, 24a, 24b, a full circuit switch 48, a ball cutout switch 187, a switch circuit 58 for supplying signals from the prize ball count switch 301A to the basic circuit 53, a solenoid 16 for opening and closing the variable prize ball device 15, and an opening and closing plate 2.
And a switching solenoid 21A for switching the path in the special winning opening.
And a solenoid circuit 59 driven in accordance with a command from the controller.

Although not shown in FIG. 4, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58.

An address decoding circuit 67 for decoding an address signal supplied from the basic circuit 53 and outputting a signal for selecting one of the I / O ports in the I / O port unit 57; According to the data given from 53, the jackpot information indicating the occurrence of the jackpot, the validity outputted when the variable display is stopped so that the number of the winning prize balls used for starting the image display of the variable display section 9 can be specified externally. An information output circuit 64 for outputting an information output signal such as start information and probability change information indicating that a probability change has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal.

Further, the main board 31 is provided with a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decoration lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52. The display control of the variable display unit 9 for variably displaying special symbols and the ordinary symbol display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 5 shows the circuit configuration in the symbol control board 80 by using an LCD (liquid crystal display) 82 as an example of the variable display section 9, an ordinary symbol display 10, and an output port (port 0) of the main board 31. , 2) are block diagrams shown together with 570, 572 and output buffer circuits 620, 62A. Output port (output port 2) 572 outputs 8-bit data, and output port 570 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives an INT signal from the main board 31 via the noise filter 107 and the input buffer circuit 105B, and receives a display control command via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, 74HC540 and 74HC14, which are general-purpose ICs, can be used. When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

The display control CPU 101 controls display of a screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 controls the LCD 8 according to the input data.
2 to generate image data to be displayed on the LCD 2, and output R, G, B signals and a synchronization signal to the LCD 82.

FIG. 5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, figures, or symbols displayed on the LCD 82.

The input buffer circuits 105A and 105B
Signals can be passed only in the direction from the main board 31 to the symbol control board 80. Therefore, the symbol control board 8
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B together with the input ports constitute irreversible information input means. Even if the circuit in the symbol control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

The outputs of the output ports 570 and 572 may be output to the symbol control board 80 as they are, but the output buffer circuits 620 and 62A capable of transmitting signals only in one direction.
, The main board 31 to the symbol control board 8
One-way signal transmission to 0 can be more reliably performed. That is, the output buffer circuits 620 and 62A together with the output ports constitute irreversible information output means. By the irreversibility information output means, the input of the illegal signal to the symbol control board 80 via the signal transmission line is surely prevented.

For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 for cutting off the high-frequency signal. The effect is eliminated. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 6 is a block diagram showing a signal transmitting / receiving portion of the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and game effect lamps 28b, 28 provided outside the game area 7 are provided.
c, lighting / extinguishing of the decorative lamp 25 provided on the game board, and lighting / extinguishing of the prize ball lamp 51 and the ball out lamp 52.
A lamp control command indicating turning off is output from the main board 31 to the lamp control board 35. Also, the start memory display 1
8 and the lamp control command indicating the number of lights of the gate passage memory display 41 are also transmitted from the main board 31 to the lamp control board 35.
Is output to

As shown in FIG. 6, the lamp control command relating to the lamp control is output to the output ports (output ports 0, 3) 570, 5 of the I / O port unit 57 in the basic circuit 53.
73. Output port (output port 3) 57
3 outputs 8-bit data, and output port 570 is 1
It outputs a bit INT signal. In the lamp control board 35, a control command from the main board 31 is supplied to the lamp control CPU via input buffer circuits 355A and 355B.
351. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

In the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a, a game effect lamp 28b, and a game effect lamp 28b defined in accordance with each control command.
8c, according to the lighting / extinguishing pattern of the decorative lamp 25,
Game effect LED 28a, game effect lamps 28b, 28
c, output a light-on / light-off signal to the decorative lamp 25; The ON / OFF signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. The lighting / lighting-out pattern is determined by the lamp control CPU.
351 is stored in an internal ROM or an external ROM.

On the main board 31, the CPU 56
When there is an unpaid prize ball remaining number in the memory content of M55, a control command for instructing lighting of the prize ball lamp 51 is output, and the control command is provided upstream of the payout ball passages 186a, 186b on the back of the game board. Ball switch 187a, 187b
When the game ball is no longer detected (see FIG. 3), a control command for instructing lighting of the ball out lamp 52 is output. In the lamp control board 35, each control command is transmitted to the lamp control CPU via input buffer circuits 355A and 355B.
351. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball out lamp 52 according to the control commands. The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a light-on / light-off signal to the start storage display 18 and the gate passage storage display 41 in response to the control command.

As the input buffer circuits 355A and 355B, for example, 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 35
5A and 355B are connected to the lamp control board 35 from the main board 31.
The signal can be passed only in the direction toward. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

In the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside 70 and 573. As the buffer circuits 620 and 63A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the lamp control board 70 to the main board 31 is more reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 7 is a block diagram showing an example of the configuration of the signal transmission portion of the voice control command on the main board 31 and the sound control board 70. In this embodiment, the speaker 2 provided outside the game area 7 according to the progress of the game.
7 is output from the main board 31 to the sound control board 70.

As shown in FIG. 7, the voice control command is
The data is output from output ports (output ports 0, 4) 570, 574 of the I / O port unit 57 in the basic circuit 53.
Output port (output port 4) 574 outputs 8-bit data, and output port 570 outputs 1-bit I
An NT signal is output. In the sound control board 70, each signal from the main board 31 is input to the input buffer circuits 705A and 705A.
Input to the voice control CPU 701 via the interface 05B. When the sound control CPU 701 does not include an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the sound control CPU 701.

For example, the voice synthesis circuit 702 using a digital signal processor
A volume switching circuit 7 that generates a sound or a sound effect according to the instruction 1
03 is output. The volume switching circuit 703 includes a sound control CP
The output level of U 701 is set to a level corresponding to the set volume and output to volume amplifying circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

As the input buffer circuits 705A and 705B, for example, 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the sound control board 70. Therefore, there is no room for a signal to be transmitted from the sound control board 70 side to the main board 31 side. Therefore, even if the circuit in the sound control board 70 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574. As the buffer circuits 620 and 67A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line to which a signal may be supplied from the sound control board 70 to the main board 31 is more reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 8 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch for detecting whether the surplus ball tray 4 is full. In addition, the ball out switch 187 (187a, 187)
The detection signal from b) is also used for the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31.

The CPU 56 of the main board 31 determines whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a payout control command to instruct payout prohibition is transmitted. When receiving the payout control command instructing the payout prohibition, the payout control CPU 37 of the payout control board 37
1 stops the ball payout process.

Further, a detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is provided in the payout mechanism of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven in accordance with the payout control command to perform award ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a RAM.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer driving signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the payout control board 37
Detection signals from the winning ball count switch 301A and the ball lending count switch 301B are input to the relay board 72b via the relay board 72. Ball rental count switch 3
01B is provided in the payout mechanism portion of the ball payout device 97,
Detects the actual loaned ball. Dispensing control board 3
7 is transmitted to the payout motor 289 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37.

The payout control board 37 of the payout control board 37
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 and pays out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31.

In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine separately from the gaming machine is exemplified, but the card unit 50 is integrated with the gaming machine. You may. Also, the present invention can be applied to a case where a gaming machine rents a game ball corresponding to the amount of money when a coin is inserted.

FIG. 9 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a symbol control board 80, a sound control board 70, and a lamp control board 35.
And it is installed independently of the electric component control boards such as the payout control board 37 and generates voltages used by each electric component control board and mechanical components in the gaming machine. In this example, AC24
V, VSL (DC + 30V), DC + 21V, DC + 12
V and + 5V DC. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.
Note that VSL is a rectifier element in the rectifier circuit 912 and is A
It is generated by rectifying and boosting C24V. VSL
Is a solenoid drive power supply.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 includes one or more converters I
C922 (only one is shown in FIG. 9), generates + 21V, + 12V, and + 5V based on VSL and outputs the generated signal to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as +30 V, +12 V, +5 V, etc., decreases relatively slowly. As a result, the capacitor 923 plays a role of an auxiliary driving power supply described later. The connector 915 is connected to, for example, a relay board, and power of a voltage required for each electric component control board and a mechanical component is supplied from the relay board.

However, the power supply board 910 may be provided with each connector leading to each electric component control board, and the power supply board 910 may supply each voltage reaching each board without passing through the relay board. FIG. 9 shows one connector 9.
Although 15 is shown as a representative, a connector is provided for each electric component control board.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is in a storage state with respect to a backup RAM (RAM backed up by a power supply, that is, a backup storage unit that can be in a storage content state even when power supply is stopped) of the electric component control board when power supply to the gaming machine is cut off. Backup power supply that supplies power so that the power can be maintained. Further, a diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line. In this embodiment, +5 V for backup is applied to the main board 31 and the payout control board 37.
Supplied to

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has a power monitoring I
C902 is mounted. The power supply monitoring IC 902
The occurrence of power interruption is detected by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output assuming that power-off occurs. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The power supply cutoff signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect a power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electric component control board to operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall.

Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to an on state.
If the power supply cutoff is recognized by monitoring the + 30V power supply voltage that drops earlier than V, it is possible to enter a state of waiting for the power supply recovery before the switch output turns on and to detect the switch output.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power-off signal to the plurality of electric component control boards. No matter how many electrical component control boards need a power-off signal, it is sufficient that only one power supply monitoring means is provided. Therefore, even if each electrical component control means in each electrical component control board performs return control described later, However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 9, the detection output (power cutoff signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control signal) via buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal.

FIG. 10 is a block diagram showing an example of the internal configuration of the CPU 56 in detail. The CPU core 501 has a built-in register and performs arithmetic processing and the like according to a program. The clock generator 502 divides the frequency of a clock signal supplied from the outside and supplies it to each built-in device. The clock generator 502 can output a 1/2 frequency-divided clock as a system clock from the CLKO terminal.
A clock signal obtained by dividing the system clock can be output from the IEO / SCLK0 terminal via the output control circuit 511.

The reset interrupt controller 503 uses the XR
System reset signal or XNMI input to ST terminal
A non-maskable interrupt request signal or the like input to the terminal is transmitted to the CPU core 501. The external bus interface 504 is
It is a bus driver that performs direction control and drive control of an address bus, a data bus, and various control signals. Built-in RAM5
Reference numeral 5 denotes a power backup, and a program is stored in the built-in ROM 54. The address decoder 505 is
Through the output control circuit 511, four chip select signals XCS0 to XCS3 can be output. The terminals of the chip select signals XCS0 to XCS3 are input / output ports PB0 to PB0.
Also used as 3.

The memory control circuit 510 has a built-in ROM 54
And a signal for controlling the built-in RAM 55 is generated. The memory control circuit 510 has a built-in RAM 55
There is a built-in register that sets whether to allow access to.

The PIO 506 is an 8-bit built-in input port PA0-PA7. When the built-in PIO is not used, for example, the unused port is set to the input mode, and the port is connected to the ground level. The CTC 508 has two external clock / timer trigger inputs CLK / TRG2,3 and two timer outputs ZC /
TO0,1 are built-in.

Next, the operation of the gaming machine will be described. FIG.
1 is a flowchart illustrating a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, necessary initial settings are made.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and a stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives the RST instruction (1 byte) or the CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, the processing at the time of power supply stop such as the addition of parity data) has been performed when the power is turned off (step S7). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. In this example, as shown in FIG. 12, if "55 (H)" is set in the backup flag area, it means that there is a backup (on state), and a value other than "55 (H)" is set. If there is no backup (off state).

When the backup is confirmed, the CPU 5
Reference numeral 6 performs data check (parity check in this example) of the backup RAM area. If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
8) The CPU 56 performs a game state restoring process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state at the time of power-off (step S).
9). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

In the initialization process, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
An initial value setting process for setting an initial value to a payout command storage pointer or the like is also performed. Further, a process for initializing the sub-boards (the lamp control board 35, the payout control board 37, the sound control board 70, and the symbol control board 80) is executed (step S13). The process of initializing the sub-board is, for example, a process of transmitting an initial setting command. As the initial setting command, for example, there is a payout possible state designation command (in the case of the payout possible state) or a payout stop state designation command (in the case of the payout impossible state) outputted to the payout control board 37. As the dispensable state, for example, the ball out switch 1
87 or the full tank switch 48 is on. That is, if the ball out switch 187 or the full tank switch 48 is on, the CPU 56 sends a payout stop state designation command to the payout control board 37, and otherwise sends a payout possible state designation command. Note that the withdrawable state designation command (in the case of the withdrawal possible state) or the withdrawal stop state designation command (in the case of the withdrawal impossible state)
You may comprise so that it may also be performed in the game state restoration process of step S9.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S14). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S1 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S1).
5).

In this embodiment, the built-in C
The TC is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, as shown in FIG. 13, the CPU 56 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S13).
12).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the process proceeds to a loop process in which the main process checks whether or not a timer interrupt has occurred (step S17). In the loop, a display random number update process (step S16) is also executed.

The CPU 56 determines in step S17
Upon recognizing that a timer interrupt has occurred, step S2
The game control processing of 1 to S31 is executed. In the game control process, the CPU 56 firstly receives, via the switch circuit 58, the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a, 19b, 24.
The states of the switches such as a and 24b are input and their states are determined (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S26). In the ordinary symbol process process, a corresponding process is selected and executed according to an ordinary symbol process flag for controlling the ordinary symbol display device 10 by the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Next, the CPU 56 sets a display control command relating to a special symbol in a predetermined area of the RAM 55 and performs a process of transmitting the display control command (special symbol command control process: step S27). Further, a display control command relating to a normal symbol is set in a predetermined area of the RAM 55, and a process of transmitting the display control command is performed (ordinary symbol command control process: step S28).

Further, the CPU 56 performs an information output process of outputting data such as big hit information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

The CPU 56 has switches 17, 23, 19a, and 19 for detecting winning in each winning opening.
A prize ball process for setting the number of prize balls based on the detection outputs of b, 24a and 24b is executed (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

With the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, for example, in the timer interrupt processing, only a flag indicating that an interrupt has occurred is set, and the game control processing is executed in the main processing.
The game control process may be executed by a timer interrupt process.

The main process includes a process for determining whether or not to shift to the game control process. The internal timer of the CPU 56 performs a timer interrupt process based on a timer interrupt that is periodically generated to execute the game control process. Since a flag for determining whether or not to shift is set or the like, all of the game control processing is reliably executed. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having a built-in CTC or PIO in the initial setting process. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

After the setting of CTC and PIO (step S5) is completed, an internal register for determining the frequency of the clock signal output from the IEO / SCLK0 terminal may be set. At that time, the frequency of the clock signal is set to a frequency corresponding to 2 ms, which is the start cycle of the game control process. With such settings, IEO /
From the SCLK0 terminal, a clock signal having a frequency corresponding to the activation cycle of the game control process is externally output from the CPU 56. Then, a signal corresponding to the start cycle of the game control process can be observed outside the CPU 56. Therefore, using such a signal, CP
Simulate the game control process by U56,
It becomes easy to test the operation status of the CPU 56.

FIG. 14A is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to the electric component control means of another electric component control board. In this embodiment, the control command has a 2-byte structure, and 1
The second byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit (bit 7) of the MODE data is always set to “1” and EX
The first bit (bit 7) of the T data is always "0". As described above, the control command which is a control command to the electric component control means is constituted by a plurality of data, and is in a form in which each can be distinguished by the first bit.

FIG. 14B shows an 8-bit control signal CD0 constituting a control command for each electric component control means.
FIG. 7 is a timing chart showing a relationship between .about.CD7 and an INT signal. As shown in FIG. 14B, MODE or EXT
When a predetermined period elapses after the data is output to the output port, the CPU 56 sets the INT signal (acquisition signal) indicating the data output to a high level. Also,
When a predetermined period elapses therefrom, the INT signal is set to a low level. Further, when there is data to be transmitted next, that is, after transmitting the MODE data, the data of the second byte is transmitted to the output port after a predetermined period. Thus, the capture signal is output for each of the MODE and EXT data.

In this embodiment, when a control command is to be output from the game control means to each electric component control board, the start address of the command transmission table set in the ROM 55 is set. FIG. 14 (C)
FIG. 9 is an explanatory diagram illustrating a configuration example of a command transmission table.
One command transmission table is composed of 3 bytes, and 1
INT data is set in the byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, EXT data of the second byte of the control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
For example, if the work area reference bit is 1, EXT
Indicates that the contents of the command extension data table are used as data.

FIG. 14D is an explanatory diagram showing an example of the configuration of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Bit 1 in the INT data indicates whether a display control command should be sent to the symbol display control board 80 or not. If bit 1 is "1", it indicates that a display control command should be sent. I
Bits 2 and 3 of the NT data are bits indicating whether to transmit a ramp control command and a voice control command, respectively. The command transmission table is prepared for each control command of the payout control command, the display control command, the lamp control command, and the voice control command.

FIG. 15 shows a ROM 54 according to this embodiment.
FIG. 4 is an explanatory diagram showing an address map of FIG. In the example shown in FIG. 15, the program area is allocated from the address 0000 (H). Also, address 1000 (H) to 1FFF
(H) The control data area is allocated to the address.

At the forefront of the control data area, there are a built-in device register setting table and a CTC / PIO setting table. In the built-in device register setting table, addresses of built-in device registers for determining the operation state of the built-in devices such as CTC and PIO and values for initializing the built-in devices are sequentially stored. That is, in step S4 of the main process, the CPU 56 sets the address of the built-in device register setting table in a predetermined general-purpose register (HL register or the like), and sets the data (the address of the built-in device register and the address of the built-in device register) indicated by the contents of the HL register or the like. The value for initializing the embedded device is sequentially loaded, and a value for initializing the embedded device is set in the internal device register.

As described above, when setting the internal device register, the data set in the control data area of the ROM is used. Therefore, in the program of step S4, the address of the internal device register is directly set or the internal device register is set. Do not use instructions to set data in registers. Therefore, the program is easy to see and the program maintenance becomes easy. Further, even if it is necessary to change the value for initializing the built-in device register, there is no need to change the program, and only the data in the control data area needs to be changed.

Regarding the setting of CTC and PIO in step S5 of the main processing, the address of the control register of each channel of CTC and the command register of each channel (each port) of PIO and the set value for each register are set to C.
They are sequentially stored in the TC and PIO setting tables. Therefore, in step S5, the CPU 56 sets the address of the CTC and PIO setting table in a predetermined general-purpose register (HL register and the like), and stores the data of the address indicated by the contents of the HL register and the like (the control register and PIO of each channel of the CTC). Are sequentially loaded and the set value is set in each register.

In the control data area, data for initial setting of the built-in device register (steps S4 and S4).
5), a work area and a work area setting table are stored. The work area and work area setting table is a table for setting the work area used by the CPU 56 during execution of game control, the initial value of the work area (RAM), and the set value of the work area in each state in which the game is in progress. There are stored a work area, a work area address and a value to be set. C
PU56, for example, in step S11 of the main processing,
The work area and work area setting table addresses are set in predetermined general registers (HL registers and the like), and data (work area and work area initial values) at the addresses indicated by the contents of the HL registers and the like are sequentially loaded to perform work. Set initial values for the area and work area. Step S25
In the (special symbol process processing), when a change in the game state (for example, a change from a state in which the symbol is changing to a state in which the special winning opening is opened) occurs, using the values set in the work area and the work area, Set the value of the work area.

Next, in the control data area, a command extension data address table is stored. The command extension data address table is used when the CPU 56 uses the data of the command extension data table when sending a command to the electric component control means. Next to the command extension data address table, a command transmission table is stored.

Furthermore, a big hit symbol setting table is stored in the control data area. In the big hit symbol setting table, a symbol number corresponding to a symbol in the case of a big hit is set.

Next, in the control data area, a fluctuation pattern distribution table offset value table for determining which data of the fluctuation pattern distribution table in which the data for specifying the fluctuation pattern is set is stored. I have. The variation pattern distribution table offset value table is referred to in step S25 (special symbol processing) of the main processing. The fluctuation pattern distribution table The fluctuation pattern distribution table is stored next to the offset value table.
Next, a special symbol change frequency setting table in which the initial value of the special symbol change frequency counter is set is stored.

Then, in the control data area, a special symbol judgment value table at the time of low probability is stored. In the special symbol judgment value table at the time of low probability, the state of the gaming machine is in a low probability state (a state in which a big hit is not raised).
Is set. CPU56
Determines in step S25 of the main process (special symbol process process) that when the random number for jackpot determination matches the jackpot determination value, a jackpot is determined. Further, a special symbol determination value table for a high probability is stored next to a special symbol determination value table for a low probability. In the special symbol determination value table at the time of low probability, a big hit determination value is set when the state of the gaming machine is in a low probability state (a state in which the probability of a big hit is increased).

As described above, the data for initial setting of the register of the built-in device and the data for initial setting of the work area used when the CPU 56 executes the control program are stored in the front part of the control data area. Is stored in Even if the type of gaming machine is different, if the microcomputer used is the same, the method of initializing the registers of the built-in device is generally the same, so it is commonly used between multiple models. This data is located at the front of the storage area for storing the control data.

The work area and work area setting tables are also stored in front of the control data area. That is, the data for initial setting of the work area and the work area used when the microcomputer executes the control program is likely to be commonly used by a plurality of models. Be placed.

In the control data area, a special symbol judgment value table for low probability and a special symbol judgment value table for high probability are stored in the rear part. Therefore, it is easy to change the jackpot determination value when changing the model.
If it is set at the back of the control data area, it is easy to increase or decrease the number of data, that is, the number of jackpot judgment values, and it is possible to change the judgment value itself if it is at the back. This is because the sex is considered to be small. And the special symbol judgment value table at the time of high probability,
It is set after the special symbol judgment value table at the time of low probability. Therefore, when a control program and control data are diverted to a model that does not perform control with a high probability (such as a cash machine that does not use a prepaid card), it is only necessary to delete the special symbol determination value table at the time of a high probability.

Data relating to a display result of identification information such as data for creating a control command to be output to the electric component control means and data of a fluctuation pattern distribution table are as follows.
As compared with the data related to the built-in device register, the work area, and the work area setting table, the possibility of being changed according to the model change is relatively high.

The empty area is provided at the rearmost position in the control data area. Therefore, it is possible to easily cope with an increase or decrease in the number of data in the control data area.

The data commonly used between a gaming machine (so-called CR machine) for renting out game media using a prepaid card and a gaming machine (so-called cash machine) that does not use a prepaid card for renting out game media is used for control. Preferably, it is located at the front of the data area.
It is preferable that the non-common data between them is arranged at the rear of the control data area. With such a configuration, the control data for the cash machine can be created only by deleting the data at the rear of the control data for the CR machine.

FIGS. 16 and 17 are flowcharts showing an example of the power supply stop processing executed in response to the power-off signal from the power supply board 910. The power-off signal is connected to the non-maskable interrupt terminal of the CPU 56, and the non-maskable interrupt activates the power supply stop process.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) to a predetermined backup RAM area (step S51). Further, the interrupt flag is copied to the parity flag (step S52). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register, and the stack pointer are saved in the backup RAM area (Steps S54 to S58). When the power is restored,
The register contents are restored based on the saved contents,
Internal setting of the interrupt permission state / prohibition state is performed according to the content of the parity flag.

Next, the backup specified value (in this example, “55 (H)”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, parity data is created (steps S60 to S67). That is, first, the clear data (00) is set in the checksum data area (step S60), and the checksum calculation start address is set in the pointer (step S61). Further, the number of checksum calculations is set (step S62).

The exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S63). The calculation result is stored in the checksum data area (step S6).
4) The value of the pointer is incremented by 1 (step S65), and the value of the checksum calculation count is decremented by 1 (step S6).
6). The processing of steps S63 to S66 is repeated until the value of the number of checksum calculation times becomes 0 (step S63).
67).

When the value of the number of times of checksum calculation becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). And
The inverted data is stored in the checksum buffer (step S69). This data is the parity data that is checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S
70). Thereafter, the internal RAM 55 cannot be accessed.

Further, the CPU 56 sets the clear data (0
0) is set in an appropriate register (step S71),
The number of processes ("7" in this example) is set in another register (step S72). Further, the address of the output port 0 is set in the IO pointer (step S73). Yet another register is used as the IO pointer. Note that the number of processes “7” corresponds to the number of I / O ports.

Then, the clear data is set at the address pointed to by the IO pointer (step S74).
The value of the IO pointer is incremented by 1 (step S75), and the value of the number of processes is decremented by 1 (step S77). Step S7
The processes from 4 to S76 are repeated until the value of the number of processes becomes zero. As a result, clear data is set to all output ports, and all output ports are turned off.

Therefore, after the processing for saving the game state (in this example, generation of the checksum and prevention of RAM access), each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up by power.

FIG. 18 shows a RAM according to the present embodiment.
FIG. 4 is an explanatory diagram showing an address map of an area. As shown in FIG. 18, the head of the RAM area is allocated to a backup flag area. The area of the checksum buffer is allocated to the last part.

FIG. 19 is an explanatory diagram for explaining an example of a checksum creation method. However, in the example shown in FIG. 19, the size of the data in the backup RAM area is 3 bytes for simplicity. In the process at the time of power supply stoppage based on the power supply voltage drop, as shown in FIG. 19, initial data (00 in this example) is used as checksum data.
(H)) is set. Next, “00 (H)” and “F0
(H) "is exclusive-ORed, and the result and" 16 "
(H) ". Further, an exclusive OR of the result and “DF (H)” is obtained. And
As a result, a value (“C6 (H)” in this example) obtained by logically inverting the result (“39 (H)” in this example) is set in the backup parity data area. In FIG. 19, for ease of explanation, data “3” before logical inversion is used.
9 (H) "is stored in the checksum buffer. Note that 00 as initial data
(H) is a value corresponding to the clear data with respect to the checksum data set in step S60.
Since the value of the exclusive OR with 00 (H) does not change before and after the operation, the exclusive OR operation with 00 (H) does not need to be performed. That is, the initial data shown in FIG. 19 is simply described for consistency with the flowchart shown in FIG.

In this embodiment, the checksum buffer is provided in the backup RAM area (variable data storage means).
Is stored at the last address. So, for example,
When checking whether there is any error in the program of the checksum generation method, the check can be easily performed.
This is because it is sufficient to confirm whether the value of the last address of the RAM area is correct. Also, in this embodiment, the checksum calculation start address is the address where the backup flag is set, and the checksum calculation end address is the last address in the prize ball control flag buffer (see FIG. 18). . Therefore, if the last address of the backup RAM area is set as the checksum buffer area after the prize ball control flag buffer, the RA
No waste occurs in the M area.

The first address of the backup RAM area may be a checksum buffer area in consideration of ease of confirmation and prevention of waste of the RAM area.

At the start of the power supply to the gaming machine, it is determined whether or not the parity check is OK (step S8 in FIG. 11). S6
0-S67), and if the processing result, that is, the operation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

In the above embodiment, the backup RA
Although the last or first address of the M area is used as the checksum buffer area, the checksum buffer area may be allocated to an intermediate area of the backup RAM area. FIG. 20 is an explanatory diagram showing an example of a memory map of such a RAM area. Note that the position of the checksum buffer area shown in FIG. 20 is merely an example, and if it is halfway through the backup RAM area, another location may be the position of the checksum buffer area.

FIGS. 21 to 22 are flowcharts showing the power supply stop processing when the checksum buffer area is allocated to an intermediate area of the backup RAM area. In this case, the first half of the number of checksum calculations is set in step S62A. In the example shown in FIG. 20, the first half of the number of checksum calculations corresponds to the area size from the address of the backup flag to the last address in the special symbol related flag counter buffer.

When the calculation for the first half of the number of checksum calculations is completed, the number of checksum calculations (second half) is completed.
Is set (step S82). In the example shown in FIG. 20, the checksum calculation start address (second half) is the top address of the ordinary symbol-related flag counter buffer, and the checksum calculation count (second half) is the first address in the ordinary symbol-related flag counter buffer. It corresponds to the area size from the address to the last address in the prize ball control flag buffer.

The exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S83). The calculation result is stored in the checksum data area (step S8).
4) The value of the pointer is increased by 1 (step S85), and the value of the number of checksum calculations is decremented by 1 (step S8).
6). The processing of steps S83 to S86 is repeated until the value of the number of checksum calculation times becomes 0 (step S83).
87).

When the value of the number of times of checksum calculation becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). And
The inverted data is stored in the checksum buffer (step S69). Next, an access prohibition value is set in the RAM access register (step S70). Then, the same processing as the processing shown in FIG. 17 is performed.

FIG. 23 is a flowchart showing a process of judging whether or not parity check is successful when a checksum buffer area is allocated to an intermediate area of the backup RAM area, that is, a parity check process at the start of power supply (step S8 in FIG. 11) It is a flowchart which shows.

In the parity check processing, the CPU 5
6, first, the contents of the checksum buffer are logically inverted (step S89), the initial data (00) is set in the checksum data area (step S90), and the checksum calculation start address is set in the pointer (step S91). ). Further, the number of checksum calculations is set (step S92). In the example shown in FIG. 20, the checksum calculation start address is the address of the backup flag, and the number of checksum calculations is the backup R
This is a number corresponding to the area size from the address of the AM area to the last address. That is, the checksum calculation is executed from the beginning to the end of the backup RAM area even though the checksum buffer is allocated in the middle of the backup RAM area.

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S93). The calculation result is stored in the checksum data area (step S9).
4) The value of the pointer is incremented by 1 (step S95), and the value of the number of checksum calculations is decremented by 1 (step S9).
6). The processing of steps S93 to S96 is repeated until the value of the number of checksum calculation times becomes 0 (step S93).
97).

When the value of the number of checksum calculation times becomes 0, the CPU 56 checks whether or not the calculation result is 00 (H) (step S99). If 00 (H), the parity check is OK (step S100), and the contents of the checksum buffer are cleared to 0 (step S10).
2). If it is not 00 (H), the parity check is set to NG (step S101), and the contents of the checksum buffer are cleared to 0 (step S102). Therefore, the content of the checksum buffer is cleared to 00 (H) when the parity check is performed. At the start of power supply to the gaming machine, the contents of the checksum buffer are cleared to 00 (H) in the RAM clear processing (step S11 shown in FIG. 11).

As described above, when the power supply to the gaming machine is stopped, the CPU 56 resets the initial data and the backup RA.
A checksum is created by sequentially calculating the exclusive OR of each data in the M area and stored in the backup RAM area, and when power supply to the gaming machine is started, exclusive control of each data stored in the backup RAM area is performed. The logical sum is sequentially calculated, and if the calculation result is 00 (H), the final storage content stored in the backup RAM area (the power supply stop stored when the game is interrupted due to the power supply stop) It is determined that the immediately preceding final control state is normal. Then, control is performed to restore the control state to the state before the power supply was stopped based on the contents of the backup RAM area. In this case, there is no need to compare the operation result with the contents of the checksum buffer, but simply with 00 (H), which has the advantage of simplifying the parity check processing.

FIG. 24 is an explanatory diagram for explaining a checksum creation method. However, in the example shown in FIG.
For simplicity, the data size of the backup RAM area is 3 bytes. In the processing at the time of power supply stoppage based on the power supply voltage drop, as shown in FIG. 24A, initial data (clear data as initial data of the checksum data) is set as the checksum data. Next, an exclusive OR of “00 (H)” and “F0 (H)” is obtained, and an exclusive OR of the result and “16 (H)” is obtained. Further, an exclusive OR of the result and “DF (H)” is obtained. Then, as a result (in this example, "39
(H) ”) and a value obtained by logically inverting (C in this example,“ C
6 (H) ”) is set in the backup parity data area in the backup RAM area. Note that FIG.
FIG. 4 shows that data “39 (H)” before logical inversion is stored in the checksum buffer for ease of explanation.

Then, in the parity check processing at the start of power supply, as shown in FIG. 24B, initial data is set as checksum data. Next, "0
0 (H) ”and“ F0 (H) ”are exclusive ORed,
The exclusive OR of “39 (H)” and the result is obtained, and the exclusive OR of “16 (H)” is further obtained. Next, an exclusive OR of the result and “DF (H)” is obtained. Since the operation result is 00 (H), it is determined that the parity check is OK.

Here, as shown in FIG. 21 and FIG. 22, the checksum buffer is excluded from the target of the exclusive OR operation, and the backup RAM area before the checksum buffer is sequentially subjected to the exclusive logical sum operation. The sum operation is performed, and then the exclusive OR operation is sequentially performed on the backup RAM area after the checksum buffer. However, at the start of the checksum creation processing,
If the contents of the checksum buffer in the backup RAM area are 00 (H), the exclusive OR operation is not affected. Therefore, the exclusive OR is sequentially passed from the first address to the last address of the backup RAM area. The same result can be obtained by performing the operation. In the above embodiment, the contents of the checksum buffer in the backup RAM area are set to 00 when the RAM is cleared at the start of power supply and when the parity check is performed.
(H).

Next, as an example of the case where the data saving processing and the restoring processing are performed in the electric component control means other than the game control means, the case where the data saving and the restoring are performed in the payout control means will be described.

FIG. 25 is a block diagram showing an example of a configuration around the payout control CPU 371. As shown in FIG. 25, a power supply cutoff signal from a power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to a non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via a buffer circuit 960. I have. Therefore, the payout control CPU 37
No. 1 can confirm the occurrence of power interruption by non-maskable interrupt processing.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 incorporated in the payout control CPU 371 is counted down. When the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt occurs in response to the input of the INT signal.

The payout control board 37 is also provided with a system reset circuit 975. In this embodiment,
Reset IC 97 in system reset circuit 975
Reference numeral 6 indicates that when the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. Also, reset IC 9
The monitor 76 monitors the power supply voltage of VSL, and sets the output to a low level when the voltage value falls below a predetermined value (for example, +9 V). Therefore, when the power is turned off, the signal from the reset IC 976 goes to a low level, so that the payout control CPU 371
Is reset.

Although the predetermined value for the reset IC 976 to detect the power-off is lower than the normal voltage, the payout control C
This is a voltage at which the PU 371 can operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the payout control CPU 371, the payout control CPU 371
The monitoring range can be extended for the voltage required by the 371. Therefore, more precise monitoring can be performed.

While power is not being supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal, and the The contents are saved even if the power is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state. At that time, since the necessary data has been backed up,
Upon recovery from a power failure or the like, it is possible to return to the payout control state at the time of the power failure.

FIG. 26 is a flowchart showing the main processing executed by the payout control CPU 371. In the main process, the payout control CPU 371 first makes necessary initial settings. That is, the payout control CPU 371 first sets interrupt prohibition (step S701). next,
The interrupt mode is set to the interrupt mode 2 (step S70).
2) A stack pointer designated address is set in the stack pointer (step S703). Further, the payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process in step S704 and the process in step S705, a register setting for setting a channel to be used to the timer mode, a register setting for permitting interrupt generation, and a register for setting an interrupt vector The settings are made. Then, the interruption by the channel is used as a timer interruption. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, the timer interrupt flag is set, and when it is detected in the main process that the timer interrupt flag is set, the payout control process is executed. That is, in the timer interrupt process, a setting for executing the payout control process, which is an example of the electrical component control process, is performed.

Another channel of the built-in CTC (channel 2 in this embodiment) is used as a channel for generating an interrupt for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the setting processing of the internal device register in step S704 and the processing in step S705, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the interrupt generation, and the interrupt vector setting are performed. Is set.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt processing is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as a specific register
The initial value “1” is set in LK / TRG2. Also, C
The interruption based on the count-up of the channel 3 (CH3) of the TC is based on the internal clock (system clock) of the CPU.
Is counted down and the register value becomes "0", and is used as a 2 ms timer interrupt described later. Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. Step S7
At 05, the register of CH3 contains 2 as an initial value.
A value corresponding to ms is set.

An interrupt based on the count-up of CH2 of the CTC has a higher priority than an interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process has priority.

The payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S70).
7). That is, for example, similarly to the processing of the CPU 56 of the main board 31, it is determined whether or not backup data exists by determining whether or not a backup flag that is set when the power is turned off is set. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 checks the data in the backup RAM area (parity check in this example). If the power is restored after an unexpected power failure, the backup R
Since the data in the AM area should have been saved, the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
708), the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S709). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
Performs RAM clear processing first (step S71).
1). A CTC provided in the payout control CPU 371 so that a timer interrupt is periodically performed every 2 ms.
Are set (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
The built-in CTC 71 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
The payout control CPU 371 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred.

The payout control CPU 371 determines in step S7
At 24, when it is detected that the timer interrupt flag has been set, the payout control process from step S751 is executed. According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing, and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

In the payout control processing, the payout control CPU
371 is the input port 37 via the relay board 72 first.
It is determined whether or not the prize ball count switch 301A and ball lending count switch 301B input to 2b are turned on (switch processing: step S751).

Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor for detecting the number of revolutions of the payout motor 289) to determine the state of the sensor (for example). Input determination processing: Step S752). The payout control CPU 371 further analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S75).
3).

Next, the payout control CPU 371 sets the payout stop state if the payout stop command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). ).
Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control of paying out a lent ball in response to a ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Furthermore, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the winning ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism of the ball payout device 97 via the relay board 72c and the relay board 72, and payout motor control processing for rotating the payout motor 289 by a predetermined number of revolutions is performed (step S758). .

Next, error detection processing is performed, and a predetermined display is performed on the error display LED 374 according to the result (error processing: step S759).

FIGS. 27 to 28 are flow charts showing an example of the non-maskable interrupt processing (power supply stop processing) executed in response to a power-off signal from the power supply board 910.

In the power supply stop processing, the payout control CPU 371 stores the AF register in the predetermined backup R
Save to the AM area (step S801). Further, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, the IX register, and the stack pointer are saved in the backup RAM area (Steps S804 to S804)
08).

Next, the backup specified value (for example, “55H”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, the same processing as the processing of the CPU 56 of the main board 31 is performed to create parity data, and the backup RA
The data is stored in the M area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the internal RAM cannot be accessed.

Further, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes ("3" in this example) in another register (step S822). Further, the smallest address (“00H” in this example) among the addresses of the output port is set as the IO pointer (step S8).
23). Yet another register is used as the IO pointer. The number of processes “3” is a number corresponding to the number of output ports.

Then, clear data is set at the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), the value of the number of processes is subtracted by 1 (step S827).
If the value of the number of processes is 0 in the processes of steps S824 to S826,
Repeat until. As a result, clear data is set to all output ports, and all output ports are turned off.

When the power supply to the gaming machine is started, it is determined whether or not the parity check is OK (step S708 in FIG. 26). In the determination, the parity data is created in the power supply stop processing (step S708). The same processing as in S810 to S817) is performed. If the processing result, that is, the calculation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

In the payout control means including the payout control CPU 371, if the checksum buffer is stored at the first or last address of the backup RAM area (variable data storage means), for example, the program of the checksum creation method Can be easily checked when checking whether there is any error in the information. Also, RAM
No waste occurs in the area.

The payout control means is also controlled by the CPU.
As in the case of the game control means including 56, the area of the checksum buffer may be allocated to an intermediate area of the backup RAM area. In such a configuration, in the parity check process at the start of power supply (step S708 in FIG. 26), the calculation of the checksum is
It is executed from the beginning to the end of the backup RAM area. Then, when the area of the checksum buffer is allocated to an intermediate area of the backup RAM area,
It is not necessary to compare the operation result with the contents of the checksum buffer, but simply with 00 (H), which has the advantage of simplifying the parity check processing.

As described above, in each of the above embodiments, data commonly used by a plurality of models is arranged at the front of the control data area, and is commonly used by a plurality of models. Since data that is unlikely to be used is located at the rear of the control data area, it is easy to change data that is unlikely to be used in common, and it is commonly used between multiple models. For such data, it is possible to reduce the necessity of making a change at the time of diversion.

At the start of power supply to the gaming machine, it is determined whether or not the final storage contents stored in the variable data storage means are normal based on the checksum stored in the variable data storage means. If it is configured to perform control for restoring the control state to the state before the power supply was stopped based on the final storage content if normal, the checksum is stored in the first or last variable data storage means. Since it is stored at the address, the checksum can be easily checked when checking whether there is an error in the program of the checksum generation method. Also, RA
No waste occurs in the M area.

Further, when the checksum is stored at an intermediate address of the variable data storage means,
It is not necessary to compare the operation result with the stored checksum data, but simply to compare it with 00 (H), which has the advantage of simplifying the parity check processing.

In the pachinko gaming machine 1 according to each of the above-described embodiments, when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the winning start becomes a predetermined symbol combination, the predetermined game value is reduced. Although it was a first-class pachinko gaming machine that can be given to a player, a predetermined game value that can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a start winning prize. Two types of pachinko machines,
When the stop symbol of the symbol variably displayed based on the start winning or the passage of the start gate becomes a predetermined symbol combination, the player wins a predetermined electric accessory which is opened, and goes to a special winning region among a plurality of winning regions. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a winning.

The present invention is not limited to pachinko gaming machines, but may be applied to slot machines and the like when a microcomputer or an electric component control board for controlling an electric component or the like that performs some operation is provided. can do.

[0203]

According to the first aspect of the present invention, a plurality of game machines are arranged in front of a storage area for storing control data for control data commonly used by a plurality of models. The control data that is unlikely to be used in common is configured to be located at the back of the storage area that stores the control data, so if the program is changed to another model, it must be changed This has the effect of further reducing the possibility of not being used and making it easier to divert to other models.

According to the second aspect of the present invention, the control data commonly used by a model having a function of lending game media in response to an operation of a player and a model not having a function of lending game media is: Since it is located at the front of the storage area for storing the control data, the control program and the control data of the model capable of lending the game medium can be transferred to the model not having the function of lending the game medium. In the case of diversion, it can be easily diverted by deleting the rear control data in the storage area for storing the control data.

According to the third aspect of the present invention, since the free area in the storage area for storing the control data is arranged at the rearmost position in the storage area, the number of data in the control data area is increased or decreased. Can be easily handled.

According to the fourth aspect of the present invention, since the control data for initial setting of the register of the built-in device is arranged at the front part of the storage area, the register of the built-in device which is less likely to be changed when diverted is used. By arranging the control data for the initial setting at the front, it is possible to easily use the entire control data.

According to the fifth aspect of the present invention, the control data for initial setting of the work area used when the microcomputer executes the control program is arranged at the front of the storage area. By arranging control data for initial setting of a work area having a small possibility of change at the front, it is possible to easily use the entire control data.

According to the sixth aspect of the present invention, the control data for creating the command to be output from the game control means to the electric component control means is arranged in the middle part of the storage area for storing the control data. By arranging control data for creating a command that can be changed to some extent in the case of diversion in the middle part between the front part and the rear part, the change is facilitated, and the entire control data is diverted. Can be easier.

[0209] According to the present invention, the control data for generating a command output from the game control means to the electric component control means includes at least the control data and the work area for initial setting of the register of the built-in device. Since it is located after the control data for initial setting, the control data for creating commands that may be changed to some extent when diverted is used for control that has a relatively small possibility of being changed when diverted. By arranging the control data after the data, it is possible to easily use the entire control data.

[0210] In the invention according to claim 8, since the data relating to the display result of the identification information is located in the middle part of the storage area for storing the control data, the identification information which may be changed to some extent when diverted is used. By arranging the control data relating to the display result in the intermediate part between the front part and the rear part, it is possible to facilitate the change and to easily use the entire control data.

According to the ninth aspect of the present invention, the data relating to the display result of the identification information is provided at least after the control data for initial setting of the register of the built-in device and the control data for initial setting of the work area. Since the control data relating to the display result of the identification information, which may be changed to some extent when diverted, is arranged after the control data which is relatively unlikely to be changed when diverted, the entire control data is arranged. Can be easily diverted.

[0212] According to the tenth aspect of the present invention, in a gaming machine controllable to a special game state in which the probability that the display result of the identification information becomes a specific display mode is increased, the control data relating to the transition to the special game state is provided. Is arranged at the rear of the storage area, so that when a control program and control data of a gaming machine that can be controlled to the special gaming state are used for a gaming machine that is not controlled to the special gaming state, the storage for storing the control data is stored. It can be easily diverted by deleting the data at the end of the area.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each substrate provided on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical panel of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 5 is a block diagram showing a circuit configuration in a symbol control board.

FIG. 6 is a block diagram showing a circuit configuration in a lamp control board.

FIG. 7 is a block diagram showing a circuit configuration in a sound control board.

FIG. 8 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 9 is a block diagram illustrating a configuration example of a power supply board.

FIG. 10 is a block diagram showing the internal configuration of the CPU in more detail.

FIG. 11 is a flowchart illustrating an example of a main process executed by a CPU on a main board.

FIG. 12 is an explanatory diagram showing an example of a method of determining whether or not to execute a game state restoration process.

FIG. 13 is a flowchart illustrating an example of a 2 ms timer interrupt process.

FIG. 14 is an explanatory diagram for describing control of a control command sent from the main board to the electrical component control means of another electrical component control board.

FIG. 15 is an explanatory diagram showing an address map of a ROM.

FIG. 16 is a flowchart showing a processing example of a power supply stop time process in the game control means.

FIG. 17 is a flowchart showing a processing example of a power supply stop time process in the game control means.

FIG. 18 is an explanatory diagram showing an address map of a RAM.

FIG. 19 is an explanatory diagram illustrating an example of a checksum creation method.

FIG. 20 is an explanatory diagram showing another example of the RAM address map.

FIG. 21 is a flowchart showing another example of the power supply stop processing in the game control means.

FIG. 22 is a flowchart showing another example of the processing at the time of power supply stop in the game control means.

FIG. 23 is a flowchart showing a parity check process.

FIG. 24 is an explanatory diagram for explaining another example of a checksum creation method.

FIG. 25 is a block diagram illustrating a configuration example around a payout control CPU.

FIG. 26 is a flowchart showing a main process executed by a CPU in a payout control board.

FIG. 27 is a flowchart showing processing at the time of stopping power supply in the payout control means.

FIG. 28 is a flowchart showing processing at the time of stopping power supply in the payout control means.

[Explanation of symbols]

 31 game control board (main board) 35 lamp control board 37 payout control board 56 CPU 70 sound control board 80 symbol control board 101 display control CPU 351 lamp control CPU 371 payout control CPU 701 sound control CPU 910 power supply board

Claims (10)

[Claims] 1. A gaming machine in which a player can play a predetermined game, comprising a microcomputer for controlling a game using a control program and control data whose contents do not change with the progress of the game. Among the control data, the control data commonly used by a plurality of models is arranged at the front of a storage area for storing the control data, and is likely to be commonly used by a plurality of models. A gaming machine characterized in that low control data is arranged at the rear of the storage area for storing control data. 2. The control data commonly used by a model having a function of lending game media in response to an operation of a player and a model not having a function of lending game media stores control data. The gaming machine according to claim 1, wherein the gaming machine is arranged at a front portion of the storage area. 3. The gaming machine according to claim 1, wherein the free space in the storage area for storing the control data is located at the rearmost position in the storage area. 4. The microcomputer includes a built-in device other than a CPU, and control data for initial setting of a register of the built-in device is arranged at a front portion in a storage area.
A gaming machine according to claim 3. 5. The game machine according to claim 1, wherein control data for initial setting of a work area used when the microcomputer executes the control program is arranged at a front portion of the storage area. . 6. A game control means including a microcomputer for controlling the progress of a game, and an electric component control means for controlling an electric component provided in the gaming machine in accordance with a command from the game control means, The control data for creating a command output by the game control means to the electric component control means is arranged between a front part and a rear part in a storage area for storing the control data. 5. The gaming machine according to 5. 7. The control data for creating a command to be output from the game control means to the electric component control means includes at least control data for initial setting of a register of a built-in device and control data for initial setting of a work area. The gaming machine according to claim 6, wherein the gaming machine is arranged rearward of the control data. 8. A variable display device capable of variably displaying identification information, wherein variable display of identification information is started according to a condition for starting the change, and a display result of the identification information is displayed in a predetermined specific display mode. A gaming machine controllable to a specific gaming state advantageous to a player on condition that the control data related to the display result of the identification information is different between a front part and a rear part in a storage area storing the control data. The gaming machine according to claim 1, wherein the gaming machine is disposed therebetween. 9. The control data relating to the display result of the identification information is arranged at least after the control data for initial setting of the register of the built-in device and the control data for initial setting of the work area. Item 7. The gaming machine according to Item 8. 10. A gaming machine controllable to a special game state in which the probability of a display result of identification information being a specific display mode is increased, wherein data relating to a transition to the special game state is stored in a rear part of the storage area. The gaming machine according to claim 8, wherein the gaming machine is arranged in a game machine.