JP2001218897A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of eliminating waste in a structure of a power source board, and preventing illegal control information from being inputted from an unconnected connecter in using a type-2 pachinko game machine. SOLUTION: A display control board 80 which is not used in a type-2 pachinko game machine is connected to a main board 31, so power is supplied through the main board 31 to the display control board 80. Need of providing a connector of the display control board 80 on a power source board is thus eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine represented by a pachinko game machine, a coin game machine or a slot machine. Specifically, the present invention relates to a gaming machine in which a power supply board is provided separately from another control board.

[0002]

2. Description of the Related Art An example of an electric power supply control means such as a pachinko game machine, a coin game machine or a slot machine is generally known as a game machine of this type. A power supply board for supplying power to each control board from the game board for controlling the gaming state of the gaming machine, a game medium payout control means for controlling the payout of game media,
Some include a display control board that controls a variable display device whose display state can be changed, a luminous body control unit that controls light emission of a luminous body, and a voice control unit that controls generation of a voice by a voice generation unit.

[0003]

In the above-mentioned gaming machine, electric power is separately supplied from the power supply board to each control board. Therefore, the power supply board is provided with connectors for connecting to the game board, the payout control board, the display control board, the illuminant control board, and the voice control board by wiring, respectively. Thereby,
Since it is necessary to provide a large number of connectors for the connector on the power supply board, structural restrictions are severe.

[0004] Further, when the model is changed from a first-type pachinko gaming machine having a variable display device or a third-type pachinko gaming machine to a second-type pachinko gaming machine having no variable display device, the power supply board is changed in model. Although it is not necessary to replace the power supply board with a display control board connector, if the power supply board is provided with a connector for a display control board, the power supply board and the first type or A connector for connecting to a display control board used in a third-type pachinko gaming machine is left unconnected. Therefore, when the second-type pachinko gaming machine is used, a useless connector is generated in the power supply board structure, and incorrect control information may be input from an unconnected connector.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and when a second-type pachinko game machine is used, waste in a power supply board structure is eliminated and incorrect control information is transmitted from an unconnected connector. An object of the present invention is to provide a gaming machine that can prevent input.

[0006]

According to the present invention, a plurality of electric components (CRT 82 or LCD 280, speaker 27, game effect lamps 28b, 28c, etc.) operated by supplied electric power are provided. Power supply means (power supply board 910) capable of generating power required in a gaming machine using power supplied from the outside, and each of the plurality of electric components based on power supplied from the power supply means. A plurality of electric component control means (main board 31, display control board 80, sound control board 70, lamp control board 35, prize ball control board 37, and launch control board 91) for controlling the electric component control means, Power is supplied via first electric component control means (main substrate 31) to which necessary power is directly supplied from the power supply means, and power is supplied via the first electric component control means. And a second electrical component control unit (display control board 80).

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the first electric component control means includes a game control means (main board 31) for controlling a game.
Display control means (display control board) for controlling variable display means (variable display 10) for variably displaying an image based on an electric signal output from the game control means. 80).

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, the second electric component control means supplies electric power necessary for controlling the electric component. Electric power generation means (switching regulator 10
9).

According to a fourth aspect of the present invention, in addition to the configuration according to any one of the first to third aspects, at least one of the electric component control means controls an electric component. Central processing means (CPU
56, CPU 371, display control CPU 101, etc.)
While monitoring the power supplied from the power supply means, according to the state of the supplied power, the arithmetic processing operation of the electrical component control means including the central processing means,
Or, it includes system reset means (system reset circuit 65 and the like) for outputting an electric signal that can be stopped.

According to a fifth aspect of the present invention, in addition to the configuration according to any one of the first to fourth aspects, the power supply means is provided by establishing a predetermined condition according to the progress of the game. Necessary electric power is directly supplied to value giving control means (payout control board 37) for performing control for giving a game value.

According to a sixth aspect of the present invention, in addition to the configuration of the fourth or fifth aspect, the power supply means supplies power to the plurality of electric component control means. By starting, the central processing means (CPU
After the electric component control means (payout control board 37, display control means 80) including the display control CPU 101) becomes operable, the game control means can control other electric component control means.

According to a seventh aspect of the present invention, in addition to the configuration of the game machine according to the sixth aspect, the present invention is also provided for executing the arithmetic processing operation of the central processing means constituting the game control means. Delay means (capacitors 652, 97) for delaying the electrical signal output by the system reset means for a predetermined time;
7).

According to an eighth aspect of the present invention, in addition to the configuration according to any one of the first to seventh aspects, the power supply means includes a predetermined potential power supply (power supply of voltage VSL). Under the predetermined condition (monitoring voltage + 22V or less and + 9V
Power supply monitoring means (power supply monitoring IC 90) capable of outputting a predetermined signal (power-off detection signal or power-down signal, and NMI interrupt signal) when the following holds.
2), and at least one of the plurality of electric component control means performs a power supply stop processing (a power failure occurrence NMI processing) according to the input of the predetermined signal.

According to a ninth aspect of the present invention, in addition to the configuration according to any one of the first to eighth aspects, the power supply means includes a plurality of the plurality of electric power supplies when no electric power is supplied. Other power supply means (capacitor 916 serving as a backup power supply) for supplying at least one of the component control means with power necessary to store information related to control of the electric component is included. .

According to a tenth aspect of the present invention, in addition to the configuration of the eighth or ninth aspect, when the predetermined condition is satisfied, the power supply from a predetermined potential power supply Voltage is a predetermined value (monitoring voltage + 22V or less and +
9V or less).

[0016]

According to the first aspect of the present invention, the following operations are provided. The plurality of electric components operate with the supplied power. By the function of the power supply means, power required for the gaming machine is created using power supplied from the outside. By the operation of the plurality of electric component control means, each of the plurality of electric components is controlled based on the power supplied from the power supply means.

The first electric component control means is directly supplied with electric power from the electric power supply means. Electric power is supplied to the second electric component control means via the first electric component control means.

According to the second aspect of the present invention, in addition to the operation of the first aspect, the game is controlled by the operation of the game control means as the first electric component control means. . By the function of the display control means as the second electric component control means, the variable display means for variably displaying an image based on the electric signal output from the game control means is controlled.

According to the third aspect of the present invention, in addition to the operation of the first or second aspect of the present invention, the electric component is controlled by the power generating means of the second electric component control means. The power required to control is created.

According to the fourth aspect of the present invention, in addition to the functions of the first to third aspects,
By the operation of the central processing means, calculations necessary for controlling the electric components are performed. By the operation of the system reset means, the power supplied from the power supply means is monitored, and the arithmetic processing operation of the central processing means is executed or stopped according to the state of the supplied power. A possible electrical signal is output.

According to the fifth aspect of the present invention, in addition to the functions of the first to fourth aspects,
By the function of the power supply means, necessary power is directly supplied to the value provision control means for performing control for providing a game value by satisfying predetermined conditions according to the progress of the game.

According to the sixth aspect of the present invention, in addition to the function of the fourth or fifth aspect of the invention, the power supply means is provided with a plurality of electric component control means by the operation of the game control means. By starting to supply power to
After the electric component control means including the central processing unit among the electric component control means excluding the game control means becomes operable, control of other electric component control means is performed.

According to a seventh aspect of the present invention, in addition to the operation of the sixth aspect of the present invention, the operation of the central processing unit constituting the game control unit is executed by the function of the delay unit. Therefore, the electric signal output from the system reset means is delayed for a predetermined time.

According to the present invention described in claim 8, in addition to the effects of the invention described in any one of claims 1 to 7,
A predetermined potential power supply is monitored by the function of the power supply monitoring means of the power supply means, and a predetermined signal is output when a predetermined condition is satisfied. Thereby, at least one of the plurality of electric component control means performs the power supply stop processing in response to the input of the predetermined signal.

According to the ninth aspect of the present invention, in addition to the function of the first aspect of the present invention,
In order to store information relating to control of an electric component in at least one of the plurality of electric component control units when power is not supplied by the operation of another power supply unit of the power supply unit. Necessary power is supplied to the vehicle.

According to the tenth aspect of the present invention, in addition to the function of the eighth or ninth aspect, the voltage of the power supplied from the predetermined potential power supply becomes a predetermined value. In this case, since the process at the time of power supply is performed, a voltage drop is monitored.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following embodiments, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to this, and may be, for example, a coin gaming machine or a slot machine. It is possible to apply to all game machines.

FIG. 1 is a front view of a pachinko gaming machine 1 in one example of a gaming machine according to the present invention. Referring to FIG.
The pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape.
Having. A game board 6 is detachably mounted behind the glass door frame 2. Further, on the lower surface of the glass door frame 2, there is a hit ball supply tray 3. A surplus ball receiving tray 4 for storing balls overflowing from the hitting ball supply tray 3 is provided below the hitting ball supply tray 3.
And an operation knob 5 for a player to perform a hitting operation. By operating the operation knob 5 by the player,
The pachinko balls stored in the hit ball supply tray 3 can be fired one by one. In the center of the game area 7, a variable display device 8 for variably displaying a special symbol as an example of identification information is provided. The variable display device 8 includes a variable indicator 10 for a normal symbol, in which a normal symbol is variably displayed as a hit ball passes through a passing gate 11, and four LEDs (Ligh
and a start memory display 18 comprising a light emitting diode. Further, below the variable display device 8, a starting electric accessory 15 having a starting port 14 and an opening / closing plate 20 are provided.
The variable winning prize ball device 19 which is in an open state in which a hitting ball can be won by tilting of the ball is provided. The starting electric accessory 15 has left and right blade members 150. Further, as a general winning opening, a winning opening 24 is provided on the upper portion of the variable display device 8 and on the left and right of the variable winning ball device 19, respectively. Reference numeral 26 denotes an out port which is collected as an out ball when the hit ball does not win any of the winning ports or the variable winning ball devices. Reference numeral 25 denotes a decorative lamp.

On the outer periphery of the game area 7, a game effect LED 28a as a frame lamp and game effect lamps 28b, 28
c, a prize ball lamp 51 that lights up when the prize ball is paid out, a lamp burnout lamp 52 that lights up when the ball runs out, and an unpaid prize ball lamp 29 that lights up when the prize ball is not paid out. Speakers 27 for generating sound effects such as stereo sound are provided on the left and right of the upper part of the game area 7.

The variable display device 8 is configured such that a plurality of types of special symbols, characters for enhancing the effect of playing a game, predetermined messages, and the like can be displayed on the central variable display section 9 as images. For example, as shown in the figure, the variable display section 9 switches its display state to three variable display areas 100a, which can variably display a special symbol in the middle left and right.
100b and 100c can be displayed as images. In each of the variable display areas 100a, 100b, and 100c, a plurality of types of special symbols are scroll-displayed from top to bottom on condition that a winning winning has occurred. After that, after a predetermined time has elapsed, the scrolling of the symbol is stopped and the variable display is ended. As a result, if a big hit symbol (for example, 777) of the big hit symbol is displayed, the big hit occurs. When a big hit occurs, the open / close plate 20 of the variable winning ball device 19 is tilted to open a big winning opening. As a result, the first state is controlled to be advantageous for the player who can make the ball hit the large winning opening, and the game state becomes the specific game state (big hit state) advantageous to the player.

A count switch 23 for detecting a ball which has won the variable winning ball device 19 is provided inside the big winning opening of the variable winning ball device 19. The inside of the special winning opening is divided into a specific winning area and a normal winning area, and a V count switch 22 for detecting a V winning is provided in the specific winning area. The winning ball that has won the specific winning area is detected by the V count switch 22 and then detected by the count switch 23. On the other hand, a normal winning ball that has won the normal winning area is detected only by the count switch 23 in the large winning opening. Every time a winning ball that has won the variable winning ball device 19 is detected by the count switch 23, 15 winning balls are paid out.

The first state of the variable winning ball device 19 is when the number of hit balls that have entered the special winning opening reaches a predetermined number (for example, nine) or when a predetermined period (for example, 30 seconds) has elapsed. When the earlier one of the conditions is satisfied, the process ends once and the opening / closing plate 20 is closed. As a result, the variable winning ball device 19 is controlled to the second state which is disadvantageous for a player who cannot make a hit ball. And
On condition that the ball hit during the period when the variable prize ball device 19 is in the first state makes a specific prize in the specific prize area and is detected by the V count switch 22, the variable prize ball device 19 is again set. Is set to the first state. The upper limit number of executions of the repetition continuation control is set to, for example, 16 times. In the repetition continuation control, a state in which the variable winning ball device 19 is in the first state is called a round. When the upper limit number of times of the execution of the repetition continuation control is 16, the variable prize ball device 19 is used for the first round to the 16th round for 16 rounds.
State. The number detected by the count switch 23 and the number of rounds are displayed by a number display 80a composed of a 7-segment display.

Below the variable display device 8, a starting electric accessory 15 is provided. A starting port 14 provided with a blade member 150 is formed at the center of the starting electric accessory 15, and a passage gate 11 is formed on both sides thereof. A gate switch 12 (see FIG. 6) is provided on one of the two left and right passage gates 11, and the ordinary symbol display 10 is variable on the condition that a hit ball is detected by the gate switch 12. Be started. In addition, when a ball is further detected by the gate switch 12 during the variable display of the normal symbol display 10, "4" is displayed.
Is stored as the upper limit of the number of stored balls, and the number of stored balls is LE in the start memory display (not shown) for a normal symbol.
It is indicated by the number of lightings of D.

The normal symbol display 10 is a 7-segment LE.
D. When the display result of the ordinary symbol display 10 is 7, it is "hit", and when it is other than that, it is "losing". When the display result of “hit” is derived on the ordinary symbol display 10, the pair of left and right blade members 150 provided on the starting electric accessory 15 is opened once. As a result, the starting electric accessory 15 is in an open state, and the hit ball is more easily won. If one of the hit balls wins while the starting electric accessory 15 is in the open state, the blade member 150 closes to the original position, and the hit ball returns to a state where it is difficult to win.
Further, if a predetermined opening period has elapsed after the starting electric accessory 15 has been opened, the blade member 150 closes to the original position and the open state ends even if the start winning does not occur. In the probability fluctuation state described later, the starting electric accessory 15 is opened twice and one opening period is extended.

The start winning ball that has won the starting opening 14 is detected by a starting opening switch 17 (see FIG. 4) provided on the game board 6. When the starting winning ball is detected by the starting port switch 17, a predetermined number of winning balls are paid out, and the variable display device 8 is variably started based on the detected output. The starting prize detected by the starting port switch 17 during the variable display of the variable display device 8 is stored with “4” as the upper limit of the number of storages, and the stored number is displayed on the start storage display 18 by the number of lighted LEDs. You.

When the result of the big hit displayed on the variable display device 8 is constituted by a specific probable change symbol (for example, "7" of a numeric symbol), after the end of the specific game state based on the big hit, The probability of occurrence of a big hit is higher than in the normal state (normal game state), and the probability is changed. Hereinafter, a jackpot based on a probability variable symbol is referred to as a probability variable jackpot. Once a probability change big hit occurs during the normal game state,
At least a predetermined number of continuations of the probability change (for example, 1
(Or twice) until the big hit occurs, the state is continuously controlled to the probability fluctuation state. Further, if a probability change jackpot occurs during the probability change state, the probability change count is counted again after the probability change hit, and thereafter, the probability change state is continued at least until the probability change occurrence count hits. And
If the jackpot that has reached the number of times of probable variation has been caused by a non-probability variable symbol other than the probable variation symbol, the game returns to the normal game state in which probability variation does not occur.

Therefore, when there is no limit on the continuous control of the probability variation state, the probability variation state is continued without any restriction as long as at least the jackpot that has reached the number of times of continuation of the probability change is the probability jackpot. In the case of the pachinko gaming machine 1, if the probability fluctuation state continues to some extent, the number of times the probability variable jackpot is continuously generated during the probability fluctuation state is determined in order to temporarily end the continuous control to the probability fluctuation state. An upper limit has been set. When the display mode of the big hit is determined to be the non-probable variable big hit based on the upper limit number, the continuous control of the probability variation state is forcibly terminated at that time. In addition,
The restriction to prohibit the jackpot in the probable symbol is called the operation of the limiter.

In the probability fluctuating state, the hit probability of the ordinary symbol increases, and the variable display period (variation time) from the start of the variable display of the ordinary symbol until the display result is derived and displayed is reduced. . Further, in the probability fluctuation state, the starting electric accessory 15 is usually caused by hitting the symbol.
The number of times of opening is increased from once to twice, and one opening period is extended from 0.2 seconds to 1.4 seconds.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

The mechanism board 36 includes a variable display control unit 129 for controlling the variable display section 9 via the relay board 30 and a game control board (main board) covered with the board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 129 and the game control board 31, and a power supply board 910 (FIG. 9).
Power supply unit box 319 for accommodating a prize ball, and a prize ball control board 37 mounted with a prize ball control microcomputer for controlling payout of prize balls. Furthermore, a ball launching device 34 that launches a ball into the game area 7 using the rotational force of a motor is provided below the mechanism plate 36.
And a lamp control board 35 are provided.

FIG. 3 is a rear view of the mechanical plate 36 of the pachinko gaming machine 1 as viewed from the rear. A power supply unit box 319 is provided at the upper right of the mechanism plate 36. Power supply board 910 housed in power supply unit box 319
(See FIG. 9) generates a plurality of power supplies having different voltages.

As shown in FIG. 3, the ball that has passed through the guiding gutter 39 has a broken-out detection switch 187 (187a, 187).
b) and the ball supply gutter 186 (186a, 186b)
And reaches the ball dispensing device 97. Note that the guide gutter 39 is provided with a cutout detection switch 167 that detects a cutout on the upstream side of the cutout switch 187.

The balls dispensed from the ball dispensing device 97 are supplied to the hitting operation supply plate 3 provided on the front of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. When a large number of balls based on the prize are paid out and the hitting ball supply tray 3 becomes full, and finally the ball is further paid out after reaching the communication port 45, the ball is transferred to the surplus ball tray 4 via the surplus ball passage 46. Be guided. When the ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the payout motor in the ball payout device 97 stops, the operation of the ball payout device 97 stops, and the driving of the hit ball firing device 34 also stops as necessary. To control the payout of the prize balls, the starting port switch 17, V
Signals from the count switch 22 and the count switch 23 and a prize ball detection switch for detecting prize balls that have won various prize holes at a collective gutter on the back side of the game board are sent to the game control board 31. When the ON signals of these switches are sent to the game control board 31, the game control board 31 sends a prize ball number command to the prize ball control board 37 to specify the number of prize balls determined for each winning opening. Sent.

FIG. 4 is a block diagram for explaining a control circuit of the pachinko gaming machine 1. 4, a game control board (main board) 31, a lamp control board 35, a prize ball control board 37, an audio control board 70, a display control board 80, and a launch control board 91 are provided as control boards. It is shown.

Game control board 31, prize ball control board 37, lamp control board 35, voice control board 70, launch control board 9
A microcomputer and the like are mounted on the display control board 1 and the display control board 80. Each control board 31, 37, 35, 7
At 0 and 80, when the power of the pachinko gaming machine 1 is turned on, initialization processing such as initializing data in a RAM provided on the control board is performed, and the prize ball control board 37, the lamp control board 35, and the sound are initialized. The control board 70 and the display control board 80 can effectively receive a command from the game control board 31 when the initialization processing ends.

The game control board 31 is a board on which a game control microcomputer (hereinafter abbreviated as a game control microcomputer) 53 for controlling the game of the pachinko gaming machine 1 is mounted, and other control boards 35, 37, Reference numerals 70 and 80 denote control commands (lamp control commands, prize ball control commands, voice control commands,
Control operation based on the display control command). Among these control commands, there is a common command common to the lamp control command, the voice control command, and the display control command.
It is output from the game control board 31 to each of the control boards 35, 70, 80 at the same time.

When a control command is output from the game control board 31, an INT signal (strobe signal) indicating a valid period of the command is output accordingly. IN
T signal is high level (OFF state) in invalid state
In the valid state, the signal becomes low level (on state).

The game control board 31 includes, in addition to the game control microcomputer 53, a switch circuit 58 for providing signals from the respective switches to the game control microcomputer 53, a solenoid 16,
A solenoid circuit 59 for driving the microcomputer 21 according to a command from the game control microcomputer 53; and an initial reset circuit 63 for resetting the game control microcomputer 53 when the power is turned on.
An address decode circuit 67 for decoding an address signal given from the game control microcomputer 53 and outputting a signal for selecting one of the I / O port units (not shown) 1 / O port; Game control microcomputer 5
Jackpot information indicating the occurrence of a jackpot according to the data given from 3, starting information indicating the number of times the variable display device 8 has been started,
It includes an information output circuit 64 that outputs probability change information indicating that a probability change has occurred to a host computer such as a hall management computer. In addition, the game control board 3
1 is provided with a power supply monitoring means for monitoring a power supply voltage, as will be described later with reference to FIG.

The game control microcomputer 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, and a CPU 56 for performing a control operation in accordance with the game control program. Among them, the RAM 55 is backed up by a backup power supply from the power supply board 910, and the RAM data is retained for a predetermined time even if a power failure occurs unexpectedly.

The switch circuit 58 includes a gate switch 1
2. The starting port switch 17, the count switch 23, the V count switch 22, the winning ball detection switch 99 and the like are connected, and detection signals from these switches are input to the game control microcomputer 53 via the switch circuit 58. Is done.

A ball payout device 97 and a card unit 50 are connected to the prize ball control board 37. Award ball control board 37
Controls the ball payout device 97 based on the prize ball control command output from the game control board 31 to pay out prize balls. Further, the prize ball control board 37 includes a card unit 50.
Control for paying out ball lending based on the control signal output from the controller.

The speaker 27 is connected to the audio control board 72. The voice control board 70 controls the speaker 27 to output various sound effects based on the voice control command output from the game control board 31.

The lamp control board 35 includes a game effect LED
28a, gaming effect lamps 28b and 28c, award ball lamp 5
1, ball cut lamp 52, variable display 10 for ordinary symbols,
Start memory indicator 18 for special symbols, start memory indicator for ordinary symbols, decorative lamp 25, lamp 29 with unpaid prize balls
Are connected. However,
FIG. 4 omits illustration of these connection states. The lamp control board 35 controls these lamps / LEDs based on a lamp control command output from the game control board 31.

The display control board 80 is connected to the variable display device 8 for special symbols (not shown). Display control board 8
0 causes the variable display unit 9 of the variable display device 8 to display a predetermined image in accordance with the display control command output from the game control board 31.

A drive motor 94 and an operation knob (ball hitting operation handle) 5 are connected to the launch control board 91. The launch control board 91 is designed so that a hit ball is fired from a hit ball firing device (not shown) at a speed corresponding to the operation amount of the operation knob 5.
The drive of the drive motor 94 is controlled.

FIG. 5 shows a CRT 82 for displaying an image of the circuit configuration in the display control board 80 on the variable display device 8 and output ports (ports A and B) 5 of the game control board 31.
It is a block diagram shown with 71,572 and the output buffer circuit 63. The output port 571 outputs 8 bits × 2 data as a display control command, and the output port 572 outputs a 1-bit INT signal (strobe signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and when the INT signal is input from the game control board 31 via the noise filter 107 and the input buffer circuit 105,
The display control command is received via the input buffer circuit 105. As the input buffer circuit 105, for example, a 74HC244, which is a general-purpose IC, can be used.
When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuit 105 and the display control CPU 101.

The display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP 103 reads necessary data from character ROM 86. VDP
103 generates image data to be displayed on the CRT 82 in accordance with the input data, and
It is stored in M87. Then, the image data in the VRAM 87 is converted into R, G, B signals,
Is further converted to an analog signal through
Output to T82.

FIG. 5 shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and frequently used image data (person, animal, character, figure or symbol). Character ROM8 for storing images composed of
6 is also shown.

Further, in the configuration shown in FIG. 5, in the display control board 80, the output of the reset switch 110 is introduced to the input port. Display control CPU 101
Detects that the reset switch 110 has been pressed after an error has occurred, returns the control to the state before the error occurred.

As an error, for example, the game control board 3
There is a case where the display control command received from No. 1 is abnormal (such as an undefined command). Display control CPU1
01 is configured to receive and store the display control command even after an error occurs, the reset switch 11
By performing display control based on the stored received command based on the pressing of 0, it is possible to reduce the influence of the occurrence of the error on the game effect.

The input buffer circuit 105 can pass signals only in the direction from the game control board 31 to the display control board 80. Therefore, the display control board 80
There is no room for a signal to be transmitted from the side to the game control board 31 side.
Even if the circuit in the display control board 80 is tampered with,
The signal output by the unauthorized modification is not transmitted to the game control board 31 side. The output ports 571, 572
May be output to the display control board 80 as it is, but the output buffer circuit 63 capable of transmitting signals only in one direction.
Is provided, the game control board 31 can more reliably transmit a one-way signal to the display control board 80. Also, a noise filter 1 for blocking high-frequency signals
As 07, for example, a three-terminal capacitor or a ferrite bead is used. However, even if the display control command includes noise between the substrates due to the presence of the noise filter 107, the effect is eliminated.

As shown, the display control CPU 101 as the display control means (variable display control means) is mounted on a separate board from the game control board 31 on which the CPU 56 as the game control means is mounted. I have. Thereby, the game control board 31 is downsized.

FIG. 6 is a block diagram showing an example of the configuration of the voice control command signal transmission portion of the game control board 31 and the voice control board 70. The audio control board 70 is provided with a control CPU 701, a ROM 711, a RAM 712, and the like. As shown, the control CPU 701 as the sound control means is mounted on a board different from the game control board 31 on which the CPU 56 as the game control means is mounted. Thereby, the game control board 31 is downsized.

In this embodiment, according to the progress of the game,
The voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 is transmitted to the game control board 31.
Is output to the voice control board 70. As shown in FIG. 6, the voice control command is output from output ports (output ports C and D) 573 and 574 of the game control microcomputer 53. The output port 573 outputs 8 bits × 2 data as control command data, and the output port 574 outputs a 1-bit INT signal (strobe signal). In the sound control board 70, each signal from the game control board 31 is input to the sound control CPU 701 via the input buffer circuit 705. When the audio control CPU 701 does not include an I / O port, the input buffer circuit 705 and the audio control CPU
701 is provided with an I / O port.

For example, a speech synthesis circuit 702 using a digital signal processor includes transistors 501 to 50
6 generates a sound or a sound effect according to the instruction of the sound control CPU 701 received through the control unit 6 and outputs the sound or sound effect to the volume switching circuit 703. The output level of the sound volume switching circuit 703 and the sound control CPU 701 is set to a level corresponding to the set sound volume and output to the sound volume amplification circuit 704. Volume amplification circuit 704
Outputs the amplified audio signal to the speaker 27.

As input buffer circuit 705, for example, 74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore,
The output level of each buffer is determined to be the input level, that is, the signal level from the game control board 31. Therefore,
There is no room for a signal to be transmitted from the voice control board 70 to the game control board 31. Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is not transmitted to the game control board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 705.

On the game control board 31 side, a buffer circuit 67 is provided outside the output ports 574, 575. As the buffer circuit 67, for example, a 74HC244 which is a general-purpose CMOS-IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the game control board 31 is blocked, a signal line to which a signal may be given from the voice control board 70 to the game control board 31 is further ensured. Can be eliminated.

Further, in the configuration shown in FIG. 6, in the voice control board 70, the output of the reset switch 710 is introduced to the input port. Voice control CPU 701
Detects that the reset switch 710 has been pressed after an error has occurred, returns the control to the state before the error occurred.

As an error, for example, the game control board 31
There is a case where the voice control command received from the server is abnormal (such as an undefined command). Voice control CPU 70
1 is configured to receive and store the voice control command even after an error occurs, the reset switch 710
By performing the voice control based on the stored received command based on the pressing of, the influence of the occurrence of the error on the game effect can be reduced.

The ROM (not shown) of the voice control board 70 has a control for generating a voice corresponding to various voice control command data in a voice synthesis circuit (voice synthesis LSI: digital signal processor) 702. Data is stored. The voice control CPU 701 reads control data corresponding to the received various voice control command data from the ROM.

In this embodiment, the speech synthesis circuit 702
Are controlled by a transfer request signal (SIRQ), a serial clock signal (SICK), a serial data signal (SI), and a transfer end signal (SRDY). When the SIRQ goes low, the speech synthesis circuit 702
Synchronize with ICK, fetch SI one bit at a time, SRDY
Becomes low level, the data consisting of each SI received so far is interpreted as one audio reproduction data. In addition,
When receiving the control data through the SI, the voice synthesis circuit 702 generates a voice corresponding to the received control data.

FIG. 7 is a block diagram showing a signal transmitting / receiving portion of the game control board 31 and the ramp control board 35. In this embodiment, the game effect LED 28a, the game effect lamps 28b and 28c, the prize ball lamp 51, the ball cutout lamp 52, the variable display 10, the start memory display 18, the decoration lamp 25, the unpaid prize ball presence lamp 29, and the like. The game control board 31 outputs a lamp control command instructing turning on / off of the game.

The lamp control board 35 includes a control CPU 3
51, a ROM 352, a RAM 353, a circuit 600 including a transistor, and the like. As shown,
The control CPU 351 as the ramp control means is a game control board 3 on which the CPU 56 as the game control means is mounted.
1 is mounted on another substrate. Thereby, the game control board 31 is downsized.

The ramp control command is output from output ports (output ports E and F) 575 and 576 of the I / O port unit 57 in the game control microcomputer 53. The output port 575 has 8 bits × 2 as control command data.
Bit data is output, and output port 576 outputs a 1-bit INT signal (strobe signal). In the lamp control board 35, a lamp control command output from the game control board 31 is input to the lamp control CPU 351 via the input buffer circuit 355. When the lamp control CPU 351 does not include an I / O port, the input buffer circuit 355 and the lamp control CP
An I / O port is provided between U351.

The lamp control CPU 351 outputs a light-on / light-off signal to each lamp / LED according to a lamp light-on / light-off pattern defined according to each lamp control command. In addition, the lighting / light-out pattern is ROM
352.

As input buffer circuit 355, for example, 74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore,
The output level of each buffer is determined to be the input level, that is, the signal level from the game control board 31. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 to the game control board 31. Even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the game control board 31 side. For example, even if the lamp control board 35 is modified so as to give the game control microcomputer 53 of the game control board 31 an illegal signal for causing a big hit, the illegal signal is not transmitted to the game control board 31 side. Can not. Note that a noise filter may be provided on the input side of the input buffer circuit 355.

Further, on the game control board 31, a buffer circuit 62 is provided outside the output ports 575, 576. As the buffer circuit 62, for example, a 74HC244, which is a general-purpose CMOS-IC, is used.
The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the game control board 31 is blocked, a signal line to which a signal may be given from the ramp control board 35 to the game control board 31 is more reliably provided. Can be eliminated.

Further, in the configuration shown in FIG. 7, in the lamp control board 35, the output of the reset switch 360 is introduced to the input port. Lamp control CPU3
When detecting that the reset switch 360 is pressed after the occurrence of the error, the control unit 51 returns the control to a state before the occurrence of the error.

As an error, for example, the game control board 31
There is a case where the lamp control command received from the server is abnormal (such as an undefined command). Lamp control CPU 35
1 is configured to receive and store the lamp control command even after an error occurs, the reset switch 36
By performing display control based on the stored received command based on the pressing of 0, it is possible to reduce the influence of the occurrence of the error on the game effect.

The lamp control CPU shown in FIG.
The circuit 600 between the built-in output port 351 and each lamp / LED includes circuits 511 to 511 each including a transistor described later.
517, 520, 530, 541, 542, 550, 5
56.

FIG. 8 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. The prize ball control board 37 includes a control CP
U371, ROM 380, RAM 381, I / O
A port 372 (372a to 372g), an input buffer circuit 373, an error display LED 374, and a reset switch (reset SW) 379 are provided.
As described above, the control CPU 371 as the prize ball control means (value giving control means or payout control means) is the game control board 3 on which the CPU 56 as the game control means is mounted.
1 is mounted on another substrate. Thereby, the game control board 31 is downsized.

As shown in FIG. 8, the detection signals of the winning ball detection switch 99 and the full tank switch 48 which collectively detect the winning balls which have won various winning ports at the collecting gutter on the back side of the game board are transmitted to the relay board. It is input to the I / O port 57 of the game control board 31 via 71. Also, winning ball discharge solenoid 1
Reference numeral 27 denotes a driving mechanism for driving a ball stop member provided on the back of the game board in the path of the winning ball flow, and the winning ball is detected by the winning ball detection switch 99 in a state where the winning ball is stopped on the ball stopping member. Is detected. The full tank switch 48
Is a switch for detecting whether the surplus ball tray 4 is full.

The detection signals from the broken-out detection switch 167 and the broken-out switch 187 (187a, 187b) are input to the I / O port 57 of the game control board 31 via the relay board 72 and the relay board 71. The cut-out detection switch 167 is a switch for detecting a shortage of supply balls in the prize ball tank 38, and the cut-out switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the game control board 31 indicates that the detection signal from the burn-out detection switch 167 or 187 indicates a burn-out state, or the detection signal from the full-state switch 48 indicates a full state. If so, a prize ball control command instructing prohibition of ball lending is transmitted to the prize ball control board 37. The prize ball control CPU 371 of the prize ball control board 37, upon receiving a prize ball control command instructing prohibition of ball lending, stops the ball lending process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the game control board 31 via the relay board 72 and the relay board 71. The drive signal from the I / O port 57 of the game control board 31 to the winning ball discharge solenoid 127 is transmitted to the relay board 7
1 is supplied to the winning ball discharge solenoid 127.
The prize ball count switch 301A is connected to the ball payout device 9
7 is provided in the prize ball mechanism portion and detects the prize balls actually paid out.

When there is a prize, the prize ball control board 37 has output ports (ports G and H) 577,
From 578, a prize ball control command (prize ball number command) indicating the number of prize balls is output. Output port 577 outputs 8-bit × 2 control command data, and output port 578.
Outputs a 1-bit INT signal (strobe signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. Each buffer in the input buffer circuit 373 can pass a signal only in a direction from the game control board 31 to the prize ball control board 37. Therefore, there is no room for a signal to be transmitted from the award ball control board 37 side to the game control board 31 side. Even if the circuit in the prize ball control board 37 is tampered with, the signal output by the tampering is not transmitted to the game control board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 373.

On the game control board 31 side, a buffer circuit 68 is provided outside the output ports 577 and 578 for outputting the prize ball control command. According to such a configuration, since a signal input from the outside to the inside of the game control board 31 is blocked, a signal line to which a signal is likely to be given from the prize ball control board 37 to the game control board 31 is increased. It can be reliably eliminated.

The CPU for controlling award ball 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer (not shown) is mounted on the buzzer substrate 75. Further, the output port 372
An error signal is output to the error display LED 374 via e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to 72b via the relay board 72. The ball lending count switch 301B detects a game ball actually lent.
The drive signal from the prize ball control board 37 to the payout motor 289 is output from the payout motor 289 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.
Conveyed to. A signal for driving the distribution solenoid 310 is transmitted to the distribution solenoid 310 via the output port 372d and the relay board 72.

In the configuration shown in FIG. 8, the output of the reset switch 379 is introduced to the input port 372b. Upon detecting that the reset switch 379 has been pressed after an error has occurred, the prize ball control CPU 371 detects
Returns control to the state before the error.

If the award ball control CPU 371 is configured to receive and store the award ball control command even after an error has occurred, the award ball control command
By performing the prize ball control based on the stored received command, the disadvantage given to the player can be eliminated.

The card unit 50 is equipped with a microcomputer (not shown) for controlling the card unit. The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

[0094] From the balance display board 74 to the card unit 50
In response to the operation, a ball lending switch signal and a return switch signal are provided to the player via the prize ball control board 37.

The CPU 371 of the prize ball control board 37 counts the number of paid prize balls by counting the detection signal of the prize ball count switch 301A, and also counts the detection signal of the ball lending count switch 301B, Count the number of balls paid out.

The CPU 371 further includes a prize ball count switch 301A and a ball lending count switch 301B.
In parallel with the operation of counting the balls based on the detection signal of the above, using the detection signal from the payout motor position sensor 286,
The number of paid prize balls and the number of lending balls are counted. That is, in the ball dispensing device 97, the screw 288 for feeding out the ball is 1
Since one ball is dispensed each time the dispensing motor position sensor 286 is turned ON / OFF once by rotating by 80 degrees, based on a change in the output signal of the dispensing motor position sensor 286. The paid-out balls are indirectly detected, and the number of balls is counted.

It should be noted that instead of the dispensing motor position sensor 286, the number of dispensing operation (rotation) of the screw 288 is detected by detecting the number of step pulses of the dispensing motor 289, which is a stepping motor, and thereby indirectly. The payout of the ball may be detected. However, the payout motor position sensor 2 which directly detects the rotation of the screw 288
Using 86 has the advantage that a highly accurate detection result can be obtained. When detecting the payout operation amount (rotation amount) of the screw 288 based on the number of step pulses of the stepping motor, an error occurs in the detected operation amount if the control amount per step changes for some reason. It is.

When the number of balls is counted based on the output signal of the payout motor position sensor 286, the screw 28
Although the counting operation can be performed more quickly than counting the balls based on the output signals of the count switches 301A and 301B in which a detection signal is output after waiting for the ball to drop from the ball 8, the balls are aligned in the screw 288. There is a disadvantage that one ball is regarded as having been dispensed even if an unnecessary gap is left between the balls and the ball is not dispensed when the screw 288 has rotated half a turn. Alternatively, even if the ball was not actually paid out due to a ball bite or other causes, it is considered that one ball was paid out.

For this reason, after the number of balls counted based on the output signal of the payout motor position sensor 286 reaches the expected payout number, the CPU 371 temporarily stops the rotation of the screw 288 and temporarily stops the count switches 301A and 301B. By referring to the counting result based on the detection signal, it is surely checked whether or not the payout of the ball as scheduled is performed. If the number of payouts is insufficient, the screw 288 is rotated again to remove the insufficient ball. Perform payout control.

By performing such two-stage control, the screw 288 is used until the number of balls (prize balls or lending balls) counted based on the detection output of the payout motor position sensor 286 reaches the expected payout number. The ball can be paid out quickly by rotating the ball at a high speed to continuously pay out the ball. Can be accurate.

A firing control signal for controlling the firing state of the hit ball is given from the prize ball control board 37 to the firing control board 91. In the firing control board 91, when the firing control signal is at the LOW level, the firing of the hit ball is prohibited,
It is controlled so that the shot cannot be fired. On the other hand, when the firing control signal is at the HIGH level, the firing of the hit ball is permitted, and the firing of the hit ball is controlled to be possible.

A card balance display signal indicating the balance of the prepaid card and a ball lending permission display signal are given from the card unit 50 to the balance display board 74 via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal),
Ball lending request signal (BRQ signal), ball lending completion signal (EX
An S signal) and a pachinko machine operation signal (PRDY signal) are exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When a card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 controls the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the prize ball control CP
U371 controls the sorting solenoid 310 and directs the ball sorting member 311 to the ball lending side. Thereafter, when the payout is completed, the CPU 371 for controlling the prize ball controls the card unit 5
The EXS signal is output to 0.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, a signal is not input from the card unit 50 to the game control board 31, and there is room for a signal to be illegally input from the card unit 50 side to the game control microcomputer 53 of the game control board 31. Absent. The game control board 31 and the prize ball control board 3
7, a driver circuit for driving a solenoid, a motor, and a lamp is mounted. However, in FIG. 8, those circuits are omitted.

In this embodiment, in addition to the RAM 55 (see FIG. 4) of the game control board 31, at least the RAM 381 of the prize ball control board 37 is backed up by a backup power supply of the power supply board 910. For this reason, even if the power supply to the gaming machine is stopped, the RAM 55 and 381 can retain the stored contents for a certain period of time by the backup power supply.

Here, the connection between the respective boards of the pachinko gaming machine 1 will be described with reference to an electric circuit diagram.

First, the power supply board 910 will be described.
As shown in FIG. 9, the power supply board 910 includes a wiring Y connected to the lamp control board 35, a wiring connected to the power cord, a wiring D connected to the main board (game control board) 31 in order from the top, Wiring F connected to the prize ball control board (payout control board) 37, wiring G connected to the launch relay A board, wiring E connected to the payout control board, wiring A connected to the main board, and voice control board A wiring X connected to 70 is provided.

As shown in FIG. 10, the voice control board 70 to which the wiring X is connected is also connected to the wiring C from the main board 31. The voice control board 70 is further connected to the voice relay A board by wiring. The voice relay A board is connected to the voice relay B board and the voice relay C board by wiring. The audio relay B board and the audio relay C board are respectively connected to the left and right speakers 27.

Next, the electric circuit structure inside the voice control board 70 will be specifically described with reference to FIGS. Wirings 1/5, 2/5, 3 / introduced from power supply board 910
Wiring 3/5, 4/5, 5/5 out of 5, 4/5, 5/5
Is grounded. As described later, the wiring 1/5
A wiring for supplying power to the voice synthesis IC, to which a low-pass filter 200 for removing noise and a regulator 300 for creating predetermined power are connected. This regulator 300 reduces the voltage VDD of 12 V to the voltage AVcc of 5 V, and the voice synthesis IC
Is supplied with power.

As described above, the voltage AVcc used in the voice synthesis IC for processing an analog signal is generated in the regulator 300 which is a constant voltage circuit inside the voice control board 70, so that the power supply board 910 can be used for the voice control board 70.
The adverse effect of noise generated during the transmission to the device can be reduced. As a result, it is possible to reduce the adverse effect of noise on the sound generated from the speaker.

As shown in FIG. 12, the wiring C connected from the main substrate 31 in FIG. 10 is connected to the wiring to which the audio control signals CD0 to CD7, the audio control signal INT is input, and the GND (GRAND) line, respectively. Each of the wirings to which the audio control signals CD0 to CD7 and the audio control signal INT are input is connected to a buffer circuit 705 for preventing an unauthorized signal from entering the main board 31 side. From the buffer circuit 705, SCD0 to SCD
The DC7 signal and the SINT signal are output. This SC
As shown in FIG. 13, the D0 to SCD7 signals and the SINT signal are input to an audio control CPU 701 that performs a process for outputting audio. This voice control CPU 7
01 is connected to a reset switch 710.
Also, the SICK signal and S
The I signal, SIRQ signal, SRDY signal, and SRES signal are output.

Next, as shown in FIG. 14, the SICK signal, SI signal, SIRQ signal, SRDY signal, PRES signal
The signals are sent to the transistors 501 to 506, respectively, to turn on the transistors 501 to 506.
As a result, although the circuits from the transistors 501 to 506 use the power supply of the system by the voltage Vcc, the circuits after the transistors 501 to 506 use the power of the system by the voltage AVcc. Speech synthesis I that outputs a signal for synthesizing speech with power generated by turning on transistors 501 to 506
C702 is driven. The voice synthesis IC 702 is connected to a voice data ROM 711 in which voice data is stored. An audio data signal synthesized using the audio data is output from the audio synthesis IC as a DAOR signal.

Next, as shown in FIG. 15, the DAOL signal and the DAOR signal pass through a sound switching circuit 703 for adjusting the sound volume, and then reach a sound amplifying circuit 704 where they are amplified and amplified. Will be sent to

According to the present embodiment as described above, the transistors 501 to 506 which transmit electric signal information only from the voice control CPU 701 to the voice synthesizing IC 702 and do not cause reverse current flow are provided. The adverse effect of the noise generated at 27 is prevented from being transmitted to the voice control CPU 701. When the voice synthesis IC 702 consumes a larger amount of power than the voice control CPU 701, a change in power consumption of the voice synthesis IC 702 is prevented from having a large adverse effect on the voice control CPU 701. As a result, the voice control CPU 701 is driven stably.

Further, since the voice control CPU 701 is composed of a digital circuit relatively insensitive to noise and the voice synthesis IC 702 includes an analog circuit easily affected by noise, the voice control IC 702 is controlled by the transistors 501 to 506 from the voice control IC 702. If the influence of noise on the CPU 701 is prevented from being transmitted, the entire electronic circuit can be driven stably.

The voltage Vcc supplied from the wiring 2/5
The power of (+ 5V) is supplied to the voice control CPU 701, and the power of the voltage AVDD (+ 5V) generated from the power of 12V supplied from the wiring 1/5 is supplied to the voice synthesis IC7.
Since the power is supplied to the sound control circuit 702 and the sound amplification circuit 704, the power supply of the sound control CPU 701 is independent of the power supply of the sound synthesis IC 702 and the sound amplification circuit 704.
Therefore, it is possible to supply stable power to the voice control CPU 701 irrespective of a change in power consumption consumed by the sound amplification circuit 704 or the like. That is, depending on the operation state of the sound amplification circuit 704 and the like, the sound control CPU 70
The situation where the power supply to 1 is insufficient may occur,
In such a state, a failure such as a failure to correctly receive the control command output from the main board 31 may occur.
With the above structure, the CPU for voice control
At 701, the occurrence of a trouble such as a failure to correctly receive a control command is prevented.

Next, an electric circuit structure related to the display control board 80 will be described. As shown in FIG. 16, the display control board 80 is connected to the main board 31 and is also connected to the normal design board 180, the LCD module 280 or the CRT 82, respectively.

Next, the electric circuit structure inside the display control board 80 will be specifically described with reference to FIGS. As shown in FIG. 17, among the wirings connected from the main board 31 to the display control board 80, the wirings 10/16, 11/16,
12/16 is grounded. 13/16 and 14/16 connected to the power supply of the voltage Vcc are connected to a low-pass filter 107 for removing noise, and the voltage Vcc (5
V). 15/16 and 16/16 connected to a power supply of voltage VDD (12 V) are connected to a low-pass filter 108 for removing noise and a switching regulator 109 for producing a predetermined power and a voltage AVDD (5 V). Power supply.

As described above, the CRT 82 or the LCD 28
Voltage AV used in a circuit that processes analog signals such as 0
By creating the DD using the switching regulator 300, which is a constant voltage circuit of the display control board 80, it is possible to reduce the adverse effects of noise generated during transmission from the power supply board 910 to the display control board 80. As a result, adverse effects due to noise on the image displayed on the CRT 82 or the LCD 280 are reduced.

Also, as shown in FIG.
6, 2/16, 3/16, 4/16, 5/16, 6/1
The symbol control signals CD1 to CD7 and the symbol control signal INT are input from the main board 31 to each of 6, 7/16, 8/16 and 9/16. Symbol control signal CD1
After the noise is removed by the ferrite beads FB, the main substrate 31
The signal is input to a buffer circuit 105 for preventing the signal from flowing backward. From the buffer circuit 105, the IN0 signal to I
The N7 signal and the INT signal are output.

Next, as shown in FIG.
The IN7 signal and the INT signal are transmitted to the display control CPU 10.
1 is input. The display control CPU 101 has the configuration shown in FIG.
The display control data ROM 102 shown in FIG.
The display control CPU 101 has the VD shown in FIG.
P103 is connected, and the VDP 103 includes an oscillation circuit 8 having a crystal oscillator for timekeeping shown in FIGS.
5, a reset circuit 83 for initializing the circuit shown in FIG. 23, a VRAM 87 shown in FIG.
6a and the character ROM 86b are connected to each other. The VDP 103 reads out image data from the character ROM 86a and the character ROM 86b based on the input signal, generates image data, and
It is stored as display data in M87. Thereafter, as shown in FIG. 26, the VDP 103 further sends out the display data stored in the VRAM 87 as RGB signals. The transistors 508, 509, 51
0 turns ON. Thereby, transistors 508 and 50
The circuits up to 9, 510 are driven by the power supply of the voltage Vcc.
The circuit of the RT 82 or the LCD module 280 has the voltage A
It is driven by the power supply of VDD.

According to the present embodiment as described above, VD
Transistors 508 to 510 that transmit electric signal information only from P103 to CRT 82 or the like and do not cause reverse current flow
Is provided, the adverse effect of noise generated in the CRT 82 or the like is prevented from being transmitted to the VDP 103. When the CRT 82 consumes a larger amount of power than the VDP 103, a change in the power consumption of the CRT 82 does not adversely affect the VDP 103. As a result, the VDP 103 is driven stably.

Further, since the VDP 103 is composed of a digital circuit which is relatively insensitive to noise and the CRT 82 is an analog circuit which is easily affected by noise, the transistors 508 to 510 allow the VDP1 to be transmitted from the CRT 82 by the transistors 508 to 510.
If the influence of noise on the electronic circuit 03 is prevented from being transmitted, the entire electronic circuit can be driven stably.

The power of the voltage Vcc (5 V) supplied from the wirings 13/16 and 14/16 is supplied to the CPU 1 for display control.
01 and the like, and the power of the voltage AVcc (+5 V) generated from the power of the voltage VDD (15 V) supplied from the wirings 15/16 and 16/16 is supplied to the CRT 82 or the LCD 28.
Therefore, the power supply of the display control CPU 101 is independent of the power supply of the CRT 82 or the like. Therefore, it is possible to supply stable power to the display control CPU 101 irrespective of a change in the amount of power consumed by the CRT 82 or the like. That is, depending on the operation state of the CRT 82 or the like, there is a possibility that the power supply to the display control CPU 101 is insufficient. In such a state, the control command output from the main board 31 cannot be accurately received. However, such a structure prevents the display control CPU 101 from causing a failure such as a failure to correctly receive a control command.

Next, the structure of an electric circuit related to the lamp control board 35 will be described with reference to FIGS. FIG.
As shown in FIG. 7, the wiring Y drawn from the power supply board 910 shown in FIG. 9 is connected to the lamp control board 35.
The lamp control board 35 has a wiring B connected to the main board 35, a wiring y1 connected to the lamp relay board 35a shown in FIG. 28, and a frame lamp relay A board 3 shown in FIG.
A wiring y2 connected to 5h is provided.

Also, as shown in FIG.
The board 35a is formed by wiring, a sleeve left board 35b, a sleeve right board 35c, a center board 35d, an AT right board 35e, AT
It is connected to the middle board 35f and the AT left board 35g.

Also, as shown in FIG.
The board 35h is connected to the frame lamp relay B board 35i1 and the frame lamp relay C board 35i2 by wiring. The frame lamp relay B board 35i1 further includes a front lamp left B substrate 35j, a front lamp left A substrate 35k, a front lamp upper substrate 35l, a front lamp right A substrate 35m, and a front lamp right B substrate 35n. Are connected via wiring, and the frame lamp relay C board 35i2 includes a speaker LED left A board 35o, a speaker LED left B board 35p, and a speaker L
ED right B board 35g and speaker LED right A board 35
r is connected via wiring.

Next, the internal structure of the lamp control board 35 will be described with reference to FIGS. As shown in FIG. 30, wirings 1/6, 2 introduced from power supply board 910
/ 6, 3/6, 4/6, 5/6, 6/6
6 is supplied with the power of the voltage VSL through the switching regulator 700. In addition, wiring 2/6
This is a wiring supplying power of the voltage VLP. Wiring 3/6
, Power of the voltage VDD is supplied via the switching regulator 800. Vcc is supplied from the wiring 4/6 via the switching regulator 900. The wirings 5/6, 6/6 are grounded (GND).

As shown in FIG. 31, the lamp control board 35 has wirings 1/11 to 8 to which the lamp control signals CD0 to CD7 are inputted from the main board 31 shown in FIG.
/ 11, wiring 9/1 to which the lamp control signal INT is input
1 and GND wirings 10/11 and 11/11 are connected to each other, and a buffer circuit 355 for preventing the backflow of the signal from the lamp control CD0 signal and the lamp control signals CD1 to CD7 via ferrite beads for absorbing noise.
Is input to The buffer circuit 355 outputs the LCD0 signal and the LCD1 to LCD7 signals. Also,
The ramp control signal INT is transmitted through an inverter circuit to INT.
The signal is output.

Next, as shown in FIG. 32, each of the LCD0 signal to the LCD7 signal is input to the CPU 351 which outputs a signal for controlling the turning off of the lamp. C
From the PU 351, the BLAMP (B) signal, the BLAMP
(A) signal, BLED (F) signal, BLED (E) signal, BLED (D) signal, BLED (C) signal, BLE
A D (B) signal and a BLED (A) signal are output. The CPU 351 outputs the MMRY (a) signal, MMR
Y (b) signal, MMRY (c) signal, MMRY (d) signal, FLED (A) signal, FLED (B) signal, FLE
The D (C) signal and the FLED (D) signal are output. FL
ANP (A) signal, FLAMP (B) signal, FLAMP
(C) signal, FLAMP (D) signal, FLAMP (E)
A signal and a SLAMP signal are output. Furthermore, CPU3
51, a DG1 signal, a DG2 signal and a TLAMP signal.
A signal is output.

Next, as shown in FIG.
(A) signal, FLAMP (B) signal, FLAMP (C)
Signal, TRAMP signal, FLAMP (D) signal, SLA
Each of the NP signal and the FLAMP (E) signal is a circuit 511, 512, 513, 514, 515, 516, 5 including a transistor provided in such a manner as to prevent a backflow of current.
17 are respectively input.

Thereafter, circuits 511, including transistors,
Signals output from 512, 513, 514, 515, 516, and 517 are output from the lower right frame lamp (game effect lamp 28).
b, 28c), a wiring 1/18 for outputting a signal for controlling signals, an upper right frame lamp (game effect lamps 28b, 2c)
8c) for outputting a signal for controlling
18. Wiring 3/18 for outputting a signal for controlling a ceiling lamp (corresponding to gaming effect lamps 28b and 28c), and Wiring 4 for outputting a signal for controlling a ball cut lamp 52
/ 18, upper left frame lamp (game effect lamps 28b, 28c
5/1 for outputting a signal for controlling the
8. Wiring 6 for outputting a signal for controlling the prize ball lamp
/ 18, lower left frame lamp (game effect lamps 28b, 28c
To output a signal for controlling the
Are output to a frame lamp relay base A plate 35h including an analog circuit shown in FIG. The power of the voltage VLP is divided into the wirings 7/18 and 8/18,
Output to 5h.

Also, as shown in FIG.
The (A) signal, the FLED (B) signal, the FLED (C) signal, and the FLED (D) signal are an inverter circuit 52 including a transistor provided in a manner to prevent a backflow of current.
1,522,523,524,525,526,52
7, 528, and wiring 11/18, 12/18, 1
3/18, 14/18, 15/18, 16/18, 17
/ 18, 18/18 are output to the frame lamp relay A board 35h to control the left speaker outside LED, the left speaker inside LED, the right speaker inside LED, and the right speaker outside LED corresponding to the game effect LED 28a. . Further, the power of the voltage VSL obtained by rectifying and smoothing the power of the AC power supply AC of 24 V is supplied to the frame lamp relay A substrate 35h from 10/18.

Also, as shown in FIG.
(A) signal, BLED (B) signal, BLED (C) signal, BLED (D) signal, BLED (E) signal, BLE
Each of the D (F) signals is an inverter circuit 531 including a transistor provided in a manner to prevent a backflow of current.
532, 533, 534, 535, 536, 537, 5
38, the decoration LE corresponding to the game effect LED 25a
Wirings 3A, 2A, 1A, 6B, 10 for controlling D
B, 7B, 9B, and 8B are output to the lamp relay board 35a shown in FIG. The power of the voltage VSL is supplied from the wirings 4B, 5B, and 4A. BLAMP
The (A) signal and the BLAMP (B) signal are used to control decorative lamps A and B corresponding to the decorative lamp 25 via circuits 541 and 542 including transistors provided in such a manner as to prevent a backflow of current. Wiring 2B, 3B
Output from

As shown in FIG. 36, MMRY
The (a) signal, the MMRY (b) signal, the MMRY (c) signal, and the MMRY (d) signal are an inverter circuit 55 including a transistor provided in a manner to prevent current from flowing backward.
1, 552, 553, 554, LED1, LED2, LED3 and L
In order to control ED4, wires 10A, 9A, 8A, 7
A is output to the lamp relay board 35a shown in FIG. Further, the DG1 signal and the DG2 signal are output from the wirings 6A and 5A to the lamp relay board 35a via buffer circuits 555 and 556 including transistors provided in such a manner as to prevent a backflow of current. Further, the power of the voltage VLP is supplied by the wiring 1A.

The voltage VSL supplied from the wiring 1/6
(30V) power is supplied to various lamps, etc.
Since the power of the voltage VDD (5 V) supplied from 6 is supplied to the CPU 351 for lamp control and the like, the power supply of the CPU 351 for lamp control is independent from the power supply of various lamps and the like. Therefore, it is possible to supply stable power to the CPU 351 for lamp control irrespective of a change in the amount of power consumed by various lamps or the like. That is,
Depending on the operating state of various lamps, the lamp control C
There is a possibility that the power supply to the PU 351 is insufficient. In such a state, a failure such as a failure to correctly receive the control command output from the main board 31 may occur. By doing so, it is possible to prevent the lamp control CPU 351 from causing a failure such as not being able to receive a control command accurately.

The wires 10A to 7A are used to control both the special symbol start memory display and the normal symbol start memory display. That is, when the DG1 signal is in the active state, the start storage indicator of the ordinary symbol is controlled, and when the DG2 signal is in the active state, the start storage indicator of the special symbol is controlled. .

According to the lamp control board 35 having the above structure, the circuit 511 including the transistor shown in FIG.
Inverter circuits 521, 512 including transistors shown in FIG.
523, 524, 525, 526, 527 and 528, and an inverter circuit 531 including the transistors shown in FIG.
533, 534, 535, 536, 537, 538 and circuits 541, 542 including transistors, and inverter circuits 551, 552, including transistors illustrated in FIG.
Since the circuit includes the buffer circuits 555 and 556 including the transistors 553 and 554, the backflow of the current is prevented. The reason is that power of the voltage Vcc is supplied to each of the circuits including the transistor, and power of the voltages VSL and VLP is supplied to the circuits including the transistor. As a result, the lamp relay board 3 shown in FIG.
29 is prevented from being transmitted to a circuit up to the CPU 35 which is a digital circuit inside the lamp control board 35.

In the block diagram of FIG. 5,
Although the embodiment in which the transistors 508 to 510 are provided only between the VDP 103 and the CRT 280 (LCD 280) has been described, as shown in FIG.
1 and the VDP 103, the display control board 80 having the transistor 500 has a V that outputs an analog signal.
DP103 and display control CPU for outputting digital signals
To prevent a current from flowing back to the display control CPU 101, the display control CPU 1 comprising only a digital circuit.
Digital circuits up to 01 are prevented from being adversely affected by noise that is likely to occur in analog circuits after VDP103.

FIG. 38 shows the main substrate 3 shown in FIG.
1 shows a power supply input circuit immediately after power is taken from a power supply board 910. As shown in FIG. 38, the power supply input circuit of the main board passes through various bypass capacitors, smoothing capacitors, and noise filters 31a, 31b, 31c, and generates power on the power supply board 910, that is, voltages VSL, VDD, and Vcc. , VBB
Output to each IC etc. That is, in the main board 31, there is no need to provide a power generation unit for adjusting the voltage of the power used in each IC or the like, and thus no power generation unit is provided.

In the lamp substrate 35,
Power was supplied to various lamps using the voltage VSL (30 V) created by the power supply board 910.
A switching regulator, which is a constant voltage circuit, may be provided inside to generate new power. If you do this,
Since adverse effects due to noise generated during transmission from the power supply board 910 to the lamp control board 35 can be reduced, adverse effects due to noise appearing in various lamps are reduced.

According to the pachinko gaming machine of the present embodiment as described above, since the display control board 80, the voice control board 70, and the lamp control board 35 are supplied with power from the main board 31, the power supply board 910 Therefore, it is not necessary to provide a connector for connecting the power supply board 910 with the display control board 80, the audio control board 70, and the lamp control board 35. Thus, the number of connectors provided on the power supply board 910 can be reduced, so that the structure of the power supply board 910 is simplified.

According to the pachinko gaming machine of the present embodiment, it is not necessary to provide a connector for connecting power supply board 910 and display control board 80 to power supply board 910. As a result, when the variable display 10 and the display control board 80 are no longer required due to the model change, there is no unconnected connector on the power supply board 910. As a result, there is no possibility that information for performing unauthorized control is input from the unconnected connector of the power supply board 910 due to the presence of the unconnected connector. Therefore, it is possible to adopt a structure in which unauthorized control caused by a model change is prevented in advance.

Further, according to the pachinko gaming machine of the present embodiment, each of the display control board 80, the sound control board 70, and the lamp control board 35 uses the electric power supplied from the electric power supply means to generate electric components. The switching regulator 109 is used as power generation means for generating power required for control.
Therefore, there is no need to provide an external power generation unit for generating necessary power.

FIG. 39 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 39, a voltage drop signal from a first power supply monitoring circuit (power supply monitoring means or first power supply monitoring means) outputs a non-maskable interrupt terminal (NMI
Terminal). The first power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC currents used by the gaming machine and detects a power supply voltage drop. In this embodiment, the first power supply monitoring circuit monitors the power supply voltage of VSL, and generates a low-level voltage drop signal when the voltage value falls below a predetermined value. The power supply voltage VSL is the largest DC voltage used in the gaming machine and is +30 V in this example. Therefore, the CPU 56
It is possible to confirm the occurrence of power cut or power drop by the interrupt processing. In this embodiment, the first
Is mounted on a power supply board described later.

FIG. 39 also shows a system reset circuit 65. In this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, the reset IC 651
When the power is turned on, the output is set to the low level for a predetermined time determined by the external capacitor 652 and the capacitance, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors a power supply voltage VSL which is a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and sets the voltage value to a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage falls below the power supply voltage value), a low-level voltage drop signal is generated. Therefore, the CPU 56 performs a predetermined power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit, and then performs a system reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

As shown in FIG. 39, the reset IC 651
Is input to a NAND circuit 947 (an AND circuit) and an inverting circuit (NOT circuit) 9
The signal is input to the clear terminal of the counter IC 941 via the terminal 44. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943. Then, the Q5 output of the counter IC 941 is supplied to the NAND circuit 94 via NOT circuits 945 and 946.
7 is input. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is a logical sum circuit (OR circuit) 94.
9 is input. The other input of the OR circuit 949 includes N
The output of the AND circuit 947 is introduced via a NOT circuit 948. The output of the OR circuit 949 is output to the CPU 56.
Connected to the reset terminal. According to such a configuration, two reset signals (low level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
The CPU 56 reliably starts operating.

Then, for example, the detection voltage of the first power supply monitoring circuit (the voltage at which a voltage drop signal is output) is set to +22 V, and the detection voltage of the second power supply monitoring circuit is set to +9 V
And In such a configuration, the first power supply monitoring circuit and the second power supply monitoring circuit have the same power supply voltage VSL.
, The difference between the timing at which the first power supply monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined time. . The desired predetermined time is a period from when the power supply stop processing is started in response to the voltage drop signal issued from the first power supply monitoring circuit until the power supply stop processing is surely completed.

In this example, the first detection condition under which the first power supply monitoring means outputs a detection signal is that the +30 V power supply voltage has dropped to +22 V, and the second power supply monitoring means outputs the detection signal. The second detection condition to be output is that the + 30V power supply voltage has dropped to + 9V. However, the voltage value used here is an example, and another value may be used.

However, although the monitoring range is narrowed, the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit is +
It is also possible to use a 5V power supply voltage. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. And when the + 5V power is restored,
Since a reset signal is issued from the system reset circuit 65, the CPU 56 returns to a normal operation state. At that time, since the necessary backup storage information is stored, it is possible to return to the gaming state at the time when the power failure occurred at the time of recovery from the power failure or the like.

In FIG. 39, when the power is turned on, the CPU 5
6 shows a configuration in which a reset signal (low-level signal) is applied twice to the reset terminal. However, when a reset signal is reliably released even when there is only one rising timing of the reset signal, a CPU is used. , Symbols 941 to 94
The circuit element indicated by 9 is unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

The delay time defined by the capacitance of the external capacitor 652 of the reset IC 651 starts when the power supply from the power supply board 910 starts and the respective boards (the sound control board 70, the lamp control board 35, the display control board 80 , The payout control board 37) is fully activated. Thereby, the inconvenience that the output target board is not operating when the CPU 56 of the game control means outputs the control command and the control according to the command cannot be performed is solved.

In addition to the external capacitor 652, a delay circuit may be provided in the middle of a signal line for transmitting a signal output from the reset IC 651 to the CPU 56, and a standby process may be performed when the CPU 56 starts processing. Further, means for managing the system reset of each board may be provided in the power supply board 910, and the power-up board 910 may manage the startup sequence.

Also, the system reset circuit 65
It may be configured to include an initial reset circuit that outputs a system reset signal to the CPU at the start of power supply, and a power supply monitoring circuit that detects a voltage drop and stops the operation of the CPU.

FIG. 40 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the audio control board 70, the lamp control board 35, and the payout control board 37, and each of the electric component control boards in the gaming machine and Generates voltages used by mechanical components. In this example, AC24V, DC + 30V (VSL), DC + 21
V, + 12V DC (VDD) and + 5V DC (Vcc). A capacitor 9 serving as a backup power supply
16 is charged from a DC + 5V (VBB), that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
Numeral 5 is connected to a relay board, for example, and electric power of a voltage required for each electrical component control board and mechanical components is supplied from the relay board. A power switch for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with a power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also, +
A diode 917 for preventing backflow is inserted between the 5V line and the backup + 5V line.

A battery that can be charged from a + 5V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply monitoring circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing the power supply voltage VSL and monitoring the power supply voltage VSL. Specifically, when the power supply voltage VSL becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output on the assumption that power supply cutoff or voltage drop occurs. In addition,
The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, the voltage VSL (+30 V) immediately after conversion from AC to DC is used. The voltage drop signal from the power supply monitoring IC 902 is supplied to various control boards such as the main board 31 and the payout control board 37.

The predetermined value for the power supply monitoring IC 902 to detect a power supply cutoff or a voltage drop is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. . Also, a power supply monitoring IC 902
Is higher than a voltage (+5 V in this example) for driving a circuit element such as a CPU, and is configured to monitor a voltage immediately after conversion from AC to DC.
The monitoring range can be extended for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Further, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection when the power is turned off can be expected. That is, when monitoring the voltage of the + 30V power supply, the + 12V generated after the + 30V generation
Can be detected before it begins to fall. Therefore, when the voltage of the + 12V power supply drops, the switch output comes to an on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized,
It is possible to enter a state of waiting for a power supply recovery before the switch output is turned on, so that the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of electric component control boards. Can be. No matter how many electrical component control boards require a voltage drop signal, only one first power supply monitoring means needs to be provided, and each electrical component control means in each electrical component control board performs return control described later. However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 40, the detection output (voltage drop signal) of power supply monitoring IC 902 is supplied to electrical component control boards (eg, main board 31 and payout control board) via buffer circuits 918 and 919, respectively. 37). For example, a configuration may be adopted in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit may be provided according to the number of substrates requiring a voltage drop signal.

Next, the operation of the gaming machine will be described. FIG. 41 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, necessary initial settings are made (step S1).

Then, it is confirmed whether or not the data width of the backup RAM area has been processed (NMI processing for power failure occurrence such as load of parity data in this example) when the power is turned off (step S2). If an unexpected power loss occurs,
As will be described later, processing for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. If the confirmation result indicates that there is no backup, an initial process is executed (steps S2 and S3). In this example, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. In this example,
If "55H" is set in the backup flag area, it means that there is a backup (on state) and "55H"
If a value other than is set, it means no backup (off state).

When backup data exists in the backup RAM area, in this embodiment, the CPU 56
Performs a data check (parity check in this example) of the backup RAM area (step S4). If recovery is performed after an unexpected power failure, the data in the backup RAM area must have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, an initialization process executed at the time of power-on without power recovery is executed (steps S5 and S3).

If the check result is normal, the CPU 56
Performs a game state restoring process for returning the internal state to the state when the power is turned off (step S6). Therefore, in this example, as shown in FIG. 42, when the value of the backup flag is set to “55H” and the check result is normal, the processing shifts to the game state restoration processing of step S6. Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area (step S7).

Execution of normal initialization processing (step S2,
After S3), the main processing executed by the CPU 56 shifts to a loop processing in which the monitoring of the timer interrupt flag (step S9) is confirmed. In the loop, a display random number update process (step S8) is also performed.

In this embodiment, step S2
After checking the presence or absence of the backup data, if the backup data exists, the backup area is checked in step S4. Conversely, after confirming that the check result of the backup area is normal, Alternatively, the presence or absence of backup data may be confirmed. In addition, a configuration may be adopted in which it is determined whether to execute the power failure recovery process by confirming whether there is backup data or checking the backup area.

In the normal initialization processing, as shown in FIG. 43, the RAM is cleared (step S3).
a). Then, based on the address value of the work area initial setting table, a predetermined work area (for example, a random number counter for normal symbol determination, a buffer for normal symbol determination, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) is initialized. An initial value setting process for setting a value (step S3b) is performed. Then, the initial setting of the timer register provided in the CPU 56 (setting that the timeout is 2 ms and the setting of the operation of the repetitive timer) is performed so that the timer interrupt is periodically performed every 2 ms (step S).
3c). That is, in step S3c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed. Then, the initial setting process (step S
Since the interrupt is prohibited (see FIG. 45) in 1), the interrupt is permitted before the initialization process is completed (step S3d).

Therefore, in this embodiment, the CPU
56 internal timers are set to repeatedly generate timer interrupts. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 44, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

When detecting that the timer interrupt flag has been set in step S9, the CPU 56 resets the timer interrupt flag (step S1).
0), a game control process is executed (step S11). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing.
Although the game control process is executed in the main process, the game control process in the timer interrupt process may be executed.

As described above, it is determined whether or not the power is restored to the state when the power is turned off based on the presence or absence of the backup data, so that when the power is turned on when the power is restored after a power failure or the like, the backup is performed. It is possible to determine whether or not to restore the power-off state according to the contents of the data storage area. Therefore, control based on backup data can be realized, and unnecessary execution of recovery processing can be prevented.

Further, by determining whether or not the power is restored to the state at the time of power failure according to the state of the backup data, when the power is turned on when the power is restored after a power failure, the backup data storage area is determined. It is possible to determine whether or not the power is restored to the state at the time of power cutoff according to the state of the contents of the above. Therefore, control based on normal backup data can be realized, and execution of recovery processing based on abnormal backup data can be prevented.

FIG. 45 is a flowchart showing the initial setting process in step S1. In the initial setting process, C
The PU 56 first sets interrupt prohibition (step S1).
a). When the interrupt is set to be prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designated address to the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d), and sets the CTC to be usable by setting the interrupt mode 2 described above.
After initialization of the (counter / timer) and PIO (parallel input / output port) (step S1e), access to the RAM is disabled because the RAM is disabled to protect the contents of the RAM when the power is turned off. The state is set (step S1f).

Note that there are the following three types of maskable interrupt modes in which an interrupt is permitted by inputting an INT signal that can be set in the initial setting process.

Interrupt mode 0: This mode is set at the time of reset, and is an address (00 (H) to (H) designated by an interrupt source by a 1-byte CALL instruction RST instruction.
38 (H)) is a mode indicating the start address of the interrupt processing program.

Interrupt mode 1: A mode in which the start address (38 (H)) of the interrupt processing program is predetermined.

Interrupt mode 2: An address composed of a value (1 byte) of a specific register of the CPU 56 and an interrupt vector (1 byte: maximum bit 0) output from a built-in device indicates an interrupt address. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector.

FIG. 46 is a flowchart showing the game control processing in step S11. In the game control process,
The CPU 56 firstly receives the gate sensor 12, the starting port sensor 17, and the count sensor 23 through the switch circuit 58.
And the state of the winning opening switches 19a and 24a,
It is determined whether or not there is a winning for each winning opening or a winning device (switch processing: step S21).

Subsequently, abnormality diagnosis processing is performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process of updating a display random number such as a random number that determines the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 in a predetermined order by the 7-segment LED. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 outputs a special symbol control command and a normal symbol control command after performing a process of setting a special symbol control command and a normal symbol signal command sent to the display control board 80 in a predetermined area of the RAM 55. (Special symbol command control processing:
Step S27, normal symbol command control processing: step S28).

Next, CPU 56 performs a process of outputting the contents of the storage area for various output data to each output port (data output process: step S29). Note that the CPU 5
6 also performs other processing such as output data setting processing for setting output data such as big hit information, start information and probability variation information output to the hall management computer in the storage area.

The CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 according to the drive command, and the variable winning ball device 19
Alternatively, the open / close plate 22 is set to the open state or the closed state. Also,
The CPU 56 sets, for example, the number of winning balls based on the detection of each winning opening such as the winning opening 24 (step S3).
1). That is, when a predetermined condition is satisfied, a payout control command is output to the payout control board 37. Dispensing control board 37
The payout control CPU 371 mounted on the device drives the ball payout device 97 in accordance with the payout control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
In the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, a flag for determining whether or not to shift to the game control process is set, so that all of the game control process is surely performed. Be executed. In other words, until all of the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process have completed execution. Have been.

In the conventional general game control processing, the game machine is forcibly returned to the initial state by an external interrupt that occurs periodically. Explaining with reference to the example shown in FIG. 46, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good.

Even in such a configuration, the flag is not determined until all the game control processes have been executed. Therefore, it is possible to complete the execution of all the processes in the game control process. Guaranteed.

FIG. 47 is a flowchart showing an example of the power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, first, the CPU 56 stores the contents of the interrupt prohibition flag in the parity flag in order to back up the interrupt permission / prohibition state immediately before the power failure such as during a power failure (step S41). Next, interrupt prohibition is set (step S42). Power failure occurrence NMI
In the process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If other interrupt processing is performed during that processing, the voltage may drop to a level at which the CPU cannot operate before the checksum generation processing is completed. Is set so as not to occur. Steps S44 to S50 in the power failure occurrence NMI process are an example of a power supply stop process.

If a CPU is used that does not cause another interrupt during the interrupt processing, the processing in step S42 is unnecessary.

Next, the CPU 56 checks whether or not the backup flag has already been set (step S).
42). If the backup flag has already been set, no further processing is performed. If the backup set has not been set, the following power supply stop processing is executed. That is, from step S44 to step S55
Execute the processing of

First, the contents of each register are backed up by R
Step S44 for storing in the AM area). Thereafter, a backup flag is set (step S45). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S46), exclusive OR is sequentially performed on the initial value and the data of the backup RAM area, and the result is inverted (step S47). The calculated value is set in the backup parity data area (step S48). Further, the RAM access is prohibited (step S49). Further, all output ports are turned off (step S50). When the power supply voltage is low, the levels of various signal lines may become unstable and the contents of the RAM may be garbled.
The data in the AM will not be corrupted.

Subsequently, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the system reset signal from the reset IC 651 shown in FIG. 39, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur when the power supply voltage decreases.

In this embodiment, the power failure occurrence NM
In I processing, the program was looped in the last part,
It may be configured to issue a HALT instruction.

The backup flag set after storing the contents of the register in the RAM area is, as described above, whether or not there is backup data to be restored at power-on (whether or not to recover from a power failure). Used to judge. Further, the processing of steps S41 to S50 is completed before the CPU 56 receives the system reset signal from the system reset circuit 65. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 65.

In this embodiment, the backup flag is checked at the start of the power supply stop processing. If the backup flag has already been set, the power supply stop processing is not performed. As described above, the backup flag is a flag indicating that the backup of necessary data has been completed and then the power supply stop processing has been completed. Therefore, for example, even if the NMI occurs again due to a reset waiting loop state, the power supply stop processing will not be executed repeatedly.

However, if a CPU having a specification that prevents other interrupts during the interrupt processing is used, the determination in step S43 is unnecessary.

FIG. 48 is an explanatory diagram for explaining an example of a backup parity data creating method. However,
In the example shown in FIG. 48, the data size of the backup data RAM area is set to 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 48, initial data (00H in this example) is set in the backup check data area. Next, "00H"
And "F0H" are exclusive ORed, and the result is "1"
6H "is exclusive-ORed. Furthermore, as a result,
The exclusive OR of "DFH" is obtained. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, parity diagnosis is performed in the power failure recovery processing. If all the data in the backup area is stored as it is, the data as shown in FIG. 48 is set in the backup area when the power is turned on again.

In the processing of step S4, the CPU 56
Performs the same processing as the processing executed in the power failure occurrence NMI processing. That is, initial data (00H in this example) is set in the backup check data area,
An exclusive OR of “00H” and “F0H” is obtained, and as a result, an exclusive OR of “16H” is obtained. further,
The exclusive OR of the result and "DFH" is obtained. Then, a final operation result obtained by inverting the result (“39H” in this example) is obtained. If all data in the backup area is stored as it is, the final calculation result is “C6
H ", that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result does not become “C6H”.

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with a storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the game machine is turned off. When the power is turned on, the CPU 56
(Specifically, the program executed by the CPU 56) is configured to perform a game state restoration process (step S6) for restoring the game state based on the backup data if the storage means is in the backup state.

In this embodiment, a power supply monitoring circuit is mounted on a power supply board 910 as shown in FIG.
As shown in FIG.
5 is mounted. When the system reset circuit 65 generates the low-level system reset signal when the power supply voltage decreases, the power supply monitoring circuit (in this example, the power supply monitoring IC 902) uses the low-level NMI.
It is set so as to be later than the time when the interrupt signal is generated. Further, a low-level system reset signal from the system reset circuit 65 is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters the loop state after executing the power failure generation processing (power supply stop processing) based on the voltage drop signal from the power supply monitoring means (power supply monitoring IC 902). , And enters a reset state. That is, the operation of the CPU 56 is completely stopped. In the case of the + 5V power supply voltage value below, normal operation of the CPU 56 cannot be ensured (that is, a state in which operation cannot be managed occurs).
Since the reset state is established when the power that can operate normally is supplied, abnormal operation based on undefined data is prevented.

As described above, in this embodiment, the CPU
56 is configured to enter a loop state in response to the input of the detection output from the power supply monitoring circuit, and to be reset in response to the input of the detection signal from the system reset circuit 65. Therefore, when the power is turned off, the data is reliably stored, thereby preventing the player from being disadvantaged.

In this embodiment, the power supply monitoring I
Although the C902 and the system reset circuit 65 monitor the same power supply voltage, they may monitor different power supply voltages. For example, the power supply monitoring circuit of the power supply board 910 has +30
The V power supply voltage is monitored, and the system reset circuit 65
The V power supply voltage may be monitored. The timing at which the system reset circuit 65 generates the low-level system reset signal is delayed with respect to the timing at which the power supply monitoring circuit generates the NMI interrupt signal. A reset signal generation voltage level is set. For example, the threshold is 4.25V. 4.25V is the CPU 56
Is lower than a normal voltage value at which the CPU 56 operates, but is a voltage at which the CPU 56 can operate for a while. The power supply monitoring circuit adjusts the delay time (in this example, the capacitance of the capacitor) of the delay means provided in the system reset circuit 65 to determine when the system reset circuit 65 generates a low-level system reset signal. You may make it delay with respect to the timing which generates an interrupt signal.

Further, in the above embodiment, the CPU 56
Detects an NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) via the non-maskable interrupt terminal (NMI terminal), but detects the NMI interrupt signal as a maskable interrupt terminal (IRQ Terminal). In that case, the power supply stop processing is executed in the interrupt processing (IRQ processing). Further, an NMI interrupt signal from the power supply board 910 via the input port may be detected. In that case,
The monitoring of the input port is performed in the main processing.

When an interrupt signal from the power supply board 910 is detected via the IRQ terminal instead of the NMI interrupt signal, an IRQ interrupt mask is set at the start of the game control process in step S10 of the main process. Alternatively, the IRQ interrupt mask may be released at the end of the game control process. In such a case, an interruption occurs before and after the start of the game control process, so that the game control process is not interrupted halfway. Accordingly, when the payout control command is sent to the payout control board 37, the command sending is not interrupted.
Therefore, even when a power failure occurs, the payout control command or the like completes the delivery.

Further, in this embodiment, in the power failure occurrence processing (power supply stop processing), when the backup flag indicating that the data has already been backed up and the power supply stop processing has already been executed is set up, Are configured not to execute the power supply stop processing. In the process of power down, NMI may occur again. Then, if the backup flag is not confirmed in the power generation processing, the power supply stop processing is executed again by the NMI that has been generated again. In the power supply stoppage processing executed first, processing for storing the contents of the register in the backup RAM is performed (see step S44 in FIG. 46). In a state of waiting for reset after the normal power supply stop processing executed first, the power supply voltage gradually decreases, so that the contents of the register may be destroyed. That is, the register value may have changed from the state at the time when the power-off was detected (when NMI first occurred). If the power supply stop processing is executed again in such a state, a value different from the register value in the state at the time when the power-off is detected is stored in the backup RAM. Then, in the power restoration processing executed when the power is restored, a value different from the register value in the state at the time when the power interruption is detected is restored to the register. As a result, there is a possibility that a game state different from the game state when the power is turned off is reproduced.

[0212] Hereinafter, the game state restoration processing will be described. FIG. 49 is a flowchart showing an example of the gaming state restoring process shown in step S6 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (Step S61). Then, based on the data stored in the backup RAM, the game state at the time of the power failure is confirmed and restored. That is, based on the data stored in the backup RAM, the solenoids 16 and 21 are connected via the solenoid circuit 59.
To restore the open / closed state of the starting winning port 24 and the opening / closing plate 22, for example (steps S62 and S63). In addition, according to the value of the special symbol process flag and the normal symbol process flag that were driven even when the power was turned off, a control command corresponding to the progress status of the special symbol process process and the progress status of the normal symbol process process when the power was turned off, It is sent to the display control board 80, the lamp control board 35, and the audio control board 70 (step S63).

As described above, in the game state restoring process, the states of various electric components are restored according to the restored internal state, and the display control board 80, the lamp control board 35, and the voice control board 70 are restored. Then, a control command for returning the control state to the power-off state (control command for processing the control state at the time of power-off) is sent out. Such a control command is generally one or more control commands last sent out prior to power down.

As a result, in this embodiment, the following state restoration can be performed by the game state restoration processing. The states of the starting winning port 14 and the special winning port (opening / closing plate) 22 are restored. The display state of the ordinary symbol (the display state of the variable display 10) controlled by the display control means is restored except for the case where it is changing when the power is turned off. The display state of the special symbol controlled by the display control means (the display state of the variable display unit 9) is restored except for the case where it is changing when the power is turned off. Further, the background and the character displayed on the variable display section 9 are restored except when the special symbol is being changed and the big hit is being played.

When the power is turned off during the change of the special symbol, information on the change time (for example, 10 seconds) of the variable display pattern and the time already executed (for example, 4 seconds) are backed up. Then, the main board 31 outputs a display control command indicating a display pattern and a display control command indicating a stop symbol to the display control board 80 at the time of popularization, and stops the symbol after a lapse of the remaining time (6 seconds in the above example). Output a display control command to cause Therefore, when the special symbol is being changed when the power is turned off, the display state of the special symbol is variably displayed for the remaining time (6 seconds in the above example) not displayed at the time of restoration. The display control command indicating the display pattern output to the display control board 80 at the time of restoration may be the same as the display control command indicating the display pattern output before the power is turned off. It is good also as a command for displaying an image such as "middle." In this case, the display "recovering power" is displayed as the remaining time (6 seconds in the above example). The same control as described above is performed based on the display state of the ordinary symbols when the power is turned off during the change of the special symbols.

[0216] When the power is cut off during the big hit game, the remaining time of the round or the interval between the rounds is restored when the power is cut off during the change of the special symbol. , Display, sound, lamp,
The solenoids 16 and 21 are controlled.
Outputs a display control command to the display control board 80 which designates a symbol at the time of confirmation (stop symbol) output before the power is turned off.

With this, it is possible to perform the effect by the big hit symbol during the round or between the rounds (for the model that performs the big hit with the big hit symbol), and the display control board 80 also recognizes the symbol to be displayed at the start of the fluctuation after the big hit end. be able to.

Decoration lamp 2 controlled by lamp control means
5, start memory display 18, gate passage memory display 41,
The display states of the prize ball lamp 51 and the cut-out lamp 52 are restored. Game effect lamps / LEDs 28a, 28b, 2
The display state of 8c is restored except when the special symbol is being changed and the big hit is being played. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored. Each of the control sections is, for example, a jackpot start holding state, a state before the opening of the special winning opening, a state during the opening of the special winning opening, and a notification state of the end of the big hit. When the power is turned off during the special symbol change and the power is turned off, the game effect lamps / LEDs 28a, 28b, and 28 are provided for the remaining time, similarly to the display control of the variable display unit 9 and the variable display device 10 described above.
Although the display state of c may be controlled, it may be turned on or blinked in a pattern specific to turning off or restoring the power failure.

The sound generation state controlled by the sound control means is as follows.
It is restored except during special symbol change and big hit game. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored. When the power is turned off during the special symbol change and the power is turned off, the sound generation state is controlled for the remaining time in the same manner as the display control of the variable display unit 9 and the variable display device 10 described above. No sound, or voice pattern specific to power outage recovery (for example, "Power recovery is in progress")
May be output.

In this embodiment, at the time of restoration from a power-off, a control command for restoring a state is sent from the game control means of the main board 31 to the display control means, the lamp control means and the voice control means. However, when the display control means, the lamp control means, and the audio control means are backed up by a power source, the display control means, the lamp control means, and the audio control means are independently controlled without using a control command from the main board 31. May be configured to be restored.

As described later, the payout control board 37
Since the payout control means mounted on the power supply is backed up by a power supply, the prize ball payout state and the ball lending control state are restored to the state at the time of the power supply cutoff when the power supply is restored. In this embodiment, since the launch control board is connected to the payout control board, the control state of the launch control board 91 is similarly restored.

When the gaming state is restored to the state at the time of power-off, in this embodiment, the CPU 56 restores the interrupt permission / prohibition state at the time of the previous power-off to restore the parity stored in the backup RAM. The value of the flag is confirmed (step S64). If the parity flag is clear, interrupt permission setting is performed (step S65). on the other hand,
If the parity flag is on, the process proceeds to step S
The game state restoring process ends (with the interrupt prohibition state set in 1a).

Here, the game state restoring processing program is configured to return to the main processing when the game state restoring processing ends, but the stack area pointed to by the stack pointer stored in the power supply stop processing is set. The address stored in the backup RAM area (in the backup RAM area) (the address executed when the NMI interrupt occurs when the power is turned off) may be returned.

As described above, after the initial setting process is started and before the recovery process is completed or before the initialization process is completed, the interrupt is prohibited. Since it is possible to prevent the processing from being interrupted, it is necessary to perform initialization, determination as to whether or not to restore the state at the time of power interruption performed according to the contents of the backup data storage area, and recovery processing (or initialization processing). ) Can be surely completed. Even in the case where the interrupt prohibition state is set before the end of the recovery processing as described above, the interrupt prohibition / permission state at the time of power-off is backed up by the parity flag. The interrupt prohibition / permission state at power-off can be reliably restored.

In the above embodiment, the case has been described where the game control means performs the data storage processing and the recovery processing. However, the payout control means, the voice control means, the ramp control means, and the RAM in the display control means have been described.
May be backed up, and the payout control means, the display control means, the voice control means, and the lamp control means may also perform the above-described processing. However, the payout control means, the display control means, the voice control means, and the lamp control means need not perform the command transmission processing at the time of restoration.

FIG. 50 is an explanatory diagram showing an example of the command form of the payout control command. In this embodiment, the payout control command has a 2-byte structure, and the first byte is M bytes.
ODE (command classification), the second byte is EX
Indicates T (type of command). The command form shown in FIG. 50 is an example, and another command form may be used.

FIG. 51 is an explanatory diagram showing an example of the content of the payout control command. In the example shown in FIG. 51, the command FF00 (H) is a payout control command that specifies a payable state. The command FF01 (H) is a payout control command for specifying a payout stop state. The command F0XX (H) is a payout control command for specifying the number of winning balls. “XX” in the second byte indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout control means stops the prize ball payout and ball lending.
When the payout control command of (H) is received, the prize ball can be paid out and the ball can be lent. Further, when a payout control command specifying the number of winning balls is received, award ball payout control according to the number specified by the received command is performed.

FIG. 52 is a timing chart showing an example of a delivery mode of the payout control command. In this embodiment,
The payout control command has a 2-byte configuration. For example, as shown in FIG. 52, when the first byte and the second byte of the payout control signal are output, INT
The signal is turned on (low level in this example). The ON period of the INT signal is, for example, 1 μs or more, and a period of, for example, 10 μs or more is provided between the first byte and the second byte. Note that the payout control command may have a one-byte configuration.

Note that the payout control command is sent only once so that the payout control means can recognize it. Recognizable means that the INT signal is turned on in this example, and is sent only once so that it can be recognized. In this example, it means that the INT signal is turned on in accordance with each of the first and second bytes of the payout control signal. That is, the INT signal is turned on only once.

As shown in FIG. 53, the payout control command may have a one-byte structure. In this case, a payout control command is output by 8-bit payout control signals CD0 to CD7. Then, when the payout control signal is being output, the INT signal is turned on (low level in this example). The ON period of the INT signal is, for example, 1 μs or more. The payout control means inputs the payout control signals CD0 to CD7 by interrupt processing according to the INT signal.

Next, as an example of the case where the data saving processing and the restoring processing are performed by the electric component control means other than the game control means, the case where the payout control means stores and restores the data will be described.

FIG. 54 is a block diagram showing an example of a configuration around the payout control CPU 371. As shown in FIG. 54, a voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is supplied to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960.
It is connected to the. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. In this embodiment, the voltage value to monitor the supply voltage V _SL to generate a voltage drop signal at a low level and becomes equal to or less than the predetermined value. The voltage VSL is the largest DC voltage used in the gaming machine, and is +30 V in this example. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the interrupt processing.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When the clock signal is input to the CLK / TRG2 terminal, the value of the time counter register CLK / TRG2 incorporated in the payout control CPU 371 is counted down. When the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / T
If the initial value of RG2 is set to "1", an interrupt will occur in response to the input of the INT signal.

[0235] The payout control board 37 is also provided with a system reset circuit 975. In this embodiment,
The system reset circuit 975 also functions as a second power supply monitoring circuit (second power supply monitoring unit). That is, the reset IC 976 sets the output to a low level for a predetermined time determined by the capacitance of the capacitor when the power is turned on, and sets the output to a high level after the predetermined time has elapsed. Also, reset IC 9
76 monitors a voltage VSL, which is a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, and changes the low level to a low level when the voltage value falls below a predetermined value (for example, + 9V). Generates a low signal. Therefore, when the power supply is turned off, the voltage drop signal from the reset IC 976 becomes low level, so that the payout control CP
U371 is reset. As shown in FIG. 54, the voltage drop signal is the same output signal as the reset signal.

The predetermined value for the reset IC 976 to detect a power-off is lower than the normal voltage, but is a voltage at which the CPU 371 for payout control can operate for a while. Further, the reset IC 976 is connected to the payout control CPU 3.
Since it is configured to monitor a voltage higher than the voltage required by 71 (+5 V in this example), it is possible to extend the monitoring range for the voltage required by the payout control CPU 371. Therefore, more precise monitoring can be performed.

While power is not supplied from the power supply of +5 V, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supplied from the power supply board to the backup terminal, and The contents are saved even if the power to the machine is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state.
At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine. Then, when the voltage of the power supply falls below a predetermined value, a voltage drop signal (power-off detection signal) is generated. At the timing output from the power-off detection signal, the IC drive voltage is still a voltage that can sufficiently drive various circuit elements. Therefore, the operation time for the payout control CPU 371 of the payout control board 37 operating at the IC drive voltage to perform the predetermined power supply stop processing is secured.

Note that, also here, the first power supply monitoring circuit
The power supply voltage VSL, which is the highest power supply among the DC voltages used in the game machine, is monitored. The monitoring target voltage need not be the highest power supply voltage VSL as long as the operation time for performing the stop-time processing is secured. That is, if at least a voltage higher than the IC drive voltage is sensed, the power-off detection signal may be generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. it can.

In this case, as described above, the voltage to be monitored is +12 V supplied to various switches of the gaming machine such as the prize ball count switch 301A, and therefore, erroneous switch-on detection at power-off is also prevented. It is preferable that the voltage can be expected. That is, it is preferable to detect the voltage drop before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is desirable to monitor at least a voltage higher than the switch voltage.

In the configuration shown in FIG. 54, when power is turned on, system reset circuit 975 outputs a low level for a period determined by the capacity of a capacitor, and then outputs a high level. That is, the reset circuit timing is 1
Only once. However, as in the case of the main substrate 31 shown in FIG. 39, a circuit configuration in which reset circuit timing occurs a plurality of times may be used.

The delay time defined by the capacitance of the external capacitor 977 of the reset IC 976 starts when the power supply from the power supply board 910 starts, and the respective boards (audio control board 70, lamp control board 35, display control board 80 , Payout control board 37) is secured for a sufficient time to completely start. This eliminates the inconvenience that the output target board is not operating at the time when the CPU 371 of the game control means outputs the control command, and control in accordance with the command cannot be performed.

In addition to the external capacitor 977, a delay circuit is provided in the middle of a signal line for transmitting a signal output from the reset IC 976 to the CPU 56.
The standby process may be performed at the start of the process. Further, a means for managing the system reset of each board may be provided on the power supply board, and the power-up board 910 may manage the startup sequence.

In addition, the system reset circuit 975
May be configured to include an initial reset circuit that outputs a system reset signal to the CPU 371 at the start of power supply, and a power supply monitoring circuit that stops the operation of the CPU 371 by detecting a voltage drop.

FIG. 55 is a flowchart showing the main processing of the payout control CPU 371. In the main processing,
The payout control CPU 371 first makes necessary initial settings (step S701).

FIG. 56 is a flowchart showing the initial setting process in step S701. In the initial setting process, the payout control CPU 371 first sets interrupt prohibition (step S701a). Next, the payout control CPU
The control unit 371 sets the interrupt mode to the interrupt mode 2 (step S701b), and sets a stack pointer designation address in the stack pointer (step S701c). The payout control CPU 371 initializes the internal device register (step S701d),
After the initialization of the timer) and the PIO (parallel input / output port) (step S701e), the RAM is set to an accessible state (step S701f).

In this embodiment, an interrupt based on the count-up of CH2 and CH3 is used as a timer / counter interrupt. The interrupt based on the count-up of CH2 is
This interrupt occurs when the value of the timer counter register CLK / TRG2 becomes “0”. Therefore, in step S701e, the initial value “1” is set in the timer counter register CLK / TRG2. The interrupt based on the count-up of CH3 is performed by counting down the internal clock of the CPU and setting the register value to “0”.
And is used as a 2 ms timer interrupt described later. Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. In step S701e, a value corresponding to 2 ms is set as an initial value in the register of CH3. Note that the interrupt address for CH2 is 0074H,
The interrupt address for No. 3 is 0076H.

The payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S70).
2). That is, for example, the total number storage or the number-of-balls-to-be-stored (see FIG. 59) formed in the backup RAM area, which will be described later, is checked to determine whether there is any backup data relating to the number of unpaid prize balls and the number of the balls to be lent. Confirm. In the event of an unexpected power failure, in most cases, some data is stored in the backup RAM area, and the data in the backup RAM area should have been stored. Indicates that there is backup data. If the confirmation result indicates that there is no backup, it means that there were no unpaid game balls when the power was last turned off, and there is no need to return the internal state to the state when the power was turned off. (Step S702, step S702)
S703). In this example, whether or not backup data exists in the backup RAM area is confirmed by a backup flag set in the backup RAM area when the power is turned off.

If backup data exists in the backup RAM area, in this embodiment, the payout control CPU 371 performs data check (parity check in this example) of the backup RAM area (step S704). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the initialization processing executed when the power is turned on without the recovery from the power failure is executed (steps S705 and S703).

If the check result is normal, the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S706). Then, the PC saved in the backup RAM area
The process returns to the address indicated by the (program counter) (step S707).

Execution of normal initialization processing (step S70)
When 3) is obtained, the main process executed by the payout control CPU 371 starts the timer interrupt flag (step S
The processing shifts to the group processing in which the confirmation of 708) is performed.

Note that in this embodiment, step S7
After confirming the presence or absence of the backup data in 02, if the backup data exists, the backup area is checked in step S704. Conversely, it is confirmed that the check result of the backup area is normal. Thereafter, confirmation of the presence or absence of backup data may be performed. Further, it may be determined whether to execute the power failure recovery process by confirming whether there is backup data or checking the backup area.

Also, for example, a parity check for determining whether or not to execute the power failure recovery processing (step S7)
In the case of 04), that is, when determining whether or not to restore the gaming state, the gaming machine is in a payout standby state (a state in which the game is not being paid out) based on the number of payout game balls in the stored RAM data. Is confirmed,
The initialization process may be performed without performing the payout state restoration process.

In the normal initialization process, as shown in FIG. 57, the register and RAM are cleared (step S9).
01) is performed (step S902). Since the interrupt is prohibited in the initial setting process (step S701a), the interrupt is permitted before the initialization process is completed (step S903).

In this embodiment, the payout control CPU 3
The internal timer 71 (CH3) is set to repeatedly generate a timer interrupt. The repetition period is set to 2 ms. Then, as shown in FIG. 58, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711). In addition, 2ms
In the timer interrupt processing, if necessary, the initial value is reset in the register of CH3.

The payout control CPU 371 proceeds to step S7.
If it is detected at 08 that the timer interrupt flag has been set, the timer interrupt flag is reset (step S709), and a payout control process is executed (step S710). According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

At the time of power-on, the payout control CPU 371 can determine whether to perform the normal initialization processing or restore the payout state by merely checking the data in the backup RAM area. That is, the payout process can be restarted for the unpaid game balls by a simple determination.

In this example, the payout control CPU 371 is used.
Also, as in the case of the CPU 56 of the main board 31, the storage contents are reliably saved by parity check.

As described above, it is determined whether or not the power-off state is restored based on the presence or absence of the backup data, so that when the power is turned on when the power is restored after a power failure, for example. In addition, it is possible to determine whether or not to restore the power-off state according to the contents of the backup data storage area. Therefore, control based on backup data can be realized, and unnecessary execution of recovery processing can be prevented.

Further, as described above, the determination as to whether or not the power supply is restored to the dispensing state when the power is turned off is made based on the state of the backup data, so that when the power is turned on when the power is restored after a power failure or the like. Then, it is possible to determine whether or not to restore the power-off state according to the state of the contents of the backup data storage area. Therefore, control based on normal backup data can be realized, and execution of recovery processing based on backup data in which an error has occurred can be prevented.

FIG. 59 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a lending number storage are formed. The total number storage stores the insertion of the payout number specified from the main board 31 side. The lending ball number storage is for storing the unpaid ball lending number.

FIG. 60 is a flowchart showing a payout control command receiving process by the interrupt process. An INT signal for payout control from the main board 31 is supplied to a payout control CPU 371.
Is input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 is turned on, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 60 is started. In this embodiment,
A 12-byte fixed command buffer area for storing the received payout control command is provided. Then, a command reception number counter is used to indicate the storage position of the received payout control command. Since the payout command has a 2-byte configuration, it can be stored in a confirmed command buffer area of six payout control commands.

In the receiving process of the payout control command, the payout control CPU 371 first reads data from the input port 372a assigned to the input of the payout control command data (step S851). Then, it is checked whether or not the payout control command is the first byte of the payout control command having the 2-byte structure (step S852). Whether it is the first byte or not can be determined based on whether or not the first bit of the received command is “1”. The leading bit is "1", which should be the MODE byte (first byte) of the payout control command having the 2-byte structure (see FIG. 50). If the first bit is “1”, the first valid byte is held and the received command is mainly stored in the confirmed command buffer indicated by the command reception number counter in the confirmed command buffer area (step S853).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). The reception buffer (determined command buffer in step S853) determines whether or not it has already been received.
Can be confirmed by checking whether valid data is set in.

Next, when the second byte has already been received, it is confirmed whether or not the first bit of the received one byte is “0”. If the first bit is “0”, the valid second byte is received, and the received command is stored in the confirmed command buffer indicated by the command reception number counter + 1 in the confirmed command buffer area (step S855). The first bit is “0” because of the EX control of the 2-byte payout control command.
It should be T bytes (the second byte) (see FIG. 50).
If it is determined in step S854 that the first bit of the received one byte is not “0”, the process ends.

When the second byte of command data is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858).

FIG. 61 is a flowchart showing the payout control processing in step S710. In the payout control process, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 have been turned on (switch: step S751). ).

Next, the payout control CPU 371 checks the state of signal input from a sensor (for example, a motor position sensor for detecting the number of points between the payout motors 289) to determine the state of the sensor (input determination processing: Step S75
2). The payout control CPU 371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S753).

Next, the payout control CPU 371 sets the payout stop state in response to the payout stop instruction command received from the main board 31, or cancels the payout stop state in response to the received payout start instruction command (step). S
754). Further, a prepaid card unit control process is performed (step S755).

Also, the payout control CPU 371 performs control to pay out a lending ball in response to a ball lending request (step S75).
6). Further, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S757). And the payout control CPU 3
71 is a payout motor 2 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72.
A drive signal is output to the motor 89, and payout motor control processing is performed via the payout motor 289 for the number of revolutions set in the ball lending control processing in step S756 or the prize ball control processing in step S757 (step S758).

In this embodiment, the delivery motor 2
A stepping motor is used as 89, and a 1-2 layer excitation method is used to control the payout motor 289. Therefore, specifically, in the payout motor control processing, eight types of excitation pattern data are repeatedly output to the payout motor 289. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is made on error display LED 374 according to the result (error: step S759). For example, the following eight types of errors are detected.

Prize ball path error: Error display LED 374 when prize ball payout operation is completed, or when prize ball count switch 301A does not detect any passing of the game ball when payout motor 289 makes one rotation. Is displayed as "0".

Ball Lending Path Error: An error display is displayed when no ball lending count switch 301B detects passage of a game ball after the ball lending payout operation is completed or when the payout motor 289 makes one rotation. "1" for LED374
Is displayed.

Prize ball count switch ball jam error: When the prize ball count switch 301A detects ON for 0.5 seconds or more, “2” is displayed on the error display LED 374.

Ball Lending Count Switch Ball Jam Error: When the ball lending count switch 301B detects ON for at least 0.5 second, “3” is displayed on the error display LED 374.

Discharge motor ball biting error: Discharge motor 28
When 9 does not rotate normally. Specifically, when the payout motor position sensor has been on for a predetermined period or more or has been off for a predetermined period or more, “4” is displayed on the error display LED 374. Note that when a payout motor ball biting error occurs, the payout control CPU 371 sets the time to 50 ms.
, The reverse rotation and the forward rotation of the payout motor 289 are repeated by outputting four types of excitation pattern data of the excitation pattern data of the 1-2 layer excitation every 8 ms.

Prepaid card unit not connected error:
When the off of the VL signal is detected. Error display LED3
“5” is displayed at 74.

Prepaid card unit communication error: When it is detected that a signal has been output from prepaid card unit 50 at a timing other than the prescribed timing. Error display L
“6” is displayed on the ED 374.

[0280] Dispensing stop state: When a dispensing control command indicating dispensing stop is received from the main board 31. Error display LE
“7” is displayed in D374. When a payout control command indicating the start of payout is received from the main board 31,
After 2002 ms from that point, the state is returned from the payout stop state to the payout start state.

A process for controlling an information signal output from an external connection terminal (not shown) is performed (output process: step S
760). The information signal is a signal that is turned on for a predetermined period of time for each unit of payout of lending balls (for example, 25 pieces), and is subsequently output to be turned off for a predetermined period of time.

FIG. 62 is a flowchart showing an example of the switch processing in step S751. In the switch processing, the payout control CPU 371 checks whether or not the award ball count switch 301A indicates an ON state (step S751a). If it indicates the ON state, the payout control CPU 371 increments the winning ball count switch ON counter by one (step S751b). The award ball count switch on counter is a counter for counting the number of times that the on state of the award ball count switch 301A is detected.

Then, the value of the prize ball count switch on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. When determining that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number storage) (step S751d). .

If it is confirmed in step S751a that the prize ball count switch 301A is not on, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, the ball rental count switch 30
It is determined whether 1B indicates the ON state (step S751f). If the ON state is indicated, the payout control CPU 371 increments the ball lending count switch ON counter by one (step S751g). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B has been turned on.

Then, the value of the ball lending count switch on counter is checked (step S751h), and if the value is 2, it is determined that one ball lending has been paid out. When judging that one ball lending has been paid out, the payout control CPU 371 decrements the lending ball unpaid number counter (the number of lending balls stored in the lending ball number storage) (step S751i). ).

If it is confirmed in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

FIG. 63 is a flowchart showing an example of the command analysis execution processing in step S753. In the command analysis execution processing, the payout control CPU 371
It is checked whether there is a received command in the confirmed command buffer area (step S753a). If there is a received command, it is confirmed whether or not the received payout control command is a payout number instruction command (step S75).
3b). When there are a plurality of received commands in the confirmed command buffer area, whether or not the received payout control command is the payout number instruction command is checked for the received command received first.

If the received payout control command is a payout number instruction command, the number received by the payout number instruction command is added to the total number storage (step S753).
c). That is, the payout control CPU 371 is connected to the main board 3
The number is recorded in the award ball number backup RAM area (total number storage) included in the payout number instruction command sent from the first CPU 56.

It is to be noted that the payout control CPU 371 performs a command reception number counter decrement or a received command shift process in the confirmed command buffer area, if necessary.

FIG. 64 is a flowchart showing an example of the payout stop state setting process in step S754. In the payout stop state setting process, the payout control CPU 371
It is checked whether there is a received command in the fixed command buffer area (step S754a). If there is a received command in the confirmed command buffer area, it is checked whether the received payout control command is a payout stop instruction command (step S754b). If the command is the payout stop instruction command, the payout control CPU 371 sets the payout stop state (step S754c).

If it is determined in step S754b that the received command is not a payout stop instruction command, it is checked whether the received payout control command is a payout start instruction command (step S754d). If it is the payout start instruction command, the payout stop state is released (step S
754e).

FIG. 65 is a flowchart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not the VL signal input by the card unit control microcomputer has been detected (step S755a). If the VL signal has not been detected, the VL signal non-detection counter is incremented by 1 (step S755b). The payout control CPU 37
1 checks whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control C
The PU 371 stops outputting the emission control signal to the emission control board 91 and stops the drive motor 94 (Step S).
755d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) If the OFF of the VL signal is continuously detected, the ball firing prohibition state is set.

If a VL signal has been detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output of the firing control signal has been stopped (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to make the drive motor 94 operable (step S755g). .

FIGS. 66 and 67 are flowcharts showing an example of the ball lending control process of step 756. In this example, the maximum value of the number of consecutive payouts is set to one unit of the lending ball (in this example, 25), but may be another number.

In the ball lending control process, a payout control CPU
371 checks whether or not ball lending is being paid out (step S511). If ball lending is being paid out, the process proceeds to the ball lending process shown in FIG. 67. This determination is made as in the state of a ball lending process flag described later. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). This determination is made based on the state of a prize ball processing flag described later.

[0297] If neither a lending ball nor a prize ball is being paid out,
The payout control CPU 371 checks whether or not there has been a ball lending request from the card unit 50 (step S513),
If there is a request, the ball lending processing flag is turned on (step S514), and 25 (1 unit of ball lending: 100 yen in this case) is set in the ball lending number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S5).
16). And the ball distribution member 3 below the ball dispensing device 97
Distributing solenoid 310 to set 11 to the ball lending side
Is driven (step S517). The payout motor 2
89 is turned on (step S518), and the routine shifts to the ball lending process shown in FIG.

The reason why the payout motor 289 is turned on is as follows.
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the reception. Note that the ball lending process flag is set in the buffer RAM area.

FIG. 67 is a flow chart showing the ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not on, it is turned on. In this embodiment, in the switch processing in step S751, it is checked whether or not the game balls have been paid out based on the detection output of the ball lending count switch 301B. No subtraction is performed. In the ball lending control process,
The payout control CPU 371 checks whether or not it is during the waiting time for passing a ball (step S519). If it is not during the waiting time for passing the ball, the payout of the ball is carried out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be completed (whether the payout operation of one unit is completed) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522), and sets a waiting time for passing a ball (step S523).

[0300] In the ball lending process in step S520,
The on / off state of the payout motor position sensor is monitored by a timer. If the on state or the off state continues for a predetermined time or longer, the payout control CPU 371 determines that a payout motor ball biting error has occurred.

If it is during the waiting time for passing a ball at step S519, the payout control CPU 371 checks whether or not the waiting time for passing a ball is completed (step S52).
4). The ball passing wait time is determined by the ball lending count switch 3 after the last payout ball is paid out by the payout motor 289.
This is the time required to pass through 01B. When the end of the waiting time for passing a lending ball is confirmed, all lending lending balls have been paid out, and EXS is used to indicate to the card unit 50 that the next ball lending request can be accepted. The signal is turned off (step S524). Further, the distributing solenoid is turned off (step S525), the payout motor 289 is turned off (step S526), and the ball lending process flag is turned on (step S527). If the last payout ball has not passed through the ball lending count switch 301B before the ball passing waiting time has elapsed, a ball lending path error is determined. In this embodiment, the prize ball and the ball lending are performed by the same payout device.

When the ball lending request signal BRQ signal is turned on again within a predetermined time after the EXS signal is turned off to accept the ball lending request, the ball lending process is performed without turning off the sorting solenoid and the payout motor. It may be executed. That is, instead of performing the ball lending process every predetermined unit (100 yen unit in this example), the ball lending process may be performed continuously.

[0303] The content of the number-of-lending-item storage is retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the content of the ball lending number storage.

FIG. 68 and FIG. 69 are flowcharts showing an example of the winning ball control processing in step 757. In this example, the maximum value of the number of continuous payouts is the same as one unit of lending balls (in this example, 25), but may be another number.

In the prize ball control processing, the payout control CPU
The 371 checks whether or not the ball is being paid out (step S531). This determination is made based on the state of the ball lending processing flag. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S532),
If the prize ball is being paid out, the processing shifts to the processing during the prize ball shown in FIG. This determination is made based on the state of a prize ball processing flag described later.

[0306] If neither a lending ball nor a prize ball is being paid out,
The payout control CPU 371 checks whether there is a ball lending preparation request from the card unit 50 (step S).
533). This check is made by the payout control CPU 371.
Is performed by confirming whether the PRDY signal input from the card unit 50 is on (requested) or off (no request).

If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of award balls (number of unpaid award balls) stored in the total number memory is not zero. Performed (step S533). If the number of prize balls stored in the total number storage is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number storage is 25 or more in this example. It is confirmed whether or not this is the case (step S536). In addition,
The winning ball processing flag is set in the backup RAM area.

The number of award balls stored in the total number storage is 2
If the number is 5 or more, the payout control CPU 371 sets a 25-piece payout operation in order to output a drive signal to rotate the payout motor 289 until 25 prize balls are paid out (step S537). On the other hand, if the number of prize balls stored in the total number storage is not 25 or more, the payout control CP
The U371 sets the total number payout operation in order to output a drive signal to rotate the payout motor 289 until all game balls stored in the total number storage are paid out (step S538). Then, in accordance with the setting in step S537 or step S538, the payout motor 289
Is turned on (step S538). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the winning ball side. Then, the process shifts to a process during payout ball payout in the award ball control process shown in FIG. 69.

FIG. 69 is a flowchart showing an example of processing during a prize ball in the payout control processing by the payout control CPU 371. In the prize ball control processing, the payout motor 289
Turn on if is not on. In this embodiment, in the switch processing of step S751, it is checked whether or not the game balls have been paid out based on the detection output of the prize ball count switch 301A. Is not performed. In the processing during the prize ball, the payout control CPU 371 checks whether or not the prize ball passage waiting time is in progress (step S540).
If it is not during the waiting time for passing the prize ball, the prize ball is paid out (step S541), and the drive of the payout motor 289 should be terminated (in this example, whether or not a predetermined number of payout operations of 25 or less than 25 has been completed). (Step S5)
42). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets a prize ball passing waiting time (step S542). The prize ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 to when it passes through the prize ball count switch 301A.

On the other hand, if it is during the waiting time for passing a prize ball by looking at step S540, the payout control CPU 371 checks whether or not the waiting time for passing a prize ball has ended (step S544). When the end of the waiting time for passing a lending ball is confirmed, since all the prize balls set in step S537 or step S538 have been paid out, the payout motor 28
9 is turned off (step S544), and a winning ball processing flag is turned on (step S546). If the last payout ball has not passed through the prize ball count switch 301A before the prize ball passage waiting time elapses, it is determined that a prize ball path error has occurred.

Also, in this embodiment, step S5
11, the ball lending is given priority over the prize ball processing by the determination in step S531, but the prize ball processing may be given priority over the ball lending.

[0312] The contents of the total number storage and the number-of-lenders storage are such that even if the power of the gaming machine is cut off,
Saved by backup power. Therefore,
When the power supply is restored during the predetermined period, the payout control CPU 37
1 can continue the payout process based on the contents of the total number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but for each prize ball number (for example, 15, 10 or more).
5). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the payout corresponding to the number counter is performed, the number counter is decremented by one (in this case, the subtraction processing is performed in the payout control processing). Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the payout control CP
U371 can continue the prize ball payout process based on the content of each number counter.

FIG. 70 is a flowchart showing an example of the process of the power failure occurrence NMI executed by the power supply monitoring circuit of the power supply board 910 in response to the NMI based on the voltage change signal. In this embodiment, the NMI interrupt address is 00
66H. In the power failure occurrence NMI process, the payout control CPU 371 first stores the contents of the interrupt prohibition flag in the parity flag (step S801). Then
The interrupt is prohibited (step S802). Power failure occurred N
In the MI process, in this example, as in the process executed on the main board 31, a process of generating a checksum for ensuring the storage of the RAM contents is performed. If another interrupt process is performed during that process, the voltage may drop to a level at which the payout control CPU 371 cannot operate before the checksum generation process is completed.
The setting is made so that no other interrupt occurs. Steps S804 to S810 in the power failure occurrence NMI process
Is an example of a process when the power supply is stopped.

[0315] If a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the processing in step S802 is unnecessary.

Next, the payout control CPU 371 checks whether or not the backup flag has already been set (step S803). If the backup flag has already been set, no further processing is performed. If the backup flag is not set, the following power supply stop processing is executed. That is, the processing from step S804 to step S810 is executed.

First, the contents of each register are backed up by R
It is stored in the AM area (step S804). After that, a backup flag is set (step S805).
Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S80).
6) The exclusive value is sequentially ORed with respect to the initial value and the data in the backup RAM area, and the determination is made (step S).
807), the final operation value is set in the backup parity data area (step S808). Also, RAM
The access is prohibited (step S809). Further, all output ports are turned off (step S
810). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Next, the payout control CPU 371 enters a loop process. That is, no processing is performed. Therefore, the reset IC 976 shown in FIG.
Before the operation is disabled from the outside by the system reset signal from the CPU, the operation is stopped internally. Therefore, the payout control CPU 371 surely stops operating when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

In this embodiment, the power failure occurrence NM
In the I processing, the program is set in a loop state at the last part, but a HALT instruction may be issued.

The backup flag set after storing the contents of the register in the RAM area indicates whether there is backup data to be restored at power-on as described above (whether or not to recover from a power failure). Used to judge again. Further, the processing of steps S801 to S810 is completed before the payout control CPU 371 receives the system reset signal from the system reset circuit 975. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 975.

In this embodiment, the backup flag is checked at the start of the power supply stop processing. If the backup flag has already been set, the power supply stop processing is not executed. As described above, the backup flag is a flag indicating that the backup of necessary data has been completed and then the power supply stop processing has been completed. Therefore, for example, even if the side NMI occurs for some reason in the reset waiting loop state, the power supply stop processing is not repeatedly executed.

However, in the case where a CPU having a specification that does not cause another interrupt during the interrupt processing is used, the determination in step S803 is unnecessary.

In this embodiment, the payout control C
PU 371 is a non-maskable external interrupt terminal (NMI terminal)
, The NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) is detected, but the NMI interrupt signal may be introduced to a maskable interrupt terminal (IRQ terminal). In that case, the power failure occurrence NMI process shown in FIG. 70 is executed by the IRQ process. Further, an NMI interrupt signal may be detected through an input port. In that case, the input port is monitored in the main processing executed by the payout control CPU 371.

FIG. 71 is an explanatory diagram for explaining an example of a backup parity data creating method. However,
In the example shown in FIG. 71, for simplicity, the data size of the backup data RAM area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 71, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, parity diagnosis is performed in the power failure restoration processing. If all the data in the backup area is stored as it is, the data as shown in FIG. 71 is set in the backup area when the power is turned on again.

In the processing of step S704, the payout control CPU 371 performs the same processing as the processing executed in steps S806 and S807 in FIG. That is, in the backup check data area,
Initial data (00H in this example) is set, and “00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, as a result, the exclusive OR of “DFH” is obtained. Then, a final operation result obtained by inverting the result (“39H” in this example) is obtained. If all data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error occurs in the data in the backup RAM area, the final calculation result does not become “C6H”.

[0327] Therefore, the payout control CPU 371 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the payout control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the gaming machine is turned off. At the time of insertion, payout control CPU
371 (specifically, a program executed by the payout control CPU 371) is configured to perform a payout state recovery process (step S706) for recovering the payout state based on the backup data if the storage unit is in the backup state. .

Hereinafter, the payout recovery processing will be described. FIG. 72 is a flowchart showing an example of the payout state restoring process shown in step S706 of FIG. In this example, the payout control CPU 371 restores the value stored in the backup RAM to the register (step S8).
61). Then, based on the data stored in the backup RAM, a process for recovering the payout state at the time of the power failure is performed. For example, a flag during processing of a prize ball is set.

When the payout state is restored, in this embodiment, the payout control CPU 371 returns to the backup RA to restore the interrupt permission / prohibition state at the time of the previous power-off.
The value of the parity flag stored in M is checked (step S862). If the parity flag is clear,
An interrupt permission setting is performed (step S863). On the other hand, if the parity flag is on, the process proceeds to step S7.
The payout state restoring process ends (with the interrupt prohibition state set in 01a).

Here, the payout state restoring processing program is configured to return to the payout control main processing when the payout state restoring processing is completed. Stack area (in the backup RAM area)
(The address executed when the NMI interrupt occurs when the power is turned off).

As described above, after the initial setting process is started and before the payout state restoring process is completed, or until the initialization process is completed, the interrupt is prohibited. Can prevent the processing from being interrupted, the initialization, the determination as to whether or not to recover to the power-off power-off state performed according to the contents of the backup data storage area, and the recovery processing (or initial processing) Process) can be surely completed. Even in the case where the interrupt prohibition state is set before the end of the recovery processing as described above, the interrupt prohibition / permission state at the time of power-off is backed up by the parity flag. The interrupt prohibition / permission state when the power is turned off can be reliably restored.

FIG. 73 is a timing chart showing the state of the power supply drop when the power of the gaming machine is turned off and the state of the NMI interrupt signal (here, the power-off signal). When the power supply to the gaming machine is cut off, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. In this example, when the voltage drops to +22 V, the power supply monitoring CI mounted on the power supply board 910 is operated.
A power-off signal (voltage drop signal) is output from 902 (becomes low level).

The power-off signal is supplied to the electric component control board (FIG. 73).
In the example shown in FIG. 5, the CPU 56 and the payout control CPU 371 are installed on the main board 31 and the payout control board 37).
Input to MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop processing by the NNMI processing described above.

When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the reset IC 651 mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 and the CPU 56 Dispensing control C
PU 371 enters a system reset state. Note that CP
The U56 and the payout control CPU 371 have completed the power supply stop processing before the system is reset.

If the voltage value of VSL further drops below a voltage at which Vcc (+5 V for driving various circuits) can be generated, various circuits cannot operate on each substrate. However, at least in the main board 31 and the payout control board 37, the process at the time of stopping the power supply is executed,
U56 and the payout control CPU 371 are in the system reset state.

The predetermined value for the reset IC 976 to detect a power-off is lower than the normal voltage at which the CPU 371 operates, but is a voltage at which the payout control CPU 371 can operate for a while. Also, reset IC 976
Is monitored to monitor a voltage higher than the voltage required by the payout control CPU 371 (+5 V in this example), so that the monitoring range for the voltage required by the payout control CPU 371 can be expanded. . Therefore, more precise monitoring can be performed.

In this embodiment, the power supply board 91
The power supply monitoring circuit mounted on 0 monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine,
When the voltage of the power supply falls below a predetermined value, a voltage drop signal (power-off detection signal) is generated. As shown in FIG. 73, at the timing output from the power-off detection signal, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, the operation time for the payout control CPU 371 of the payout control board 37 operating at the IC drive voltage to perform the predetermined power supply stop processing is secured.

Note that the power supply monitoring circuit also monitors the highest voltage of the power supply VSL among the DC voltages used in the game machine. The monitoring target voltage may not be the highest voltage of the power supply VSL as long as the operation time for the electric component control means operating at the voltage to perform the predetermined power supply stop processing is secured. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off detection signal is generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. Can be.

In this case, as described above, since the voltage to be monitored is +12 V supplied to various switches of the gaming machine such as the prize ball count switch 301A, it is possible to prevent erroneous switch-on detection when the power is turned off. It is preferable that the voltage is also expected. That is, it is desirable that the voltage drop can be detected before the + 12V power supply voltage, which is the voltage (switch voltage) supplied to the switch, starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the voltage monitoring circuit and other voltage monitoring circuits. Also in that case, the detection potential of the voltage monitoring circuit is set higher than the detection potentials of the other voltage monitoring circuits.

As described above, it is determined whether or not the power is restored to the state at the time of power failure based on the presence or absence of the backup data. It is possible to determine whether or not the data is restored to the power-off data according to the contents of the data storage area. Therefore, control based on backup data can be realized,
Unnecessary execution of the recovery process can be prevented.

Also, as described above, whether or not the power is restored to the state at the time of power failure is determined based on the state of the backup data. It is possible to determine whether or not to restore the power-off state according to the data of the contents of the backup data storage area. Therefore, control based on normal backup data can be realized, and execution of recovery processing based on backup data in which an error has occurred can be prevented.

[0344] As described above, the values from the start of the initial setting process to the end of the recovery process and before the end of the initial process (during the initial preparation process) are set to the interrupt prohibition state. With this configuration, it is possible to prevent the processing from being interrupted, so that it is possible to initialize or not to be restored to the power-off state performed according to the contents in the backup data storage area. And the restoration process (or the initialization process) can be surely completed. Even in the case where the interrupt prohibition state is set before the above-described recovery processing is completed, the interrupt prohibition / permission state at the time of power-off is backed up by the parity flag. Prohibition of interrupt when power is turned off /
The permission state can be reliably restored. in this case,
The process included in the initial preparation process is an example,
The initial preparation process may be a part of the above-described process, for example, a process from monitoring the initial setting process to determining whether or not to perform restoration based on the backup data.

In each of the above-described embodiments, the power supply monitoring means is provided on either the power supply board or the electric component control board. It can be installed at any position as needed.

In each of the above embodiments, a case was described in which a RAM was used as the storage means. However, any other storage means than the RAM may be used as long as it is an electrically rewritable storage means. Good.

Also, in each of the above-described embodiments, the payout control means has been described as an electric component control means other than the game control means, but the display control means, the voice control means, and the lamp control means are also controlled as described above. May be performed.

In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910.
It may be provided on an electric component control board such as the main board 31 or the payout board 37. When the electric component control board on which the power supply circuit is mounted is configured, the power supply monitoring circuit is not mounted on the power supply board.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-type pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a winning start is combined with a predetermined symbol. However, if there is a prize in a predetermined area of an electric accessory that is opened based on a winning start, a second-type pachinko gaming machine in which a predetermined game value can be given to a player, and a symbol variably displayed based on a starting prize The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize to a predetermined electric auditors product which is opened when the stop symbol becomes a predetermined combination of symbols.

Further, regardless of the pachinko gaming machine, even in a slot gaming machine, when power is turned off by turning on the power, data immediately before the power is turned off is stored in a backup RAM or the like,
The present invention can be applied to a case where control restart processing based on stored data is performed when power is restored. For example, when applied to a slot machine, it is possible to restore an internal flag (flag of big, regular, small role, etc.) or a state of being big.

The power monitoring means sends out a signal when the voltage becomes equal to or lower than a predetermined value, but may output a signal when the voltage becomes equal to or higher than a predetermined value. As a result, it is possible to prevent electric circuits such as ICs from being damaged and to prevent waste of power consumption.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0353]

According to the first aspect of the present invention, electric power is supplied to the second electric component control means via the first electric component control means. It is not necessary to provide a connector for connecting the power supply means and the second electric component control means to the power supply means. Thereby, the number of connectors provided in the power supply means can be reduced, so that the structure of the power supply means is simplified.

According to the present invention described in claim 2, the following effects are obtained in addition to the effects of the invention described in claim 1. In the present invention, the first electric component control means includes a game control means for controlling a game, and the second electric component control means changes an image based on an electric signal output from the game control means. A display control means for controlling the variable display means to be displayed is included. Therefore, it is not necessary to provide a connector for connecting the power supply unit and the display control unit to the power supply unit. As a result, when the variable display means and the display control means are no longer required due to the model change, there is no longer any unconnected connector in the power generation means. As a result, there is no danger that information for performing unauthorized control is input from the unconnected connector of the power generation unit, which is caused by the presence of the unconnected connector. Therefore, it is possible to adopt a structure in which unauthorized control caused by a model change is prevented in advance.

According to the third aspect of the present invention, in addition to the effects of the first or second aspect, the second electric component control means controls the electric power required for controlling the electric components. Since the power generating means is provided, it is not necessary to provide an external power generating means for generating power required for the second electric component control means.

According to the present invention described in claim 4, in addition to the effects of the invention described in any one of claims 1 to 3,
Central processing means for performing calculations necessary for controlling the electric components, and monitoring the power supplied from the power supply means, and executing or executing the processing operation of the central processing means according to the state of the supplied power. Since the system includes a system reset unit that outputs an electric signal that can be stopped, the electric component control unit performs a system reset independently, thereby preventing the central processing unit from performing a kure operation during a power failure or the like. It becomes possible to do.

According to the present invention described in claim 5, in addition to the effects of the invention described in any of claims 1 to 4,
Since the power supply means directly supplies necessary power to the value provision control means for performing control for providing a game value by satisfying predetermined conditions according to the progress of the game, the first electric component control means performs value provision control. There is no need to provide a terminal or the like for supplying power to the means. As a result, the structure of the first electric component control means is simplified.

According to the sixth aspect of the present invention, the following effects are produced in addition to the effects of the fourth or fifth aspect of the present invention. In the present invention, since the power supply means starts supplying power to the plurality of electric component control means, the electric component control means including the central processing means among the electric component control means excluding the game control means operates. After that, control of other electric component control means by the game control means becomes possible. Therefore, by starting the game control means before the electric component control means including the central processing means, it is possible to prevent the occurrence of an undesired phenomenon such that the electric component control means including the central processing means malfunctions. Can be.

According to a seventh aspect of the present invention, in addition to the effect of the sixth aspect of the present invention, the system reset means outputs an instruction to execute the arithmetic processing operation of the central processing means constituting the game control means. Since the control means of the game control means outputs the control command, the control means to be output is not operating at the time when the control processing means outputs the control command. Can be prevented.

According to the present invention described in claim 8, in addition to the effects of the invention described in any of claims 1 to 7,
The following effects are produced. In the present invention, the power supply means includes a power supply monitoring means capable of monitoring a predetermined potential power supply and outputting a predetermined signal when a predetermined condition is satisfied. At least one of them performs power supply stop processing in response to input of a predetermined signal. Therefore, setting to monitor the wasteful consumption of power can reduce the power charge, and before a complete power failure in the event of a power outage,
It is also possible to set so as to execute a power failure process such as data creation for checking data corruption at the time of power restoration.

According to the ninth aspect of the present invention, in addition to the effects of the first to eighth aspects,
The following effects are produced. In the present invention, the electric power supply means controls the electric component to one of the plurality of electric component control means, when the electric power is not supplied, to the electric component control means for which the supply of the electric power is stopped. Other power supply means for supplying power required to store information related to control is included. Therefore, if the predetermined condition monitored by the power monitoring means is set to be equal to or less than the voltage value for performing the process at the time of the power failure, information on control of the electric components at the time of the power failure is stored by using another power supply means. Electric power for keeping the power can be supplied.

According to the tenth aspect of the present invention, in addition to the effects of the eighth aspect of the present invention, the power supplied from the predetermined potential power source satisfies the satisfaction of the predetermined condition. Of the power supplied from the predetermined potential power supply at the time of a power failure has become lower than or equal to the predetermined value. Can be supplied. As a result, a backup power supply at the time of a power failure can be supplied.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine.

FIG. 2 is a rear view of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming machine showing a configuration around the mechanical panel.

FIG. 4 is a block diagram showing a circuit configuration of the game control board.

FIG. 5 is a block diagram showing a circuit configuration of a display control board.

FIG. 6 is a block diagram illustrating a circuit configuration of a voice control board.

FIG. 7 is a block diagram illustrating a circuit configuration of a lamp control board.

FIG. 8 is a block diagram showing components related to a winning ball control board.

FIG. 9 is a diagram showing the periphery of a power supply board.

FIG. 10 is a diagram showing a board of an audio control system.

FIG. 11 is a diagram showing an electric circuit in the vicinity of a power supply port inside the audio control board.

FIG. 12 is a diagram showing an electric circuit around a buffer circuit inside the audio control board.

FIG. 13 is a diagram showing an electric circuit around an audio control CPU inside the audio control board.

FIG. 14 is a diagram showing an electric circuit around a voice synthesis IC and a voice data ROM inside the voice control board.

FIG. 15 is a diagram showing an electric circuit around an audio switching circuit and an audio amplifier circuit inside the audio control board.

FIG. 16 is a diagram showing a substrate of a display control system.

FIG. 17 is a diagram showing an electric circuit in the vicinity of a power supply port inside the display control board.

FIG. 18 is a diagram showing an electric circuit around a buffer circuit inside the display control board.

FIG. 19 is a diagram showing an electric circuit around a display control CPU inside a display control board.

FIG. 20 shows display control data RO inside a display control board.
It is a figure showing an electric circuit of M circumference.

FIG. 21 is a diagram showing an electric circuit around a crystal oscillator inside a display control board.

FIG. 22 is a diagram showing an electric circuit around a crystal oscillator inside a display control board.

FIG. 23 is a diagram showing an electric circuit around a reset circuit inside the display control board.

FIG. 24 is a diagram showing an electric circuit around a VDP inside the display control board.

FIG. 25 is a diagram showing an electric circuit around a VRAM and a character ROM inside the display control board.

FIG. 26 is a diagram illustrating a case where a transistor inside a display control substrate is connected to C
FIG. 3 is a diagram showing an electric circuit up to RT.

FIG. 27 is a diagram showing a lamp control board.

FIG. 28 is a diagram showing a board connected to a lamp relay board and a lamp relay A board.

FIG. 29 is a diagram showing a frame lamp relay A substrate and a substrate connected to the frame lamp relay A substrate.

FIG. 30 is a diagram showing an electric circuit in the vicinity of a power supply port inside the lamp control board.

FIG. 31 is a diagram showing an electric circuit structure around a buffer circuit inside the lamp control board.

FIG. 32 is a diagram showing an electric circuit structure around a CPU inside the lamp control board.

FIG. 33 is a diagram showing a part of a wiring for outputting a signal from the lamp control board to the lamp relay board.

FIG. 34 is a diagram illustrating a part of a wiring for outputting a signal from the lamp control board to the frame lamp relay A board;

FIG. 35 is a diagram showing a part of a wiring for outputting a signal from the lamp control board to the lamp relay board.

FIG. 36 is a diagram showing a part of a wiring for outputting a signal from the lamp control board to the lamp relay board.

FIG. 37 is a block diagram showing another example of the display control board.

FIG. 38 is a diagram showing the periphery of a power supply input circuit on a main board.

FIG. 39 is a block diagram illustrating a configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 40 is a block diagram illustrating a configuration example of a power supply board.

FIG. 41 is a flowchart illustrating an example of main processing executed by a CPU on a main board.

FIG. 42 is an explanatory diagram showing an example of a method for determining whether or not to execute a game state restoration process.

FIG. 43 is a flowchart illustrating an example of an initialization process.

FIG. 44 is a flowchart illustrating an example of a 2 ms timer interrupt process.

FIG. 45 is a flowchart illustrating an example of an initial setting process.

FIG. 46 is a flowchart illustrating an example of a game control process.

FIG. 47 is a flowchart illustrating an example of a power failure occurrence NMI process.

FIG. 48 is an explanatory diagram for describing an example of a backup parity data creation method.

FIG. 49 is a flowchart illustrating an example of a game state restoration process.

FIG. 50 is an explanatory diagram showing an example of a command form of a payout control command.

FIG. 51 is an explanatory diagram showing an example of the content of a payout command.

FIG. 52 is a timing chart showing another example of the delivery mode of the payout control command.

FIG. 53 is a timing chart showing an example of a delivery mode of a payout control command.

FIG. 54 is a block diagram illustrating a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 55 is a flowchart illustrating an example of main processing executed by a payout control CPU.

FIG. 56 is a flowchart illustrating an example of an initial setting process of a payout control CPU;

FIG. 57 is a flowchart illustrating an example of initialization processing of a payout control CPU;

FIG. 58 is a flowchart illustrating an example of initialization processing of a payout control CPU;

FIG. 59 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 60 is a flowchart illustrating an example of a command receiving process of the payout control CPU.

FIG. 61 is a flowchart illustrating an example of a payout control process executed by a payout control CPU.

FIG. 62 is a flowchart illustrating an example of a switch process.

FIG. 63 is a flowchart illustrating an example of a command analysis execution process.

FIG. 64 is a flowchart illustrating an example of a payout stop state setting process.

FIG. 65 is a flowchart showing an example of a prepaid card unit control process.

FIG. 66 is a flowchart illustrating an example of a ball lending control process.

FIG. 67 is a flowchart illustrating an example of a ball lending control process.

FIG. 68 is a flowchart illustrating an example of a winning ball control process.

FIG. 69 is a flowchart illustrating an example of a winning ball control process.

FIG. 70 A power outage occurrence NM executed by the payout control CPU
It is a flowchart which shows the example of I processing.

FIG. 71 is an explanatory diagram for describing an example of a backup parity data creating method;

FIG. 72 is a flowchart illustrating an example of a payout recovery process executed by a payout control CPU.

FIG. 73 is a timing chart showing an example of the state of a power supply drop and an NMI signal when the power of the gaming machine is turned off.

[Explanation of symbols]

27 Speaker, 28b, 28c Game effect lamp, 3
1 main board, 35 lamp control board, 37 payout control board, 53 basic circuit, 56 CPU, 65 system reset circuit, 70 audio control board, 80 display control board, 82 CRT, 91 launch control board, 97 ball payout apparatus, 101 Display control CPU, 371 payout control C
PU, 109 switching regulator, 280 LC
D, 652 Capacitor, 902 Power supply monitoring IC, 9
10 Power supply board, 902 Power supply monitoring IC, 916 Capacitor to be backup power supply, 977 capacitor.

Claims (10)

[Claims] 1. A plurality of electric components that operate with supplied power, power supply means capable of generating power required in a game machine using power supplied from the outside, and power supplied from the power supply means. A plurality of electric component control means for controlling each of the plurality of electric components based on electric power, wherein the plurality of electric component control means is configured to firstly receive necessary electric power from the electric power supply means.
A gaming machine, comprising: an electric component control unit; and a second electric component control unit to which power is supplied via the first electric component control unit. 2. The first electric component control means includes a game control means for controlling a game, and the second electric component control means is based on an electric signal output from the game control means. The gaming machine according to claim 1, further comprising display control means for controlling variable display means for variably displaying an image. 3. The gaming machine according to claim 1, wherein said second electric component control means has a power generation means for generating electric power required for controlling the electric components. 4. At least one of the plurality of electric component control means includes a central processing unit that performs an operation necessary for controlling the electric component, and monitors power supplied from the power supply means. The system according to claim 1, further comprising: a system reset unit that outputs an electric signal capable of executing or stopping an arithmetic processing operation of the central arithmetic processing unit according to a state of supplied power. A gaming machine according to any of the above. 5. The power supply means directly supplies necessary power to value provision control means for performing control for providing a game value by satisfying predetermined conditions according to the progress of a game. Item 6. A gaming machine according to any one of Items 4. 6. The electric component including the central processing unit among the electric component control units other than the game control unit, as the electric power supply unit starts supplying electric power to the plurality of electric component control units. The gaming machine according to claim 4 or 5, wherein after the control means becomes operable, control of another electric component control means by the game control means becomes possible. 7. The system according to claim 6, further comprising a delay unit for delaying an electric signal output from the system reset unit for a predetermined time in order to execute an arithmetic processing operation of a central processing unit constituting the game control unit. Gaming machine. 8. The power supply control unit includes a power supply monitoring unit that monitors a predetermined potential power supply and outputs a predetermined signal when a predetermined condition is satisfied. The gaming machine according to any one of claims 1 to 7, wherein at least one of the means performs power supply stop processing in response to the input of the predetermined signal. 9. The power supply means is required to store information related to control of an electric component in at least one of the plurality of electric component control means when power is not supplied. The gaming machine according to any one of claims 1 to 8, further comprising another power supply means capable of supplying an appropriate power. 10. The gaming machine according to claim 8, wherein the case where the predetermined condition is satisfied is a case where a voltage of power supplied from a predetermined potential power supply has reached a predetermined value.