JP2001246061A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can delete data of which is memory-held by a backup power source. SOLUTION: A switch SW1 is connected to the middle of a backup power source supplying line L1a in cables which electrically connect a power source board 80 and a main board 100. When the switch SW1, which is normally closed (turned ON) for the supply of a backup power source, is opened (turned OFF), the backup power source, which is fed from a capacitor provided on the power source board 80 to a power source terminal VBB for the backing up of a built-in RAM of a micro-processor 110, is shut off, and data which is backed up in a RAM 116 is deleted. Thus, data or the like such as various kinds of control commands to indicate a game state when the power source is shut off, being backed up (memory-held) in the RAM 116 can be deleted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine controlled by a computer, such as a pachinko machine and a slot machine.

[0002]

2. Description of the Related Art Conventionally, as this type of gaming machine, for example, a pachinko machine shown in FIGS. 18 and 19 is known.
FIG. 18 is an explanatory front view of a conventional pachinko machine.
FIG. 19 is an explanatory view of the back set of the pachinko machine shown in FIG.
As shown in FIG. 18, a conventional pachinko machine 500 stores a game board 502, a firing device 504 for firing game balls to a game area of the game board 502, and game balls to be supplied to the firing device 504. An upper tray 506 and a lower tray 508 for storing game balls that cannot be completely stored in the upper tray 506 are provided. In addition, on the game board 502, a special symbol display device 524, a prize winning opening 510, a right sleeve winning opening 512, a left sleeve winning opening 514, a first kind starting opening 516, a lower right winning opening 518, The lower left winning opening 520,
A special winning opening 526 is provided. Then, when the game ball fired from the firing device 504 wins the first kind starting port 516, the special symbol display device 524 displays the symbols in a fluctuating manner, and the stopped symbols are aligned with a predetermined symbol (for example, 777). A big hit occurs, and the special winning opening 526 is opened for a predetermined time. Then, when the opening time of the special winning opening 526 reaches a predetermined time or when the number of winnings to the special winning opening 526 reaches a predetermined number, the special winning opening 526 is closed. At this time, when a winning ball that has won the special winning opening 526 passes through a specific area 528 provided inside the special winning opening 526, the special winning opening 526 is continuously opened. In this manner, a predetermined number of rounds (for example, 16 rounds) can be played on the condition that the game ball passes through the specific area 528, with the round from opening to closing of the special winning opening 526 being one round.

[0003] Further, as shown in FIG.
In the back set of No. 0, a back set mechanism plate 530 is provided, and a winning prize port 510, a right sleeve prize port 512, a left sleeve prize port 514, a first kind starting port 516, a lower right prize port 518, and a lower left prize port are provided. The winning ball that wins the mouth 520 etc. is the back ball passage 5
At 32, it flows down along the path shown by the arrow in the figure, gathers in the winning ball collecting gutter 524, and is guided to the winning ball detection switch 522. When the winning ball detection switch 522 detects a winning ball, a predetermined number of winning balls are paid out by a winning ball payout device (not shown). The winning balls detected by the winning ball detection switch 522 are discharged downward one by one by operating the winning ball cutting solenoid 534 each time the predetermined number of the winning balls are paid out.

[0004]

However, the conventional pachinko machine requires a structure such as a winning ball collecting gutter 524 and a winning ball cutting solenoid 534, so that the structure of the back set of the pachinko machine is complicated. Therefore, there has been a problem that the manufacturing efficiency is poor and it is difficult to save space. Further, since the winning ball cutting solenoid 534 frequently repeats the operation of discharging the winning balls one by one, there is also a problem that a failure due to abrasion or breakage of the operating portion is common. Further, the manufacturing cost of the above-mentioned structure is a factor that increases the manufacturing cost of the entire pachinko machine, which hinders the reduction of the manufacturing cost of the pachinko machine. Therefore, the present inventor has considered a configuration in which the number of winning balls and the number of winning balls are electrically stored in association with each other. According to this configuration, since the above-mentioned structure is unnecessary, the above-mentioned problems can be solved. However, the memorized number of winnings is lost due to power interruption or voltage drop, so even if power is restored, it is not possible to pay out the prize balls that should be paid out, which may be disadvantageous to the player. It turned out that there was. Therefore, the present inventor has considered a configuration in which a backup power supply is provided for holding a memory of the winning number when the power supply is cut off or the power supply voltage is reduced.

[0005] Further, if the power is cut off during the game due to a power failure or the like, when the power is restored, the game cannot be resumed from the game state at the time of the power cut, so that the player feels uncomfortable. In particular, when the power is cut off during a round based on a big hit or when the special symbol display device 524 variably displays the special symbol, the power supply is restarted from the middle of the round after the power is restored, or the special symbol is changed. Since the game cannot be restarted from the beginning, there is a risk that the player will be disadvantaged. Therefore,
The present inventor has considered a configuration in which a backup power supply for retaining storage of data for controlling a game is provided when the power supply is cut off or the power supply voltage decreases.

However, if the stored prize balls or winning spheres are rewritten due to static noise or fraudulent behavior, the power is cut off to erase the rewritten data. It turned out that the rewritten data could not be erased because the backup function worked. In addition, a jackpot may occur when a pachinko machine is tested and the final adjustment is performed before the pachinko hall is opened. In this case, prize ball data for paying out a predetermined number of prize balls is stored in the RAM. You. Therefore,
If the store is opened in such a state, a predetermined number of prize balls are paid out based on the memory in the RAM, and thus it has been found that the store may be disadvantaged. Furthermore, if the control data generated during the trial shooting before the store is opened is backed up, when the player plays the game at the time of opening the store, the game is started based on the backed up control data, which makes the player feel uncomfortable. There was a risk of learning.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to realize a gaming machine capable of erasing data stored in memory by a backup power supply.

[0008]

In order to achieve the above object, according to the present invention, a control means for controlling a game and data generated during the game are stored. Storage means for storing the storage of the storage means by supplying power to the storage means when the voltage of the drive power supply supplied to the gaming machine drops to a predetermined voltage; Means, wherein the control means is a gaming machine capable of controlling a game by referring to data stored and held by the storage and holding means, wherein a switch capable of shutting off supply of power for the storage and holding is provided. Technical means of having means are used.

That is, since the supply of the power for storing data can be cut off by the switching device, the data stored and stored in the storing device can be erased. For example, data generated during a game, for example, data relating to payout of prize balls (prize media) is stored in a storage means, and a pachinko machine (game machine) which pays out prize balls by referring to the stored data. In some cases, stored data may be rewritten due to static electricity noise or fraudulent activity. Even if such data is rewritten, the data is backed up (stored and held) in the storage means by the switch means. Since the stored data can be erased, loss of the pachinko hall (game store) due to data rewriting can be minimized. Further, even if data related to the payout of prize balls (prize media) at the time of trial shooting before the opening of the pachinko hall is backed up (stored and held) in the storage means, the backed up data is switched by the switch means. Since the data can be erased, there is no possibility that the store side suffers a disadvantage due to the prize balls being paid out based on the backed up data. Furthermore, even if the control data for controlling the game that occurred during the trial shooting before opening the store is backed up, the backed up control data can be erased by the switch means, so that the player can When playing a game, the game is started based on the backed-up control data, and the player does not feel uncomfortable.

According to a second aspect of the present invention, in the gaming machine according to the first aspect, the switch means operates when the drive power is turned on, and shuts off the power supply for holding the memory. Use technical measures.

That is, when the driving power of the gaming machine is turned on, the switch means operates to cut off the power supply for holding the memory, thereby erasing the data backed up (held) by the memory means. For example, when the drive power of each pachinko machine (game machine) is turned on when the power of the pachinko hall (game machine) is turned on, a simple operation of simply turning on the power of the pachinko hall at the time of opening the shop is performed. The data stored in the storage means of each pachinko machine can be erased. Therefore, even when busy preparing for the opening of the store, the data stored in each pachinko machine can be easily and quickly erased, which is convenient.

According to a third aspect of the present invention, in the gaming machine according to the first or second aspect, the switch means operates when the voltage of the drive power supply drops to a predetermined voltage, and stores the data. The technical means of shutting off the power supply for holding is used.

That is, when the drive power supply drops to a predetermined voltage, the data stored in the storage means is backed up (stored and held) by the storage holding means. To block, the backed up data can be erased. Therefore, by shutting off the drive power supply when closing stores,
Data backed up in the storage means of each gaming machine can be deleted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a gaming machine according to the present invention will be described below with reference to the drawings. In the following embodiments, a so-called first class pachinko machine will be described as an example of a gaming machine according to the present invention. First Embodiment [Overall Main Configuration] First, a main configuration of a pachinko machine according to the first embodiment will be described with reference to FIG. FIG. 1 is an explanatory diagram of the pachinko machine according to the first embodiment as viewed from the front. The pachinko machine 10 is provided with a front frame 11 so as to be openable and closable. A metal frame 12 is attached to the front frame 11 so as to be openable and closable. Mounted on Glass frame 1
A game board 14 is provided in the inside of 3. Front frame 11
A firing handle 15a for operating a firing motor (indicated by reference numeral 15e in FIG. 3) for firing a game ball to the game board 14 is rotatably attached to the lower right of the shooting handle 15a. A firing stop button 15b for stopping the firing operation is provided. On the left side of the game board 14, a guide rail 16 for guiding the shot game balls to the game area.
Is provided.

On the right side of the front frame 11, there is provided a keyhole decoration 17 having a keyhole 15 into which a key for opening and closing the glass frame 13 is inserted. Above the front frame 11, a frame lamp 18a is provided. A front plate 19 is provided under the glass frame 13, and a prize ball / lending ball supply port 20a to which a prize ball or a lending ball is supplied is formed on an upper left portion of the front plate 19, On the supply side of the prize ball / lending ball supply port 20a, an upper receiving tray 20 for storing prize balls or lending balls supplied from the prize ball / lending ball supply port 20a is attached. Below the upper tray 20, there is formed an outlet 21a for discharging a prize ball that has flowed in excess of the number that can be accommodated in the upper tray 20, a game ball discharged from the upper tray 20 by operating the upper tray ball removing lever 20b, and the like. Have been. On the discharge side of the discharge port 21a, a lower tray 21 for storing the game balls discharged from the discharge port 21a is provided. On the left side of the front frame 11, there is provided a device outside the gaming machine 22 such as a prepaid card unit having a slit 22a for inserting a prepaid card.

[Main Configuration of Game Board 14] Next, the game board 1
4 will be described with reference to FIG. A center case 30 is provided substantially at the center of the game board 14. The center case 30 has a prize entrance 31
And a normal symbol display device 34 including three LEDs, and 4 indicating the number of times the normal symbol display device 34 is operated.
A normal symbol storage display LED 35 composed of a plurality of LEDs, a special symbol display device 32 for variably displaying a plurality of symbols, for example, 0-9 special symbols on a liquid crystal display, and a display 4 for displaying the number of times the special symbol display device 32 has been started. And a special symbol storage display LED 36 composed of a plurality of LEDs.

On the left and right sides of the center case 30, a normal symbol operation gate 2 for operating the normal symbol display device 34 is provided.
6, 26 are provided. Below the center case 30, a first type starting port 27 having a function of operating the special symbol display device 32 is provided. Below the first type starting port 27, a stop symbol of the ordinary symbol display device 34 is provided. Ordinary electric accessory 28 that opens both wings when hit
Is provided. The opened ordinary electric accessory 28 has a function of starting the operation of the special symbol display device 32, similarly to the first type starting port 27. A variable winning device 40 which is activated when the stop symbol of the special symbol display device 32 hits the symbol is provided below the ordinary electric accessory 28.

The variable winning device 40 is provided with a large winning opening 41 in the form of a door which is opened when a hit occurs. The winning winning opening 41 is provided on both sides thereof. Are provided respectively. Further, inside the special winning opening 41, there is provided a specific area 42 having a function of continuously opening the special winning opening 41, and a specific area switch (reference numeral 42 in FIG. 3) for detecting a game ball passing through the specific area 42.
a) and a special winning opening switch (indicated by reference numeral 43a in FIG. 3) for counting the number P of game balls that have won the special winning opening 41.

In addition, the game board 14 has windmills 23, 23
, Sleeve entrance prize opening 24, 24, corner decoration lamp 18
b, 18b, a prize lamp 18c that lights up when a prize is won,
An out-of-ball lamp 18d that lights up when the ball runs out, side decoration lamps 18e, 18e, and an out port 45 for collecting game balls that did not win as out balls are provided.
Further, many nails 47 are driven into the game board 14, and the game balls fired on the game board 14 fall while dancing between the nails 47.

[Electrical Configuration of Pachinko Machine 10] Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. The pachinko machine 10 is provided with a main board 100, on which a microprocessor 110 is mounted. The microprocessor 110 has a main CP for executing game control.
U112 and a ROM 11 in which various control programs for the main CPU 112 to execute various controls are recorded.
And a RAM 116 for temporarily storing various data such as a control program read from the ROM 114 when the main CPU 112 executes various control programs and data relating to a big hit occurring during a game. In addition, the RAM 116 backs up data processed by the main CPU 112 and commands transmitted to each board when the power is turned off, in order to reproduce a game state at the time of power shutdown such as a power failure after the power is restored.

The following components are electrically connected to the main substrate 100. Power supply board 80, payout control board 200 for controlling payout of award balls, etc., special symbol display device 3
2. A lamp control device 75 for controlling lamps provided on the game board 14, a sound control device 79 for controlling a sound reproduction device (not shown) for reproducing sound effects during a game, etc., a first type start of a game ball. A first-type start-up switch 27a for detecting the passage of the mouth 27, and game board information on winnings, big hits, and the like are transmitted to a computer (hereinafter, referred to as a hall computer, not shown) provided in a control room of the pachinko hall. Frame information terminal board 52, board-surface relay board 51, and game-frame relay board 55. The main substrate 100
Is connected via a switch SW1 to a backup power supply line L1a that supplies power for backing up data stored in the RAM 116 when the power is turned off.

The payout control board 200 is equipped with a microprocessor 210 which operates by inputting a control command sent from the main board 100. The microprocessor 210 has a sub CPU which controls payout of award balls and the like.
212, a ROM 214 in which various control programs for the sub CPU 212 to execute control such as payout of prize balls, and a control program read from the ROM 214 when the sub CPU 212 executes various control programs and a game And a RAM 216 for temporarily storing various data such as the number of prize balls generated in the RAM. The payout control board 200 is electrically connected to the power supply board 80, the CR connection board 56, the firing motor drive board 15c for driving the firing motor 15e, the game frame information terminal board 52, and the payout relay board 55. I have. Further, in the payout control board 200, a backup power supply line L2a for supplying power for backing up data stored in the RAM 216 when the power is turned off is connected via a switch SW2.

The game frame relay board 53 has a full detection switch 2 for detecting that the lower tray 21 is full of prize balls.
1b and the sensor relay board 54 are electrically connected. The sensor relay board 54 is electrically connected to the prize ball payout sensors 62a and 62b and the payout relay board 55 provided in the prize ball unit 62. The prize ball unit 62
Prize ball payout sensors 62a, 62b and prize ball payout motor 6
2c. There are two prize ball payout mechanisms for efficiently paying out prize balls, and each payout mechanism is driven by a prize ball payout motor 62c. The prize ball payout sensor 62a is provided in one mechanism, and the prize ball payout sensor 62b is provided in the other mechanism. Detection signals from the prize ball payout sensors 62a and 62b are transmitted from the sensor relay board 54 to the main board 100 via the game frame relay board 53.
The CPU 120 counts the number of paid-out balls based on the signal.

The payout relay board 55 is electrically connected to a ball-off switch 61 for detecting that there is no longer a ball, a prize ball payout motor 62c, and a ball-for-ball unit 63. The following components are electrically connected to the board-surface relay board 51. Ordinary electric accessory solenoid 28a for opening and closing the ordinary electric accessory 28, ordinary symbol display device 34, symbol actuation opening switch 26a, large winning opening switch 43a, and sleeve winning opening switch 24 for detecting winning in the sleeve winning opening 24.
a, a lower prize port switch 29a for detecting a prize to the lower prize port 29, a lower prize port switch 31a for detecting a prize to the lower prize port 31;

The special winning area solenoid 42b, the special winning area solenoid 43b, and the specific area switch 42a are electrically connected to the special winning opening relay board 50. The power supply board 80 is electrically connected to the CR connection board 56,
The CR connection board 56 is electrically connected to the gaming machine external device portion 22 including a frequency display board for displaying the remaining frequency of the prepaid card and a device for reading the prepaid card. The power supply board 80 is a 24 V AC (50 Hz / 6
(0 Hz) from the main power supply 70.

[Main Hardware Configuration] Next, the main hardware configuration of the pachinko machine 10 is shown in FIG.
This will be described with reference to FIG. Here, the main CPU 112 of the main board 100 and the sub C of the payout control board 200
The hardware configuration of the interface between the PUs 212 will be described as an example. Main CP of main board 100
Various control commands output from U112
Output to the output port 120 via the PU bus 118;
The output various control commands are temporarily stored in the output buffer 126 via the main CPU parallel output port 124, and then stored in the input buffer 220 connected to the sub CPU 212. And the main CPU
The transfer signal output from the main CPU bus 1
When the trigger signal (TRG2) 226 of the sub CPU 212 is input from the sub-CPU 212 via the output port 122, the output buffer 128, and the input buffer 222, various control commands accumulated in the input buffer 220 are transmitted to the sub-CPU 212.
The data is input to the input port 224 of the sub CPU 212 via the parallel input port 228. And the sub CPU
The 212 performs analysis such as what the captured various control commands mean, and outputs an award ball payout command to the award ball unit 62 based on the analysis result. Note that the main CPU 1 of the main board 100
The hardware configuration between the sub-CPU 12 and the sub CPU mounted on a board other than the payout control board 200 is the same as the above-described configuration.

[Main Configuration of Power Supply Board 80, Power Supply Board 80
Next, the main configuration of the power supply board 80 and the connection relation between the power supply board 80 and each board will be described with reference to FIGS. FIG. 5 is an explanatory diagram showing a main configuration of the power supply board 80 together with a connection relationship with each substrate, and FIG. 6 is an explanatory diagram showing details of a connection relationship between the power supply substrate 80 and each substrate. As shown in FIG. 5, the 24 V AC current supplied from the main power supply 70 is converted to 32 V DC by the rectifier circuit 81 via the fuse F <b> 1 and supplied to the main board 100 and the payout control board 200, respectively. The 32 V direct current is supplied to the DC / DC converter 82.
The voltage is changed to 12V, and supplied to the main board 100, the special symbol display device 32, the lamp control device 75, the voice control device 79, and the payout control board 200, respectively. Also,
The AC 24 V of the main power supply 70 is connected to the CR through the fuse F2.
It is supplied to the connection board 56.

The 12 V DC supplied to the main board 100 is supplied to the board relay board 51 (FIG. 3) to drive the ordinary motor accessory solenoid 28a, the ordinary symbol display device 34 and the like. The 12V direct current supplied to the special symbol display device 32 drives the liquid crystal and the like of the special symbol display device, and the 12V direct current supplied to the lamp control device 75 uses LEDs such as the corner decoration lamp 18b and the winning lamp 18c. Turn on or blink lamps. The 12 V DC supplied to the audio control device 79 drives a speaker via an audio circuit,
The 12 V DC supplied to the payout control board 200 is supplied to the prize ball unit 62 and the ball lending unit 63 via the payout relay board 55, and drives the prize ball payout motor 62c and the like.

The DC current converted to 12V by the DC / DC converter 82 is converted to 5V by the DC / DC converter 83. The DC of 5V is supplied to the clear signal output circuit 84, the main board 100, and the special symbol display. It is supplied to the device 32, the lamp control device 75, the sound control device 79, and the payout control board 200, respectively. Main board 100
5V DC supplied to the microprocessor 110
The DC power of 5 V supplied to the payout control board 200 as the driving power supply of FIG. 3 serves as the driving power supply of the microprocessor 210 (FIG. 3). Also, special symbol display device 32,
The 5 V DC supplied to the lamp control device 75 and the audio control device 79 serves as a drive power supply for a microprocessor (not shown) provided in each device. That is, the power of each board is all supplied from a single power board 80, and the power board 80 controls the power of each board. For this reason, as compared with the conventional configuration in which the pressure is changed on each substrate,
Space for the transformer circuit can be omitted on each substrate. Further, even if the substrates use the same power supply voltage, the circuit design for supplying power can be simplified as compared with a conventional substrate in which the voltage is changed for each substrate.

As shown in FIG. 6, the power supply board 80 has the No. 1 for electrically connecting to the main board 100. 1-7 of 7
A pin connector CN2a is attached, and the connector CN2a is connected to the connector CN1 attached to the main board 100 by a cable L1. Cable L
A terminal CN2b for connecting to the connector CN2a is attached to one end of the connector 1, and a terminal (not shown) for connecting to the connector CN1 on the main board 100 is attached to the other end. In addition, the power supply board 80 has the No. for electrically connecting to the payout control board 200. 1-7 of 7
A pin connector CN3a is attached, and the connector CN3a is connected to the payout control board 2 by a cable L2.
00 is connected to the connector CN1 attached to the connector 00. A terminal CN3b for connection to the connector CN3a is attached to one end of the cable L2, and a terminal (not shown) for connection to the connector CN1 on the payout control board 200 is attached to the other end. .

Further, the power supply board 80 includes a connector CN.
7a, CN4a, CN5a, CN6a, CN1a are attached. The connector CN7a is connected to the CR connection board 56 by a cable L3.
Is connected to a connector CN7a at one end.
7b is attached, and a terminal (not shown) for connecting to the connector CN2 on the CR connection board 56 side is attached to the other end. The connector CN4a is connected to the cable L4
Is connected to a special symbol control board 32a provided in the special symbol display device 32, a terminal CN4b for connecting to the connector CN4a is attached to one end of the cable L4, and a special symbol control board is attached to the other end. A terminal (not shown) for connecting to the connector CN1 on the 32a side is attached.

The connector CN5a is connected to a lamp control board 75 provided in the lamp control device 75 by a cable L5.
a terminal CN5b for connecting to the connector CN5a is attached to one end of the cable L5, and the connector CN on the lamp control board 75a side is attached to the other end.
A terminal (not shown) for connecting to the terminal 1 is attached. The connector CN6a is connected to a voice control board 79a provided in the voice control device 79 by a cable L6. A terminal CN6b for connecting to the connector CN6a is attached to one end of the cable L6, and the other end is connected to the other end. A terminal (not shown) for connecting to the connector CN1 on the audio control board 79a side is attached. Connector C
N1a is connected to the main power supply 70 by a power cord L7, and one end of the power cord L7 has a connector CN1a.
A terminal CN1b for connection to the terminal is attached.

Since the cables L4 to L6 have the same number of terminal pins, a common cable can be used.
Therefore, it is possible to save the trouble of selecting a cable as compared with a case where cables having different numbers of terminal pins are used, so that the cable connection processing can be performed easily and in a short time. In addition, since the number of cables that can be used in common is large, the manufacturing cost can be reduced as compared with the case where many types of cables having different numbers of terminal pins are manufactured.

[Data backup function] Here, the functions of backing up the data stored in the RAM 116 built in the microprocessor 110 and the RAM 216 built in the microprocessor 210, respectively, are shown in FIGS. 5, 7A and 8 ( This will be described with reference to A).
FIG. 7A shows the power supply board 80 and the microprocessor 11
FIG. 8A is an explanatory diagram showing a connection relationship between the power supply board 80 and the microprocessor 210. In the following description, the sub-substrate refers to each substrate other than the main substrate 100 and the payout control substrate 200.

As shown in FIG. 7A, a voltage monitoring IC 120 for monitoring the voltages of 12 V and 5 V is connected to the main board 100.
The output of 20 is connected to an NMI (Non-Maskable Interrupt) terminal of the microprocessor 110. Further, as shown in FIG.
A voltage monitoring IC 220 for monitoring voltages of 12 V and 5 V is also mounted on the IC.
The output of 220 is the NMI of microprocessor 210
(Non-maskable interrupt) terminal. Further, a voltage monitoring IC (not shown) for monitoring 5 V is mounted on each sub-substrate, and each voltage monitoring IC is connected to a microprocessor mounted on the sub-substrate. I have.

As shown in FIG. 5, a diode D1 is connected in series to a power supply line 83a connecting the DC / DC converter 83 and the payout control board 200, and a capacitor C1 is connected to the output side of the diode D1. (A power supply for storing data) are connected in parallel. DC / DC
A diode D2 is connected in series to a power supply line 83b connecting the converter 83 and the main board 100, and a capacitor C2 is connected to the output side of the diode D2.
(A power supply for storing data) are connected in parallel. Capacitors C1 and C2 are charged by a DC current of 5 V supplied from DC / DC converter 83, respectively.

The discharge current of the capacitor C1 is as shown in FIG.
As shown in FIG. 6, the microprocessor 11 is connected via the backup power supply line L1a in the cable L1 (FIG. 6).
0 is supplied to the internal RAM backup power supply terminal VBB. That is, when the supply of 24 V AC from the main power supply 70 (FIG. 5) is stopped due to a power failure or the like, the power supply voltage monitoring I
C120 (FIG. 7A) detects a drop in the power supply voltage and D120
Since the discharging current of the capacitor C1 is supplied to the microprocessor 210 instead of the C / DC converter 83,
Data related to award ball payout stored in the RAM 216 is backed up (stored and stored).

The discharge current of the capacitor C2 is as shown in FIG.
As shown in (A), the microprocessor 210 is connected via the backup power supply line L2a in the cable L2.
Is supplied to a power supply terminal VBB for internal RAM backup. That is, when the supply of 24 V AC from the main power supply 70 (FIG. 5) is stopped due to a power failure or the like, the power supply voltage monitoring IC
220 (FIG. 8A) detects a drop in the power supply voltage and
Since the discharging current of capacitor C2 is supplied to microprocessor 110 instead of / DC converter 83, R
The data stored in the AM 116 is backed up (stored and held). The data to be backed up includes, for example, the number of times the big winning opening is opened in the game when a big hit occurs, the number of winnings in the big winning opening, the number of rounds, the reach state before the big hit occurs, the pattern variation, the stop symbol ,
Data generated during the game, such as the number of operating memories of the ordinary symbol display device 34, the number of starting memories of the special symbol display device 32, the reliability, the profitability, the probability at the time of probability variation, the symbol variation start interval at the time of working hours, or Main CPU1 when power off
12 is a control command (control data) transmitted to the payout control board 200 or each sub-board.

Assuming that the degree of reliability is, for example, a case where "7" is displayed in each of the three display areas of the special symbol display device 32 as a big hit, "7" is displayed in the two display areas. It means the probability that “7” stops in the remaining one display area. In addition, the profit level means the probability of occurrence of a jackpot in which the largest number of prize balls are paid out when there is a difference in the degree of profit that the player can obtain, for example, the number of prize balls paid out depending on the type of big hit. . In this embodiment, the capacitor C1 is an electric double layer capacitor with a nominal capacitance of 0.1 F and a rated voltage of 5.5V. The cables L1 to L6 are FPCs (flexible print circuits).

[Erase of Backup Data] Next, RA
Configuration for erasing backup data stored in M116, 216 FIGS. 7B and 8B
This will be described with reference to FIG. FIG. 7B is a partial explanatory diagram showing a configuration in which a switch is provided in the middle of the cable L1a.
FIG. 8B is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L2a. As shown in FIG. 7B, a switch SW1 is connected in the middle of the backup power supply line L1a in the cable L1 (FIG. 6) for electrically connecting the power supply board 80 and the main board 100. Normally, it is closed (ON
When the switch SW1 is opened (OFF),
Capacitor C2 provided on power supply board 80 (FIG. 5)
Then, the backup power supplied to the built-in RAM backup power supply terminal VBB of the microprocessor 110 is cut off, and the data backed up in the RAM 116 (FIG. 7A) is erased. Thereby, RAM1
Data such as various control commands that are backed up (stored and stored) in the game 16 and indicate the game state when the power is turned off can be deleted.

As shown in FIG. 8B, the backup power supply line L2 in the cable L2 (FIG. 6) for electrically connecting the power supply board 80 and the dispensing control board 200.
The switch SW2 is connected in the middle of a. Normally,
When the switch SW2, which is closed (ON) for supplying backup power, is opened (turned OFF), a power supply terminal for a built-in RAM backup of the microprocessor 210 from the capacitor C1 (FIG. 5) provided on the power supply board 80. The backup power supplied to the VBB is cut off, and the data backed up in the RAM 216 (FIG. 8A) is erased. As a result, the winning data indicating the number of winnings, the data indicating the number of paying out prize balls, and the like that are backed up (stored and stored) in the RAM 216 can be deleted.

[Main control from power-on to power-off]
Next, main control from power-on to power-off will be described with reference to FIGS. 9 to 12 and FIG. FIG.
FIG. 10 is a flowchart showing a flow of a program start process executed by the sub CPU 212, and FIG.
It is a flowchart which shows the flow of the main program process which U212 executes. FIG. 11 is a flowchart illustrating a flow of a command input process executed by the sub CPU 212, and FIG. 12 is a flowchart illustrating a flow of the NMI interrupt process 1 executed by the sub CPU 212. FIG. 16 is a timing chart showing the rise and fall of the power supply of each substrate. In the following description, the sub CPU 2
The processing executed by the CPU 12 is stored in the ROM 214 as a computer program, and the processing executed by the main CPU 112 is stored in the ROM 114 as a computer program.

(Startup of Power Supply) When the main power supply 70 (FIG. 5) is started up, the DC / DC converter 83 applies 5 V to each substrate.
Power is supplied. Then, when the voltage becomes equal to or higher than the minimum operating voltage of the voltage monitoring IC connected to the microprocessor mounted on each board, a system reset signal (low level) is output on all the boards and is stabilized (FIG. 16). Subsequently, after a time Trs from when the 5V power supply reaches the voltage Vus, the system reset signal of the sub-substrate is released (low level to high level), and control of each sub-substrate is started. Then, the DC / DC converter 82 sends one
The system reset signal of the dispensing control board 200 is released after a time Trh from when the 2V power supply is supplied and the 12V power supply reaches the voltage Vuh, and the sub CPU 212 (FIG. 8A).
Performs a security check. In this security check, it is checked whether or not there is any abnormality in the computer program recorded in the ROM 214. Subsequently, when the security check ends, the sub CPU 212 starts operating.

Then, the system reset signal of the main board 100 is released after a time Trm after the 12 V power supply reaches the voltage Vum, and the main CPU 112 of the main board 100 starts the operation after executing the security check. At this stage, the pachinko machine 10 is in a playable state. As described above, the sub-substrate, the payout control substrate 200, the main substrate 100
Control can be started in the order of
There is no omission of command reception from the main board 100 on all boards managed by 0.

(Program Start Process of Sub CPU 212) Here, a program start process executed by the sub CPU 212 will be described with reference to FIG. Sub C
The PU 212 sets interrupt prohibition (S10), and sets a stack pointer for holding the address of the main routine at the bottom of the address when shifting from the main routine to the subroutine (S12). Then sub CP
The U212 sets access permission to the RAM 216 (S14), and sets the interrupt mode to mode 2 (S1).
6). Subsequently, the sub CPU 212 sets an address to be used in mode 2 in the interrupt register (S18).
It is determined whether the check data in the RAM 216 is correct, for example, whether it is A5A5H (S20). If the check data is correct, for example, A5A5H (S20: Yes), the backup area (storage holding) in the RAM 216 is determined. Areas other than (area) are cleared to 0 (initialized) (S22).

On the other hand, if the check data is incorrect (S20: No), the entire area of RAM 216 (for example, 2
After clearing (initializing) all the data (56 bytes) to 0, the check data (for example, A5A5H) is stored (S2).
4). Subsequently, the sub CPU 212 initializes a built-in device such as a watchdog timer which is a timer for monitoring runaway of the sub CPU 212 (S26), and initializes a work area (S28). Subsequently, the sub CPU 21
2 sets an interrupt permission (S30) and shifts to an infinite loop in which this S30 is repeated.

(Main Program Processing of Sub CPU 212) Next, the flow of the main program processing executed by the sub CPU 212 of the payout control board 200 will be described with reference to FIG. This main program processing is performed by CTC
(Timer counter) is executed by a channel 3 interrupt of 218 (FIG. 8A). The sub CPU 212 sets interruption permission (S100) and restarts the watchdog timer (S200). Then, sub CPU2
Reference numeral 12 denotes data and command output processing (S300), input processing (S400), prize ball processing (S500) such as storage of the number of prize balls to be paid out and a payout command, and data from the CR connection board 56 (FIG. 3) A ball lending process (S600) for controlling the ball lending unit 63 is executed based on this.

(Command Input Processing of Sub CPU 212)
Next, a flow of a command input process executed by the sub CPU 212 will be described with reference to FIG. This command input processing is executed by the channel 2 interrupt of the CTC 218. The sub CPU 212 inputs a control command such as a payout command sent from the main board 100 (S50), and checks the input control command (S52). For example, the control command is 2 bytes composed of an 8-bit signal, and is distributed to each byte. Subsequently, the sub CPU 212 determines whether the input control command is a control command meaning, for example, a command indicating a payout command of 5 prize balls, a command indicating a payout command of 15 prize balls, or the like. Analysis is performed (S54), and interruption permission is set (S56). As described above, the command input process is assigned to the channel 2 interrupt, and is executed in the second priority order following the NMI interrupt process described later. For example, the sub CPU 212 outputs a pulse to the winning ball payout motor 62c. Even if the main board sends a control command for paying out a prize ball, the control command can be analyzed with priority. Therefore, it is possible to eliminate a prize ball payout error or a delay in award ball payout due to a failure to receive a control command from the main board 100.

(Shutdown of power supply) When the main power supply 70 is cut off due to power cutoff, power failure, or power supply abnormality at the end of pachinko hall business, and the 12V power supply reaches the voltage Vdm (FIG. 16), the main board is turned off. A system reset signal is generated at 100 (from high level to low level). Then 12
When the V power supply reaches a voltage Vdh (for example, 10.3 V), N
An MI signal is generated and the NMI signal lasts for a time Tnmi. Data such as the number of prize balls is backed up in the RAM 216 during the time period Tnmi. At this time,
The discharge current of the capacitor C1 (FIG. 5) is applied to the backup power supply terminal VBB of the microprocessor 210 (FIG. 8).
(A)), the RAM 216 can back up (store and hold) data such as prize ball data. Further, the discharge current of the capacitor C2 (FIG. 5) is changed to the backup power supply terminal VBB of the microprocessor 110.
(FIG. 7A), the RAM 116 can back up (store and hold) data such as various control commands indicating a game state at the time of power-off.

(NMI interrupt processing 1) Here, the sub CP
FIG. 12 shows NMI interrupt processing 1 executed by U212
This will be described with reference to FIG. When the NMI signal is generated, the sub CPU 212 sets access prohibition in the access register for the RAM 216 (S70). This interrupt process is executed with the highest priority over other interrupt processes. That is, by prohibiting access to the RAM 216,
The prize ball data stored in the RAM 216 is prevented from being rewritten. Although not shown in the flowchart, when the NMI signal is generated, the main CPU 112 also sets access prohibition in an access register for the RAM 116. This interrupt process is executed with the highest priority over other interrupt processes. In other words, by prohibiting the access to the RAM 116, the prize ball data stored in the RAM 116 is prevented from being rewritten.

For example, at the time of backing up the RAMs 116 and 216, if another interrupt process has already been executed and a new interrupt is prohibited, and the processing time of the other interrupt process becomes longer, Interrupt processing is permitted, and access to the RAMs 116 and 216 is prohibited in an attempt to prohibit access.
There is a possibility that some or all of the stored contents of the memory 16 may be destroyed. Therefore, the NMI interrupt process is used to set RAM1
By prohibiting the access to the
The storage contents of M116 and 216 are prevented from being destroyed. Then, as shown in FIG. 16, when the time Tnmi elapses, NM
The I signal stops, a system reset signal is generated on the main board 100, and the main board 100 is reset. Subsequently, a system reset signal is generated in the payout control board 200, and the payout control board 200 is reset. Subsequently, when the 5V power supply reaches the voltage Vds, a system reset signal is generated on the sub-substrate, and the sub-substrate is reset. Note that R
When the power is turned on during the period when the AM 116 is backed up, the main CPU 112
Then, various control commands indicating the game state at the time of power-off stored in the control unit 6 are output to the payout control board 200 and each sub-board, and the game is restarted from the middle of the game at the time of power-off. Also,
If the power is turned on while the RAM 216 is being backed up, the sub CPU 212
6, the prize ball payout motor 6 is referred to.
2c (FIG. 3) is driven to pay out award balls corresponding to the number of award balls.

[Effects of the First Embodiment] (Effects of Data Backup)
If the pachinko machine 10 of the embodiment is used, even if the main power supply 70 is cut off due to a power failure or the like, access to the RAMs 116 and 216 can be prohibited by the NMI interrupt processing. Game data or prize ball data stored in the RAM 216 can be prevented from being destroyed. Further, the RAM 1 built in the microprocessor 110 mounted on the main board 100 from the capacitor C2 serving as a backup power supply.
Since power can be supplied to the RAM 16, there is no possibility that data such as various control commands stored in the RAM 116 will be lost. Then, after the power is restored, the game can be restarted based on data such as various control commands stored in the RAM 116. Further, a RAM 2 built in a microprocessor 210 mounted on the dispensing control board 200 from a capacitor C1 serving as a backup power supply.
Since power can be supplied to the prize ball 16, there is no fear that the prize ball data stored in the RAM 216 will be lost. Then, after the power is restored, the prize balls corresponding to the number of prize balls stored in the RAM 216 can be paid out.

(Effect of Erasing Backup Data) Using the pachinko machine 10 of the first embodiment,
By turning off the switch SW1, the backup power supplied from the capacitor C2 to the microprocessor 110 of the main board 100 can be cut off, so that the data backed up in the RAM 116 can be erased. Also, switch SW2 is turned off.
, The payout control board 2 from the capacitor C1
00, the backup power supplied to the microprocessor 210 can be cut off.
6 can be erased. Therefore, even if data related to the payout of prize balls at the time of trial shooting before the opening of the pachinko hall or prize ball data rewritten due to static electricity noise or fraud is backed up in the RAM 216, the data is backed up. Since the stored data can be erased, there is no danger that the store side will suffer any disadvantage due to the prize balls being paid out based on the backed up data. Further, even if the control data for controlling the game generated during the trial shooting before the store is opened is backed up in the RAM 116, the backed up control data can be erased. Is performed, the game is started based on the backed up control data, and the player does not feel uncomfortable.

<Second Embodiment> Next, a second embodiment according to the present invention will be described with reference to FIGS. The pachinko machine according to the second embodiment operates the switches SW1 and SW2 from the hall computer to
M backup data can be cleared. FIG. 13 is a flowchart showing a flow of a RAM initialization process executed by the hall computer.
FIG. 14 is a flowchart showing the flow of the processing of the analysis circuits 91 and 92. FIG. 15 is an explanatory diagram showing the main electrical configuration in blocks.

As shown in FIG. 15, the hall computer 90 is connected to analysis circuits 91 and 92, respectively. The analysis circuit 91 includes a switch SW1 and an analysis circuit 92.
Are connected to the switch SW2, respectively. The analysis circuits 91 and 92 analyze commands output from the hall computer 90, respectively. The analysis circuit 91 turns ON / OFF the switch SW1 based on the analysis result,
The analysis circuit 92 switches the switch SW based on the analysis result.
2 is turned ON / OFF. As shown in FIG. 13, when the hall computer determines that the power of the hall is turned on (S2: Yes), the hall computer outputs a switching command to each pachinko machine (S4).

Then, as shown in FIG.
1 judges that the switching command output from the hall computer 90 has been input (S80: Yes),
It is analyzed whether or not the input switching command is an OFF command (S82). If the analysis result is an OFF command (S82: Yes), the OFF signal is transmitted to the switch S.
Output to W1 (S84). Thereby, the switch SW
1 operates OFF and the supply of the backup power from the capacitor C2 is cut off, so that the data backed up in the RAM 116 is erased. Similarly, the analysis circuit 92 also analyzes the switching command output from the hall computer 90. If the command is an OFF command, the switch SW2 is turned off.
The data backed up in No. 16 is deleted. If the switching command output from the hall computer 90 is not an OFF command, that is, if it is an ON command (S82: No), the analysis circuits 91 and 92 output ON signals to the switches SW1 and SW2, respectively. Since the ON state of SW1 and SW2 is maintained, the supply of the backup power from the capacitors C2 and C1 is continued, so that the backup of the data stored in the RAMs 116 and 216 is maintained.

[Effects of the Second Embodiment] As described above, if the pachinko machine according to the second embodiment is used, the switches SW1 and SW2 are turned off based on the switching command output from the hall computer 90. As a result, the backup power supplied from the capacitors C2 and C1 is cut off, and the data backed up in the RAMs 116 and 216 can be erased. Therefore, since the backup data of each pachinko machine can be deleted from the hall control room, the efficiency of the data erasing operation is improved as compared with the case where the pachinko machines are opened one by one and the switches SW1 and SW2 are operated. be able to.

Third Embodiment Next, a third embodiment according to the present invention will be described with reference to FIGS. The pachinko machine according to the third embodiment is characterized in that the backup data can be erased when the voltage of the drive power supply of the pachinko machine drops. FIG. 17 is a flowchart showing the flow of processing of the power supply voltage monitoring IC, and FIG.
FIG. 8 is an explanatory diagram showing a main electric configuration by blocks.

As shown in FIG. 18, the power supply board 80 is connected to power supply voltage monitoring ICs 120 and 220. The power supply voltage monitoring IC 120 is connected to the switch SW1, and the power supply voltage monitoring IC 220 is connected to the switch SW2. The power supply voltage monitoring ICs 120 and 220
From the power supply board 80 to the microprocessor 110,
The power supply voltage of 12V and 5V supplied to 210 is monitored. Then, as shown in FIG. 17, the power supply voltage monitoring IC 120 determines that the drive power supply of the pachinko machine has dropped due to a power failure or the like, and that the monitored power supply voltage V has dropped below the voltage V1 (S90: Yes). , And outputs an OFF signal to the switch SW1 (S92). For example, when the monitored 12V drops to 11V, an OFF signal is output to the switch SW1. Thereby, the switch SW1
Operates OFF and the supply of the backup power from the capacitor C2 is cut off, so that the data backed up in the RAM 116 is erased. Similarly, the power supply voltage V monitored by the power supply voltage monitoring IC 220 is the voltage V1.
If it is determined that the voltage has decreased below, an OFF signal is output to the switch SW2.
In operation, the supply of the backup power from the capacitor C1 is cut off, so that the data backed up in the RAM 216 is erased.

[Effects of the third embodiment] As described above, if the pachinko machine according to the third embodiment is used, the switches SW1 and SW2 are turned off as the driving power of the pachinko machine decreases. , The backup power supplied from the capacitors C2 and C1 is cut off, and the RAM 1
16, 216 can be deleted. In other words, when the drive power drops to a predetermined voltage due to a power failure or the like, the data in the RAMs 116 and 216 is held by the data backup function, and the stored data is automatically erased as the drive power drops. be able to. Therefore, the backup data of each pachinko machine can be erased by a simple operation of shutting off the drive power when the store is closed.

<Other Embodiments> (1) The pachinko machines can be individually designated from the hall computer 90 (designating means) and the backup data of the designated pachinko machines can be erased (individual erasing means). ). (2) In each of the above embodiments, the R
The case of erasing the backup data of the AM 116 and the RAM 216 of the payout control board 200 has been described. However, a switch is provided between each microprocessor of the special symbol display device 32, the voice control device 79 and the lamp control device 75 and the backup power supply. By connecting and operating these switches, the power supply from the backup power supply is cut off and the RA built in each microprocessor is connected.
The backup data stored in M may be erased. Further, the configuration of the second embodiment or the third embodiment can be applied to each device. (3) Further, in each of the above-described embodiments, the case where a capacitor is used as a backup power source has been described as an example.
An electrically erasable ROM such as an EEPROM, a solid storage element such as an IC, a battery, a rechargeable battery, a chargeable solar battery, and the like can also be used. (4) In each of the above-described embodiments, the first-type pachinko machine has been described as an example of the gaming machine according to the present invention.
Of course, the present invention can be applied to other game machines such as a type 2 pachinko machine, a type 3 pachinko machine, other types of pachinko machines, and slot machines.

[Correspondence between Claims and Embodiments] The main CPU 112 corresponds to the control means according to claim 1 of the present invention, and the RAMs 116 and 216 correspond to the storage means. Further, the capacitors C1 and C2 correspond to the memory holding unit, and the switches SW1 and SW2 correspond to the switch unit.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a pachinko machine according to an embodiment of the present invention as viewed from the front.

FIG. 2 is an explanatory diagram showing a main configuration of a game board 14 provided in the pachinko machine 10 shown in FIG.

FIG. 3 is an explanatory diagram showing an electrical configuration of the pachinko machine 10 by blocks.

FIG. 4 is an explanatory diagram showing a main hardware configuration of the pachinko machine 10;

FIG. 5 is an explanatory diagram showing a main configuration of a power supply board 80 together with a connection relationship with each board.

FIG. 6 is an explanatory diagram showing details of a connection relationship between a power supply board 80 and each board.

FIG. 7A is an explanatory diagram illustrating a connection relationship between a power supply board 80 and a microprocessor 110;
(B) is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L1a.

FIG. 8A is an explanatory diagram showing a connection relationship between a power supply board 80 and a microprocessor 210;
(B) is a partial explanatory view showing a configuration in which a switch is provided in the middle of the cable L2a.

FIG. 9 is a flowchart illustrating a flow of a program start process executed by a sub CPU 212;

FIG. 10 is a flowchart showing a flow of a main program process executed by a sub CPU 212.

FIG. 11 is a flowchart illustrating a flow of a command input process executed by a sub CPU 212;

FIG. 12 is a flowchart illustrating a flow of an NMI interrupt process 1 executed by a sub CPU 212;

FIG. 13 is a flowchart illustrating a flow of a RAM initialization process executed by the hall computer according to the second embodiment of the present invention.

FIG. 14 is a flowchart showing a flow of processing of analysis circuits 91 and 92.

FIG. 15 is an explanatory diagram showing a main electrical configuration by blocks.

FIG. 16 is a timing chart showing the rise and fall of the power supply of each substrate.

FIG. 17 is a flowchart showing a processing flow of a power supply voltage monitoring IC according to a third embodiment of the present invention.

FIG. 18 is an explanatory diagram showing a main electrical configuration by blocks.

FIG. 19 is an explanatory front view of a conventional pachinko machine.

20 is an explanatory diagram of a back set of the pachinko machine shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 pachinko machine (game machine) 70 main power supply 80 power supply board 90 hall computer 100 main board 112 main CPU (control means) 116 RAM (storage means) 200 payout control board 212 sub CPU 216 RAM (storage means) C1, C2 capacitors ( SW1 and SW2 switches (erasing means)

Claims (3)

[Claims] 1. A control means for controlling a game, a storage means for storing data generated during the game, and said storage means when a voltage of a drive power supply supplied to the game machine drops to a predetermined voltage. Storage means for holding the storage of the storage means by supplying power for storage holding to the means, wherein the control means refers to the data stored and held by the storage means to play a game. A controllable gaming machine, comprising: switch means capable of cutting off the supply of the power for storing data. 2. The gaming machine according to claim 1, wherein the switch means operates when the drive power is turned on, and cuts off the power supply for holding the memory. 3. The power supply according to claim 1, wherein the switch means operates when the voltage of the drive power supply drops to a predetermined voltage, and cuts off the power supply for storing the data. The gaming machine described.