JP2001230262A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve reliability by restraining deterioration of current amplification factor based on an energization time. SOLUTION: A sub-collector layer 21 for reducing the resistance of a collector layer 22 on a substrate 20, and emitter cap layers 27, 28, 29 for reducing the ohmic contact resistance of an emitter layer are formed. A planer doped layer 211 is formed inside the sub-collector layer. According to the planer doped layer, even if an energization time to the semiconductor device 2 with a structure of a hetero bipolar transistor increases, current amplification factor can be prevented from lowering and reliability of a semiconductor device can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high-speed LSI (L
arge Scale Integratedcirc
The present invention relates to a semiconductor device used for ultra-high-speed, large-capacity optical communication and the like, and particularly to a hetero-bipolar transistor having a high current amplification factor.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor device.
Terrorist bipolar transistor (hereinafter referred to as HBT)
The structure is shown. This HBT 1 is made of gallium arsenide (GaAs).
s), the resistance of the collector layer 12 on the semi-insulating substrate 10
N to reduce⁺-GaAs layer (n-type, 5 × 10
¹⁸cm^-3), The sub-collector layer 11, n^--GaAs
Layer (n-type, 5 × 10¹⁶cm^-3), The collector layer 12
p⁺-GaAs layer (p-type, 4 × 10¹⁹cm^-3)
Layer 13, n-AlGaAs graded layer (n-type,
5 × 10¹⁷cm^-3), N-AlG
aAs layer (n-type, 5 × 10¹⁷cm^-3) Emitter layer
15. n-AlGaAs graded layer (n-type, 5 × 1
0¹⁷cm^-3), The emitter layer 16, the emitter layer 14,
15 and 16 for reducing ohmic contact resistance
N⁺-GaAs layer (n-type, 5 × 10¹⁸cm^-3)
Emitter cap layer 17, n⁺-InGaAs gray
Dead layer (n-type, 2 × 10¹⁹cm ^-3)
Cap layer 18, n⁺-InGaAs layer (n-type, 2 × 10
¹⁹cm^-3) Is formed in this order.
It is a configuration that has been made.

[0003] Sub-collector layer 1 of n ⁺ -GaAs layer
1, a collector layer 12 composed of an n ⁻ -GaAs layer, n-Al
GaAs graded emitter layer 14, n-A
An emitter layer 15 composed of an lGaAs layer, n-AlGaAs
Emitter layer 16 composed of a graded layer, n ⁺ -GaAs
The n-type impurity of the emitter cap layer 17 formed of a layer is silica (Si). n ⁺ -InGaAs gray emitter cap layer 18 formed of a dead layer, n ⁺ -InGaAs layer n-type impurity of the emitter cap layer 19 of the Theron (S
e). p ^{+ of the} base layer 13 composed of ap ⁺ -GaAs layer
The type impurity is carbon (C). In FIG. 4, x represents a mixed crystal ratio of Al, and y represents a mixed crystal ratio of In (the same applies hereinafter).

[0004]

However, in general, HB
In T, it is important to improve the reliability by increasing the current amplification factor β. However, the conventional HBT 1 has a disadvantage that the current amplification factor β decreases as the energization time increases. FIG. 5 is a diagram showing the relationship between the current supply time t (hr) of the conventional HBT 1 and the current amplification factor β. As is apparent from this figure, the current amplification factor β decreases as the energization time t (hr) increases. For example, the energization time t (h
When r) reaches 600 hours, the reduction rate of the current amplification factor β is as high as 44%.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the reliability by suppressing the deterioration of the current amplification factor due to the conduction time.

[0006]

In order to achieve the above object, the present invention provides a sub-collector layer for reducing the resistance of a collector layer formed on a substrate, and an emitter layer formed on the substrate. A semiconductor device having a structure of a hetero bipolar transistor having at least an emitter cap layer for reducing ohmic contact resistance, wherein a planar doped layer is formed in the subcollector layer. I will provide a.

[0007] According to the above configuration, even if the time for energizing the semiconductor device is increased, a decrease in the current amplification factor can be prevented by the action of the planar dope layer formed in the subcollector layer. Reliability can be improved. According to another aspect of the present invention, there is provided a first conductivity type GaAs formed on a semi-insulating GaAs substrate.
an s collector layer, a second conductivity type GaAs base layer formed on the GaAs collector layer, a first conductivity type AlGaAs emitter layer formed on the GaAs base layer, and the semi-insulating GaAs substrate. A GaAs subcollector layer of a first conductivity type formed between the GaAs collector layer and the first conductivity type for reducing the collector resistance, and a first GaAs subcollector layer formed thereon to reduce the ohmic contact resistance of the AlGaAs emitter layer. It has a structure of a hetero bipolar transistor including a conductive type GaAs emitter cap layer or an InGaAs emitter cap layer, and the sub-collector layer is formed of one or more planar dopes doped with selenium (Se) or silica (Si). There is provided a semiconductor device comprising a layer.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An HBT, which is a semiconductor device of the present embodiment, includes a sub-collector layer for reducing the resistance of a collector layer formed on a substrate, a collector layer, a base layer, an emitter layer, An emitter cap layer for reducing the ohmic contact resistance of the emitter layer, and at least one planar doped layer is formed in the sub-collector layer. I have. By forming the planar dope layer in the sub-collector layer, it is possible to prevent a decrease in the current amplification factor β even if the time t (hr) for energizing the HBT increases.

[0009]

FIG. 1 shows the structure of an HBT according to an embodiment of the present invention.
You. This HBT 2 is made of gallium arsenide (GaAs).
The resistance of the collector layer 22 is reduced on the semi-insulating substrate 20.
N to let⁺-GaAs layer (n-type, 5 × 10¹⁸c
m^-3), The sub-collector layer 21^--GaAs layer
(N-type, 5 × 10¹⁶cm^-3), The collector layer 22, p
⁺-GaAs layer (p-type, 4 × 10¹⁹cm^-3) Bae
Layer 23, n-AlGaAs graded layer (n-type, 5
× 10¹⁷cm^-3), N-AlGa
As layer (n-type, 5 × 10¹⁷cm^-3) Emitter layer 2
5, n-AlGaAs graded layer (n-type, 5 × 10
¹⁷cm^-3), The emitter layers 24,
To reduce ohmic contact resistance of 5, 26
N⁺-GaAs layer (n-type, 5 × 10¹⁸cm^-3)
Emitter cap layer 27, n⁺-InGaAs grade
Layer (n-type, 2 × 10¹⁹cm ^-3)
Layer 28, n⁺-InGaAs layer (n-type, 2 × 10¹⁹
cm^-3) Is formed in this order.
It is the configuration that was done.

Subcollector layer 2 made of n ⁺ -GaAs layer
1, a collector layer 22 composed of an n ⁻ -GaAs layer, n-Al
Emitter layer 24 of GaAs graded layer, n-A
an emitter layer 25 composed of an lGaAs layer, n-AlGaAs
Emitter layer 26 composed of a graded layer, n ⁺ -GaAs
The n-type impurity of the emitter cap layer 27 is silica (Si). n ⁺ -InGaAs gray emitter cap layer 28 made of a dead layer, n ⁺ -InGaAs layer n-type impurity of the emitter cap layer 29 made of In Theron (S
e). p of base layer 23 made of p ⁺ -GaAs layer
The type impurity is carbon (C). And n ⁺ -Ga
In the sub-collector layer 21 composed of an As layer, selon (Se)
Are formed in a plurality of layers.

[0011] The HBT 2 having such a structure is formed, for example, by flowing arsine gas and hydrogen selenide (H ₂ Se) gas.
The sub-collector layer 21 made of an n ⁺ -GaAs layer having a thickness of 500 nm is planar-doped with selon (Se) to form 26 planar-doped layers 211 at a pitch of 20 μm. At this time, the planar dope layer 21
The sheet carrier concentration of No. 1 was about 1 × 10 ¹³ cm ⁻² .

FIG. 2 shows the energizing time t of the HBT 2 of this embodiment.
FIG. 6 is a diagram showing a relationship between (hr) and a current amplification factor β. As is clear from this figure, the current amplification factor β in the initial state of the HBT 2 of the present embodiment is 150 to 160, whereas the current amplification factor β in the initial state of the conventional HBT 1 shown in FIG.
100 to 110, indicating that the current amplification factor β in the initial state of the HBT 2 of the present embodiment is significantly improved as compared with the current amplification factor β of the conventional HBT 1 in the initial state.

In the case of the HBT 2 of this embodiment, the energization time t (hr) increases, for example, the energization time t (hr)
Is 600 hours, the decrease rate of the current amplification factor β is 95
Even when the energization time t (hr) is 1000 hours, the reduction rate of the current amplification factor β is 90%, whereas in the case of the conventional HBT 1 shown in FIG.
When (hr) is 600 hours, the decrease rate of the current amplification factor β is as much as 44%, and the change with time of the current amplification factor β of the HBT 2 of the present embodiment is smaller than the change with time of the current amplification factor β of the conventional HBT 1. It can be seen that it is greatly improved.

FIG. 3 is a diagram showing the value of the current amplification factor β when the number of planar doped layers 211 formed in the subcollector layer 21 is changed. As is clear from this figure, the planar doped layer 211 has an effect of improving the current amplification factor β even with only one layer, but the effect of improving the current amplification factor β sharply increases from the second layer and the third and subsequent layers. Then the current amplification factor β
It can be seen that the effect of the improvement gradually increases. .

Although the carrier concentration of the subcollector layer 21 is set to 5 × 10 ¹⁸ cm ⁻³ here, the higher the carrier concentration of the subcollector layer 21 is, the more remarkable the effect of improving the current amplification factor β is. It turned out to be out. Note that the sheet carrier concentration of the planar doped layer 211 is 1 × 10 ¹² c
Within the range of m ⁻² to 1 × 10 ¹⁵ cm ⁻² , there was almost no difference in the effect of improving the current amplification factor β.

In the embodiment described above, arsine gas and hydrogen selenide (H ₂ Se) gas are allowed to flow,
1 was planar-doped with n-type cellon (Se) to form a planar doped layer 211. For example, a disilane (Si ₂ H ₆ ) gas or a monosilane (SiH ₄ ) gas was flowed into the sub-collector layer 21. The same effect can be obtained by forming a planar doped layer by planar doping with n-type silica (Si).

[0017]

As described above, according to the present invention, it is possible to prevent a decrease in the current amplification factor even when the energizing time to the semiconductor device is increased, thereby improving the reliability of the semiconductor device. Can be.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a structure of an embodiment of an HBT of the present invention.

FIG. 2 is a diagram showing a relationship between a current supply time and a current amplification factor of the HBT of FIG. 1;

FIG. 3 is a diagram showing a value of a current amplification factor when the number of planar doped layers formed in a subcollector layer of the HBT of FIG. 1 is changed.

FIG. 4 is an explanatory view showing the structure of a conventional HBT.

FIG. 5 is a diagram illustrating a relationship between a conduction time of the HBT of FIG. 4 and a current amplification factor.

[Explanation of symbols]

 Reference Signs List 1 HBT 2 HBT 10 semi-insulating substrate 11 sub-collector layer 12 collector layer 13 base layer 14 emitter layer 15 emitter layer 16 emitter layer 17 emitter cap layer 18 emitter cap layer 19 emitter cap layer 20 semi-insulating substrate 21 sub-collector layer 22 collector layer Reference Signs List 23 base layer 24 emitter layer 25 emitter layer 26 emitter layer 27 emitter cap layer 28 emitter cap layer 29 emitter cap layer 211 planar doped layer

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Junichi Igarashi 5-1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture F-term in the Hidaka Factory, Hitachi Cable, Ltd. 5F003 AP00 BC02 BC05 BE02 BE04 BE90 BF06 BM03 BP23 BP32

Claims (6)

[Claims] At least a sub-collector layer for reducing a resistance of a collector layer formed on a substrate and an emitter cap layer for reducing an ohmic contact resistance of an emitter layer formed on the substrate are provided. A semiconductor device having a structure of a hetero bipolar transistor, wherein a planar doped layer is formed in the sub-collector layer. 2. The method according to claim 1, wherein the planar doped layer is formed of selenium (S
2. The semiconductor device according to claim 1, wherein e) is doped. 3. The method according to claim 1, wherein the planar doped layer is formed of silica (S
2. The semiconductor device according to claim 1, wherein i) is doped. 4. The method according to claim 1, wherein said planar doped layer is 1 × 10 ¹² c
The semiconductor device according to claim 1, wherein the semiconductor device has a sheet carrier concentration of m ⁻² to 1 × 10 ¹⁵ cm ⁻² . 5. The method according to claim 1, wherein the planar doped layer has at least one layer.
The semiconductor device according to claim 1, wherein the semiconductor device is formed of at least a layer. 6. A first semiconductor device formed on a semi-insulating GaAs substrate.
A GaAs collector layer of the first conductivity type, a GaAs base layer of the second conductivity type formed on the GaAs collector layer, and a first conductivity type of A formed on the GaAs base layer.
a first conductivity type Ga formed between the semi-insulating GaAs substrate and the GaAs collector layer for reducing collector resistance.
The structure of a hetero bipolar transistor including an As subcollector layer and a first conductivity type GaAs emitter cap layer or an InGaAs emitter cap layer formed thereon to reduce the ohmic contact resistance of the AlGaAs emitter layer. The semiconductor device according to claim 1, wherein the sub-collector layer includes one or more planar doped layers doped with selenium (Se) or silica (Si).