JP2001229674A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2001229674A5 JP2001229674A5 JP2000337241A JP2000337241A JP2001229674A5 JP 2001229674 A5 JP2001229674 A5 JP 2001229674A5 JP 2000337241 A JP2000337241 A JP 2000337241A JP 2000337241 A JP2000337241 A JP 2000337241A JP 2001229674 A5 JP2001229674 A5 JP 2001229674A5
- Authority
- JP
- Japan
- Prior art keywords
- clock
- circuit
- misfet
- semiconductor device
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 claims 41
- 239000004065 semiconductor Substances 0.000 claims 19
- 239000003990 capacitor Substances 0.000 claims 4
- 230000000630 rising effect Effects 0.000 claims 4
- 230000001066 destructive effect Effects 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000337241A JP4111304B2 (ja) | 1999-12-08 | 2000-10-31 | 半導体装置 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34840599 | 1999-12-08 | ||
| JP11-348405 | 1999-12-08 | ||
| JP2000337241A JP4111304B2 (ja) | 1999-12-08 | 2000-10-31 | 半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006304652A Division JP4650900B2 (ja) | 1999-12-08 | 2006-11-10 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001229674A JP2001229674A (ja) | 2001-08-24 |
| JP2001229674A5 true JP2001229674A5 (enrdf_load_stackoverflow) | 2005-07-21 |
| JP4111304B2 JP4111304B2 (ja) | 2008-07-02 |
Family
ID=26578737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000337241A Expired - Fee Related JP4111304B2 (ja) | 1999-12-08 | 2000-10-31 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4111304B2 (enrdf_load_stackoverflow) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004171678A (ja) * | 2002-11-20 | 2004-06-17 | Sony Corp | 情報記憶装置、情報記憶方法、及び情報記憶プログラム |
| JP2006092640A (ja) | 2004-09-24 | 2006-04-06 | Sanyo Electric Co Ltd | メモリ |
| JP4672341B2 (ja) * | 2004-11-22 | 2011-04-20 | 株式会社東芝 | 半導体記憶装置 |
| JP4753637B2 (ja) | 2005-06-23 | 2011-08-24 | パトレネラ キャピタル リミテッド, エルエルシー | メモリ |
| JP4362573B2 (ja) | 2005-07-28 | 2009-11-11 | パトレネラ キャピタル リミテッド, エルエルシー | メモリ |
| US7733681B2 (en) | 2006-04-26 | 2010-06-08 | Hideaki Miyamoto | Ferroelectric memory with amplification between sub bit-line and main bit-line |
| CN101089992B (zh) * | 2006-06-16 | 2012-09-05 | 帕特兰尼拉财富有限公司 | 存储器 |
| JP4272227B2 (ja) | 2006-06-16 | 2009-06-03 | 三洋電機株式会社 | メモリおよび制御装置 |
| JP4195899B2 (ja) * | 2006-06-16 | 2008-12-17 | 三洋電機株式会社 | 強誘電体メモリ |
-
2000
- 2000-10-31 JP JP2000337241A patent/JP4111304B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI514416B (zh) | 記憶胞以及動態記憶體陣列 | |
| JP3140461B2 (ja) | ランダム・アクセス・メモリ | |
| US9281047B2 (en) | Dynamic random access memory with fully independent partial array refresh function | |
| US6381188B1 (en) | DRAM capable of selectively performing self-refresh operation for memory bank | |
| US8295101B2 (en) | Semiconductor device | |
| JP4632114B2 (ja) | 半導体集積回路装置 | |
| US6728157B2 (en) | Semiconductor memory | |
| JP2012022751A (ja) | 半導体装置 | |
| US6879540B2 (en) | Synchronous semiconductor memory device having dynamic memory cells and operating method thereof | |
| JP2003257178A (ja) | 半導体メモリ装置 | |
| US4873672A (en) | Dynamic random access memory capable of fast erasing of storage data | |
| JP2000156079A (ja) | マルチバンク構造を有する半導体メモリ装置 | |
| CN101809668A (zh) | 用于在高速动态随机存取存储器中处理信号的系统及方法 | |
| US6657920B2 (en) | Circuit for generating internal address in semiconductor memory device | |
| JP2001229674A5 (enrdf_load_stackoverflow) | ||
| US7548485B2 (en) | Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof | |
| US6339560B1 (en) | Semiconductor memory based on address transitions | |
| JPH10222977A (ja) | 半導体メモリ装置の隔離ゲート制御方法及び回路 | |
| US7835180B2 (en) | Semiconductor memory device | |
| US6570799B1 (en) | Precharge and reference voltage technique for dynamic random access memories | |
| US6693838B2 (en) | Semiconductor memory device equipped with refresh timing signal generator | |
| US20100110747A1 (en) | Semiconductor memory device | |
| US7283421B2 (en) | Semiconductor memory device | |
| JPH07192461A (ja) | 半導体記憶装置 | |
| JP4060527B2 (ja) | クロック同期型ダイナミックメモリ |