JP2001210674A - Mounting method of bare chip ic - Google Patents
Mounting method of bare chip icInfo
- Publication number
- JP2001210674A JP2001210674A JP2000024683A JP2000024683A JP2001210674A JP 2001210674 A JP2001210674 A JP 2001210674A JP 2000024683 A JP2000024683 A JP 2000024683A JP 2000024683 A JP2000024683 A JP 2000024683A JP 2001210674 A JP2001210674 A JP 2001210674A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- chip
- wiring board
- mounting
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、同じボンディング
パット座標を持つ2個以上のベアチップICを、AFC
等を接続媒体としてある一定の加重をベアチップICに
加えて配線基板に接続するフリップチップ方式のベアチ
ップ実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to two or more bare chip ICs having the same bonding pad coordinates.
The present invention relates to a flip chip type bare chip mounting method in which a certain load is applied to a bare chip IC using the same as a connection medium and connected to a wiring board.
【0002】[0002]
【従来の技術】フリップチップ実装は、ベアチップIC
を直接配線基板に接続するため高密度実装には非常に有
利である。2. Description of the Related Art Flip chip mounting is a bare chip IC.
Is directly connected to the wiring board, which is very advantageous for high-density mounting.
【0003】又、フリップチップ実装方法で工数が比較
的簡単に行う方法の一つに、ベアチップのボンディング
パットにスタットバンプ等によりの凸を設け、ベアチッ
プICと基板との間に、ACF、導電性ペースト等の接
続媒体介して配置し、さらに上記配置したベアチップI
Cのボンディングパットにある一定の加重をある一定時
間加えて上記ベアチップICと配線基板を接続する方法
がある。[0003] One of the flip-chip mounting methods in which the man-hour is relatively simple is to provide a projection such as a stat bump on a bonding pad of a bare chip, and to provide an ACF and a conductive material between the bare chip IC and the substrate. The bare chip I arranged via a connection medium such as paste and further arranged as described above
There is a method of connecting the bare chip IC and the wiring board by applying a certain weight to the bonding pad of C for a certain time.
【0004】ただし上記方法の場合、ベアチップICを
加圧する際、ベアチップICと基板を均一に加圧する必
要があるため上記ベアチップICが実装される基板の裏
面には実装部品は実装せず平坦にする必要がある。However, in the case of the above method, when the bare chip IC is pressed, the bare chip IC and the substrate need to be uniformly pressed. Therefore, the mounting component is not mounted on the back surface of the substrate on which the bare chip IC is mounted, and is flattened. There is a need.
【0005】そのため、複数のベアチップICを実装す
る場合は、ベアチップICの実装は、実装面を統一する
のが一般てきである。For this reason, when a plurality of bare chip ICs are mounted, the mounting surface of the bare chip IC is generally unified.
【0006】日経マイクロデバイス1997年5月号に
掲載されたMCM実施例は、5個のベアチップICを実
装した例であるが、ベアチップICの実装面は同一面に
統一している。The MCM embodiment described in the May 1997 issue of Nikkei Microdevices is an example in which five bare chip ICs are mounted, but the mounting surfaces of the bare chip ICs are unified on the same surface.
【0007】[0007]
【発明が解決しようとする課題】上記フリップチップ実
装方式でベアチップICをフリッチップ実装を行う回路
基板において、さらに実装密度を上げる場合は、配線基
板の実装面積を有効に使うために、ベアチップICを実
装する配線基板の表裏両面にベアチップICを実装する
必要がある。In a circuit board on which bare chip ICs are flip-chip mounted by the above-described flip chip mounting method, when the mounting density is to be further increased, the bare chip ICs are mounted in order to effectively use the mounting area of the wiring board. It is necessary to mount bare chip ICs on both the front and back surfaces of the wiring board to be formed.
【0008】しかし、配線基板の両面にベアチップIC
を実装する場合のベアチップIC実装工程は、ベアチッ
プICのボンディングパットに均一に加圧する必要があ
るため、各々のベアチップIC実装面毎にフリップチッ
プ実装工程が必要になり、ベアチップ実装工程が増加す
る問題がある。However, bare chip ICs are provided on both sides of the wiring board.
In the bare chip IC mounting process when mounting a chip, it is necessary to uniformly apply pressure to the bonding pad of the bare chip IC, so a flip chip mounting process is required for each bare chip IC mounting surface, and the bare chip mounting process increases. There is.
【0009】本発明の目的は、同じボンディングパット
座標を持つ2個以上のベアチップICを搭載する回路基
板において、ベアチップ実装工程を大きく増加する事無
く、回路基板の表面裏面の両面の実装エリアにベアチッ
プICを実装すことが出来るため、大きな工数の増加す
る事無く2個以上のベアチップICを高密度に実装でき
る効果がある。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit board on which two or more bare chip ICs having the same bonding pad coordinates are mounted, without significantly increasing the number of steps for mounting the bare chip, in the mounting areas on both surfaces of the front and back surfaces of the circuit board. Since the IC can be mounted, there is an effect that two or more bare chip ICs can be mounted at high density without increasing the number of man-hours.
【0010】[0010]
【課題を解決するための手段】上記目的を達成するため
本発明では、配線基板の表面裏面の両面に同じボンディ
ングパット座標を持つベアチップICを実装し、かつ表
面に実装したベアチップICのボンディングパット位置
と、裏面に配置したベアチップICのボンディングパッ
ト位置とが配線基板を介して向かい合わせになる様にベ
アチップICを配置し、フリップチップボンディングの
際の加圧は、一回の加圧で裏面に配置したベアチップI
Cと表面に配置したベアチップICの間に前記ベアチッ
プICを実装する絶縁基板が間にはさみ込まれた状態
で、表面に配置したベアチップICと裏面に配置したベ
アチップICとの間で加圧しフリップチップ実装を行う
ため工数の増加する事無く、上記ベアチップICを回路
基板に均一に加圧することができ、回路基板の両面にベ
アチップICを実装することが出来る。According to the present invention, a bare chip IC having the same bonding pad coordinates is mounted on both the front and back surfaces of a wiring substrate, and the bonding pad position of the bare chip IC mounted on the front surface is provided. The bare chip IC is arranged so that the bonding pad position of the bare chip IC arranged on the back surface is opposed to the bonding pad position via the wiring board, and the pressure during flip chip bonding is arranged on the back surface with one press Bare chip I
In a state where the insulating substrate for mounting the bare chip IC is sandwiched between C and the bare chip IC arranged on the front surface, a flip chip is pressed between the bare chip IC arranged on the front surface and the bare chip IC arranged on the back surface. Since the mounting is performed, the bare chip IC can be uniformly pressed onto the circuit board without increasing the number of steps, and the bare chip IC can be mounted on both sides of the circuit board.
【0011】[0011]
【発明の実施の形態】以下、本発明の複合配線基板実装
方法を用いたACF方式のフリップチップ実装の一実施
例をを図1〜図3により説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of flip chip mounting of the ACF system using the composite wiring board mounting method of the present invention will be described below with reference to FIGS.
【0012】ACF工法は、ベアチップICと接続する
配線基板との接続はACFに熱を加えながらベアチップ
ICと基板に加圧することで接続するのが一般的であ
る。In the ACF method, the connection between the bare chip IC and the wiring board is generally performed by applying pressure to the bare chip IC and the substrate while applying heat to the ACF.
【0013】図1は、本発明によるベアチップICを実
装配置した回路基板の断面図を示す。FIG. 1 is a sectional view of a circuit board on which a bare chip IC according to the present invention is mounted and arranged.
【0014】図2は、図1で配線基板に配置したベアチ
ップICを接続を行う方法を示す。図3は、図1で配線
基板に配置したベアチップICを図2の方式で接続を行
い完成した回路基板を示す。FIG. 2 shows a method for connecting bare chip ICs arranged on the wiring board in FIG. FIG. 3 shows a completed circuit board obtained by connecting the bare chip ICs arranged on the wiring board in FIG. 1 in the manner shown in FIG.
【0015】図1において、ガラエポ基板、セラミック
基板などの絶縁基板5に配線パターン3を形成した配線
基板に接続媒体であるACFテープ4、4’を表面裏面
にそれぞれ貼り付け、同じボンディングパット座標を持
つベアチップIC1、1’にスタットバンプ2、2’を
設けたベアチップICを配線基板の裏側、表側に配線基
板を介して向い合わせになる様に配置する。In FIG. 1, ACF tapes 4 and 4 'as connection media are attached to a wiring substrate having a wiring pattern 3 formed on an insulating substrate 5 such as a glass epoxy substrate, a ceramic substrate or the like, and the same bonding pad coordinates are set. The bare chip ICs having the stat bumps 2 and 2 ′ provided on the bare chip ICs 1 and 1 ′ are arranged on the back side and the front side of the wiring board so as to face each other via the wiring board.
【0016】上記の様に配線基板に対してそれぞれ表裏
面に同じボンディングパット座標を持つベアチップIC
が向い合わせになる様に配置すると配線基板とベアチッ
プICを接続するための加圧力は表面に設けたベアチッ
プIC1に設けたスタットバンプ2と裏面に設けたベア
チップIC1’に設けたスタットバンプ2’との間に挟
みこまれた配線基板の間で加重される。As described above, the bare chip IC having the same bonding pad coordinates on the front and back surfaces with respect to the wiring board, respectively.
Are arranged so as to face each other, the pressing force for connecting the wiring board and the bare chip IC is equal to the stat bump 2 provided on the bare chip IC 1 provided on the front surface and the stat bump 2 'provided on the bare chip IC 1' provided on the back surface. It is weighted between the wiring boards sandwiched between them.
【0017】図2において、予めACF接続するために
加温したステージ6に図1で配線基板に配置したベアチ
ップICの表面又は裏面に設置したベアチップICの背
面が合わさる様に設置し、前記ステージ6に図1で配線
基板に配置したベアチップICの表面又は裏面に設置し
たベアチップICの背面の反対面からは、加温装置付き
加圧プレス装置7を配置し、ある一定の加重を加えてる
ことで、図1で配線基板に配置した表面のベアチップI
C1と裏面に配置したベアチップIC1’の両側から加
温しながらある一定の加重で加圧することにより配線基
板と表面に配置したベアチップICと裏面に配置したベ
アチップICをフリップチップ実装することが出来る。In FIG. 2, the stage 6 is pre-heated for ACF connection so that the front surface of the bare chip IC placed on the wiring board in FIG. In FIG. 1, a pressurizing press device 7 with a heating device is arranged from the surface opposite to the back surface of the bare chip IC placed on the front surface or the back surface of the bare chip IC placed on the wiring substrate in FIG. , Bare chip I on the surface arranged on the wiring board in FIG.
By applying pressure with a certain load while heating from both sides of C1 and the bare chip IC 1 'arranged on the back surface, the bare chip IC arranged on the wiring substrate and the front surface and the bare chip IC arranged on the back surface can be flip-chip mounted.
【0018】図3に図1で配線基板に配置したベアチッ
プICを図2方法でフリップチップ実装を行い本発明の
手法により完成した回路基板を示す。FIG. 3 shows a circuit board completed by the method of the present invention by flip-chip mounting the bare chip IC arranged on the wiring board in FIG. 1 by the method of FIG.
【0019】上記実装方法で同じボンディングパット座
標を持つベアチップICを2個以上実装する回路基板に
おいて、大きな工数の増加する事無く配線基板の両面に
ベアチップICをフリップチップ実装できる。In a circuit board on which two or more bare chip ICs having the same bonding pad coordinates are mounted by the above mounting method, the bare chip ICs can be flip-chip mounted on both sides of the wiring board without increasing the number of steps.
【0020】[0020]
【発明の効果】以上述べたように本発明の方法によれ
ば、前記同じボンディングパット座標を持つベアチップ
ICを2個以上実装する回路基板において、工数を大き
く増加する事無く、同じボンディングパット座標を持つ
ベアチップICを回路基板の両面に実装できるため、高
密度な回路基板を提供できる。As described above, according to the method of the present invention, in a circuit board on which two or more bare chip ICs having the same bonding pad coordinates are mounted, the same bonding pad coordinates can be used without greatly increasing the number of steps. Since the bare chip IC can be mounted on both sides of the circuit board, a high-density circuit board can be provided.
【図1】本発明によるベアチップIC配線基板の表面裏
面の両面に実装した回路基板の断面図である。FIG. 1 is a cross-sectional view of a circuit board mounted on both front and back surfaces of a bare chip IC wiring board according to the present invention.
【図2】図1を接続する装置に配置した回路基板及び接
続装置の断面図である。FIG. 2 is a cross-sectional view of a circuit board and a connection device arranged in the device for connecting FIG. 1;
【図3】本発明により完成した回路基板の断面図であ
る。FIG. 3 is a sectional view of a circuit board completed according to the present invention.
1・1’…同じベアチップパット座標をもつベアチップ
IC、2・2’…スタットバンプ、3・3’…配線パタ
ーン、4・4’…ACF、5…絶縁基板、6…フリップ
チップ用実装用ステージ、7…フリップチップ用加圧プ
レス装置。1, 1 ': bare chip IC having the same bare chip pad coordinates, 2, 2': stat bump, 3, 3 ': wiring pattern, 4, 4': ACF, 5: insulating substrate, 6: mounting stage for flip chip , 7 ... Pressing press device for flip chip.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 村松 盛生 茨城県ひたちなか市大字稲田1410番地 株 式会社日立製作所デジタルメディア製品事 業部内 Fターム(参考) 5E336 AA04 AA14 BB02 BC31 CC31 CC58 EE05 EE07 5F044 KK10 LL07 LL09 PP15 PP19 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Morio Muramatsu 1410 Inada, Hitachinaka City, Ibaraki Pref. Digital Media Products Division, Hitachi, Ltd. F-term (reference) 5E336 AA04 AA14 BB02 BC31 CC31 CC58 EE05 EE07 5F044 KK10 LL07 LL09 PP15 PP19
Claims (1)
基板上に、同じボンディングパット座標を持つ2個以上
のベアチップICをACF等を接続媒体として、ある一
定の加重をベアチップICに加えて上記配線基板に押し
て付けてベアチップ実装を行うフリップチップ実装方式
の実装方法において、前記同じボンディングパット座標
を持つ前記2個以上のベアチップICの実装面を前記配
線基板の表裏に配置し、かつ、表面に実装したベアチッ
プICのボンディングパット位置と、裏面に配置したベ
アチップICのボンディングパット位置とが配線基板を
介して向かい合わせになる様にベアチップICを配置
し、フリップチップボンディングの際の加圧は、一回の
加圧で裏面に配置したベアチップICと表面に配置した
ベアチップICの間に前記ベアチップICを実装する絶
縁基板が間にはさみ込まれた状態で、表面に配置したベ
アチップICと裏面に配置したベアチップICとの間で
加圧しフリップチップ実装を行うことを特徴とするベア
チップICの実装方法。1. A wiring board comprising: a wiring pattern formed on an insulating substrate; two or more bare chip ICs having the same bonding pad coordinates; In a flip-chip mounting method in which a bare chip is mounted by pressing against a substrate, the mounting surfaces of the two or more bare chip ICs having the same bonding pad coordinates are arranged on the front and back surfaces of the wiring board and mounted on the front surface. The bare chip IC is arranged so that the bonding pad position of the bare chip IC and the bonding pad position of the bare chip IC arranged on the back face face each other via the wiring board, and the pressure during flip chip bonding is once. Between the bare chip IC placed on the back side and the bare chip IC placed on the front side by pressing In a state where the insulating substrate on which the bare chip IC is mounted is sandwiched therebetween, a flip chip mounting is performed by applying pressure between the bare chip IC arranged on the front surface and the bare chip IC arranged on the back surface. Implementation method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000024683A JP2001210674A (en) | 2000-01-28 | 2000-01-28 | Mounting method of bare chip ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000024683A JP2001210674A (en) | 2000-01-28 | 2000-01-28 | Mounting method of bare chip ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001210674A true JP2001210674A (en) | 2001-08-03 |
Family
ID=18550627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000024683A Pending JP2001210674A (en) | 2000-01-28 | 2000-01-28 | Mounting method of bare chip ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001210674A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100462993B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
KR100462992B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
JP2006319266A (en) * | 2005-05-16 | 2006-11-24 | Toshiba Corp | Semiconductor device |
-
2000
- 2000-01-28 JP JP2000024683A patent/JP2001210674A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100462993B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
KR100462992B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
JP2006319266A (en) * | 2005-05-16 | 2006-11-24 | Toshiba Corp | Semiconductor device |
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