JPS6360540A - Manufacture of connecting terminal - Google Patents
Manufacture of connecting terminalInfo
- Publication number
- JPS6360540A JPS6360540A JP61205689A JP20568986A JPS6360540A JP S6360540 A JPS6360540 A JP S6360540A JP 61205689 A JP61205689 A JP 61205689A JP 20568986 A JP20568986 A JP 20568986A JP S6360540 A JPS6360540 A JP S6360540A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- conductive resin
- connecting terminal
- laser
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000010355 oscillation Effects 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子上の接続端子と基板上に形成した
配線パターン上の突起電極（以下バンブと呼称）の接続
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to connection between connection terminals on a semiconductor element and protruding electrodes (hereinafter referred to as bumps) on a wiring pattern formed on a substrate.
近年、液晶ディスプレイや、コンピューター。 In recent years, liquid crystal displays and computers.
工Ｃカードなどの小型で高信頼性を要求される分野では
、フリップチップ法やテープキャリア法というワイヤボ
ンディングを用いない実装方法が使用されるようになっ
てきた。In fields such as industrial C cards that require small size and high reliability, mounting methods that do not use wire bonding, such as the flip chip method and tape carrier method, have come to be used.
前記テープキャリア方式やフリップチップ方式のいずれ
も半導体素子上の接続端子と基板上に形成した配線パタ
ーン上の突起１ＪＬ極とを位置合わせし、加熱圧着せし
め、該半導体素子上の接続端子を構成する金属と該突起
電極を構成する金属とを共晶させて接続を行なっていた
。In both the tape carrier method and the flip-chip method, the connection terminals on the semiconductor element are aligned with the protrusion 1JL poles on the wiring pattern formed on the substrate, and the connection terminals on the semiconductor element are formed by heat and pressure bonding. The connection was made by eutecticizing the metal and the metal constituting the protruding electrode.
しかし、従来技術では液晶パネルのように同一回路基板
上に複数の半導体素子を実装しようとした場合、テープ
キャリア方式においてはテープキャリアが基板からはみ
出し実装面積が大きくない、また不良素子が出た場合は
テープ一体で交換するためコスト高となる。また、フリ
ップチップ方式では半導体素子は基板に金属の共晶によ
り接続されているため、不良素子があった場合、交換し
ようとすると基板上の配線パターンまで損μｓを与える
ため使用できなくなり、基板の歩留シの低下を引き起し
、コスト高の原因となる。この対策として接合に金属粒
子を分散させた導電性樹脂を使用すれば、接合後加熱す
ることにより配線パターンに損傷を与えることなく容易
に取り外しができ不良素子の交換が可能となる。However, with conventional technology, when trying to mount multiple semiconductor elements on the same circuit board like a liquid crystal panel, in the tape carrier method, the tape carrier protrudes from the board and the mounting area is not large, or if a defective element occurs. The cost is high because the tape must be replaced as a whole. In addition, in the flip-chip method, semiconductor elements are connected to the substrate by metal eutectic, so if you try to replace a defective element, it will damage the wiring pattern on the board, making it unusable. This causes a decrease in yield and increases costs. As a countermeasure to this problem, if a conductive resin in which metal particles are dispersed is used for bonding, the wiring pattern can be easily removed by heating after bonding, and defective elements can be replaced.
しかしながら、上記樹脂を基板全体に塗布すると配線パ
ターン間でのショートや半導体素子のエツジショートを
引き起こすという問題点を有するそこで本発明は、この
ような問題点を解決するもので、その目的とするところ
は、半導体素子の交換が容易に可能な接合方法を提供す
るところにある。However, when the resin is applied to the entire board, there is a problem in that it causes short circuits between wiring patterns and edge shorts in semiconductor elements.The present invention is intended to solve these problems. The object of the present invention is to provide a bonding method that allows semiconductor elements to be easily replaced.
本発明の接続端子の製造方法は、半導体素子上の接続端
子と基板上に形成した配線パターン上の複数の突起電極
の接合に導電性樹脂を使用することにおいて、該接続端
子及び突起電極のいずれか一方又は両方に導電性樹脂を
レーザー尤を熱源として熱転写することを特徴とする。The method for manufacturing a connecting terminal of the present invention includes using a conductive resin to bond a connecting terminal on a semiconductor element and a plurality of protruding electrodes on a wiring pattern formed on a substrate. It is characterized by thermally transferring a conductive resin onto one or both of them using a laser as a heat source.
以下、本発明について実施例に基づき詳細に説明する。 Hereinafter, the present invention will be described in detail based on examples.
第１図は、本発明の実施例を工程順に示した図である。FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps.
まずα図の如く、突起電極付き配線パターン（２）の付
いた基板（１）に４電性フイルム（５）を載せる。この
時の導電性樹脂フィルムの特性を第１表に示す。又、フ
ィルム厚は１５μである。次にｂ図の如くバンプ部のみ
にレーザｙｔ、（４）を照射する。この時のレーザは発
振波長が１．０６μのセグレーザを使用した。またレー
ザ光の横モードはガウスモードでビーム径は８０μであ
る。次に０図の如く導電性樹脂フィルムを剥すとｄ図の
如くバンプ部のみに樹脂が塗布される。First, as shown in figure α, a tetraelectric film (5) is placed on a substrate (1) having a wiring pattern (2) with protruding electrodes. Table 1 shows the properties of the conductive resin film at this time. Further, the film thickness is 15μ. Next, as shown in figure b, only the bump portion is irradiated with laser yt, (4). The laser used at this time was a Seg laser with an oscillation wavelength of 1.06μ. Further, the transverse mode of the laser beam is a Gaussian mode, and the beam diameter is 80μ. Next, when the conductive resin film is peeled off as shown in Figure 0, the resin is applied only to the bump portions as shown in Figure d.
次に０図の如く半導体素子（５）を７リツプチツプ方式
により熱圧着して接合した。この時の温度は１８０℃、
圧力は１０ＫＰ／−で時間は１５秒である。Next, as shown in Figure 0, the semiconductor element (5) was bonded by thermocompression bonding using the 7-lip chip method. The temperature at this time was 180℃,
The pressure is 10 KP/- and the time is 15 seconds.
また、半導体素子上の電極にも同様の方法により導電性
樹脂を塗布し、突起ｖ４極付き配線パターンの付いた基
板に７リツプチツプ方式により上記と同様の条件で熱圧
着して接合した。Further, conductive resin was applied to the electrodes on the semiconductor element by the same method, and the electrodes were bonded by thermocompression bonding under the same conditions as above to a substrate having a wiring pattern with 4 protruding poles using the 7-rip-chip method.
明細書の浄さく内容に変更なし）
＠ １ 表
〔発明の効果〕
上述の如く本発明によれば、半導体素子上の接続端子と
基板上に形成した配線パターン上の俣敢の突起’＋Ｊ極
の接合に導電性樹脂を使用することにおいて、該接続端
子及び該突起正極のいずれか一方又は両方に導電性樹脂
をレーザ光を使用して熱転写することにより選択的に塗
布することが可能となり、また、配線パターンへ半導体
素子を接合した後不良素子があった場合、ＤＯ熱するだ
けで容易に取り外しができ新しいチップと交換が可能と
なり、今まで不良素子があった場合基板全体を廃棄して
いた時と比較して大巾なコストダウンが可能となる効果
を有する。(No change to the content of the specification) @ 1 Table [Effects of the invention] As described above, according to the present invention, the connecting terminal on the semiconductor element and the protrusion '+J pole on the wiring pattern formed on the substrate In using a conductive resin for bonding, it becomes possible to selectively apply the conductive resin to either or both of the connecting terminal and the protruding positive electrode by thermally transferring the conductive resin using a laser beam, Additionally, if there is a defective element after bonding the semiconductor element to the wiring pattern, it can be easily removed by simply applying DO heat and replaced with a new chip.Until now, if there was a defective element, the entire board had to be discarded. This has the effect of making it possible to significantly reduce costs compared to the previous model.
また、樹脂により接合しているため、従来基板と半導体
素子の熱膨張係数の違いにより光生じていた半導体素子
の四すみの′成極での破断も見られないため半導体素子
装着後の基板の不良率も大巾に低減された。In addition, since the bond is made with resin, there is no damage caused by polarization at the four corners of the semiconductor element, which conventionally occurs due to the difference in thermal expansion coefficient between the substrate and the semiconductor element. The defective rate was also significantly reduced.
第１図（α）〜（、ａ）は本発明接続端子の製造工程図
を示す。
１・・・・・・基 板
２・・・・・・突起電極付き配線パターン３・・・・・
・導電性樹脂フィルム
４・・・・・・レーザー尤
５・・・・・・半導体素子
以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 最上 務（他１名ｙ−”＝第１図
丁続補正書（方式〕
昭和 ６１年１２月１６０
２発明の名（６、
接続端子の製造方法
ま 補正をする者
４ （、、□ い 代表取締役 玉 部 一
部゛ −
＆／浦止の１を争FIGS. 1(α) to 1(a) show manufacturing process diagrams of the connecting terminal of the present invention. 1... Board 2... Wiring pattern with protruding electrodes 3...
・Conductive resin film 4...Laser layer 5...Semiconductor element and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Tsutomu Mogami (and 1 other person) Written amendment (method) December 1986 160 2. Name of the invention (6. Method for manufacturing connection terminals) Person making the amendment 4 (,,□ Representative Director Tamabe Part ゛ - &/ Uradome disputes 1)
Claims (2)
パターン上の複数の突起電極の接合に導電性樹脂を使用
した接続端子の製造方法において、該接続端子及び該突
起電極のいずれか一方又は両方に導電性樹脂を熱転写す
ることを特徴とする接続端子の製造方法。(1) In a method for manufacturing a connecting terminal in which a conductive resin is used to bond a connecting terminal on a semiconductor element and a plurality of protruding electrodes on a wiring pattern formed on a substrate, one of the connecting terminal and the protruding electrode Or a method for manufacturing a connecting terminal, characterized by thermally transferring a conductive resin to both.
とを特徴とする特許請求の範囲第１項記載の接続端子の
製造方法。(2) The method for manufacturing a connecting terminal according to claim 1, characterized in that a laser beam is used as a heat source in the transfer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61205689A JPS6360540A (en) | 1986-09-01 | 1986-09-01 | Manufacture of connecting terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61205689A JPS6360540A (en) | 1986-09-01 | 1986-09-01 | Manufacture of connecting terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6360540A true JPS6360540A (en) | 1988-03-16 |
Family
ID=16511076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61205689A Pending JPS6360540A (en) | 1986-09-01 | 1986-09-01 | Manufacture of connecting terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6360540A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0758145A3 (en) * | 1995-08-08 | 1997-11-19 | Taiyo Yuden Co., Ltd. | Method of manufacturing circuit module |
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| JP2007110050A (en) * | 2005-10-17 | 2007-04-26 | Namics Corp | Bump forming method |
-
1986
- 1986-09-01 JP JP61205689A patent/JPS6360540A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0758145A3 (en) * | 1995-08-08 | 1997-11-19 | Taiyo Yuden Co., Ltd. | Method of manufacturing circuit module |
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| JP2007110050A (en) * | 2005-10-17 | 2007-04-26 | Namics Corp | Bump forming method |
| JP4684843B2 (en) * | 2005-10-17 | 2011-05-18 | ナミックス株式会社 | Bump formation method |
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