JP2004128259A - Joint structure and electronic equipment equipped with the same - Google Patents

Joint structure and electronic equipment equipped with the same Download PDF

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Publication number
JP2004128259A
JP2004128259A JP2002291108A JP2002291108A JP2004128259A JP 2004128259 A JP2004128259 A JP 2004128259A JP 2002291108 A JP2002291108 A JP 2002291108A JP 2002291108 A JP2002291108 A JP 2002291108A JP 2004128259 A JP2004128259 A JP 2004128259A
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Prior art keywords
substrate
organic material
electronic component
structure
bumps
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JP2002291108A
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Japanese (ja)
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Yasushi Takeuchi
竹内 靖
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Canon Inc
キヤノン株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To improve connection reliability by reducing a uniform load and providing a mounting connection structure which is free of bending and a recess when an electronic component and a substrate are pressed and electrically connected by using an organic material. <P>SOLUTION: On the organic material represented by an ACF, a structure member is previously arranged at a position corresponding to between bumps of electronic components and electrodes of the substrate, and pressed and joined. In such constitution, the structure member is present between the bumps of the electronic components and electrodes of the substrate, so a structure having columns formed between the bumps and electrodes by pressure application is obtained to reduce the uniform load, and consequently a join having neither flexure nor a recess is obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、電子部品と基板、電子部品と電子部品、基板と基板の接合構造に係り、接合部の高信頼性を図る手法に関する。 The present invention relates to an electronic component and the substrate, the electronic component and the electronic component, relates to a joint structure of the substrate and the substrate, to techniques to improve the reliability of the joint.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
電子部品を異方導電性フィルム(ACF)、異方導電性ペースト(ACP)、非導電性フィルム(NCF)、非導電性ペースト(NCP)に代表される熱硬化性有機材料、あるいは光硬化性有機材料を用いて基板に接合する場合、前記フィルムを電子部品と基板の間に挟んで加熱、加圧接合、光照射、加圧接合を行い電気的に接続していた。 Electronic components an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), non-conductive film (NCF), thermosetting organic material typified by a non-conductive paste (NCP) or photocurable, If bonded to the substrate using an organic material, the film heating is interposed between an electronic component and substrate, pressure bonding, light irradiation, was electrically connected perform pressure bonding.
【0003】 [0003]
有機材料を加熱、加圧接合する場合や光照射、加圧して電子部品と基板を接合する場合、電子部品のバンプと基板の電極間の有機材料を流動排出させて電子部品のバンプと基板の電極を相互に接触させ、バンプと電極間に有機材料を残さずに有機材料の接着力により電子部品と基板を電気的に接続する構造としていた。 The organic material heating, or when the light irradiation for bonding pressure, when bonding the electronic component and the substrate under pressure, the electronic component of the bumps and the substrate between the electrodes and the organic material was fluidized discharge of electronic components bumps and the substrate electrodes mutually contacting, and the electronic part and the substrate had a structure for electrically connecting the adhesion of the organic material without leaving organic material between the bumps and electrodes.
【0004】 [0004]
さらに、電子部品と基板の加圧接合時に等分布荷重を低減するために、電子部品や基板上に本来の電気的接続以外の目的でダミーのバンプと電極を形成し、接合後に電子部品や基板の部分的撓みや凹みを低減すると同時に、接合部の信頼性向上を図っていた(例えば、特許文献1参照)。 Furthermore, in order to reduce to a uniformly distributed load when the pressure bonding of the electronic component and the substrate, the electronic components and to form a dummy bump and the electrode for the purpose for non-electrical connections on the substrate, the electronic component and the substrate after bonding at the same time reducing the partial deflection or dents and is aimed to improve the reliability of the joint portion (for example, see Patent Document 1).
【0005】 [0005]
【特許文献1】 [Patent Document 1]
特開平9−68715号公報【0006】 Japanese Unexamined Patent Publication No. 9-68715 [0006]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら上記従来例では、電子部品や基板にダミーのバンプや電極を形成するため、電子部品上に部品の機能とは関係ないエリアを設ける必要があり、電子部品や基板が大きくなりコストが上昇するという問題があった。 However, in the above prior art, in order to form an electronic component and a substrate in the dummy bumps or electrodes, it is necessary to provide an area not related to the functions of the components on the electronic component, the electronic component and the substrate is cost increases greatly there is a problem in that.
【0007】 [0007]
又、電子部品や基板にダミーのバンプや電極を形成する自由度が低い場合は、接合時に等分布荷重が低減されず部分的撓みや凹みが発生し、電子部品のバンプや基板の電極の塑性変形量がばらついた状態で接合され、最悪の場合電子部品と基板の電気接合部が剥離して電気的にオープンになるという問題があった。 Further, if a low degree of freedom for forming the dummy bump and the electrode on the electronic component and the substrate, uniform load is reduced without partial deflection or dents are generated at the time of joining, the electronic components of bumps or substrate electrodes plastically are joined in a state where the deformation amount varies, the electrical junction worst case the electronic component and the substrate has a problem that it becomes electrically open by peeling.
【0008】 [0008]
本発明は上記の問題点を解決する為になされたもので、電子部品を有機材料を挟んで基板に加熱、加圧接合する場合や、光照射、加圧接合する場合に、電子部品や基板にダミーバンプや電極を形成することなく電子部品と基板の接合信頼性向上を図るとともに、コスト上昇を抑える接合構造とこの接合構造を備えた電子機器を提供することを目的とする。 The present invention has been made in order to solve the problems described above, heating the electronic components on a substrate by sandwiching an organic material, and when bonding pressure, light irradiation, when the bonding pressure, the electronic component and the substrate strive to bonding reliability of the electronic component and the substrate without forming the dummy bump and electrode, and an object thereof is to provide an electronic apparatus having the junction structure and the joining structure to suppress the cost increase.
【0009】 [0009]
【課題を解決するための手段】 In order to solve the problems]
上記目的を達成する為本出願に係る第1の発明は、電子部品と基板を加熱、加圧接合する有機材料中に、電子部品のバンプや基板の電極間に位置するように構造部材を設けたことを特徴とする。 First invention of the present application to achieve the above object, heating the electronic component and the substrate, the organic material to be joined under pressure, provided the structural member so as to be positioned between the electronic component bumps or substrate electrodes characterized in that was. 特に電子部品のバンプと基板の電極の接続点同士が離れている場合に構造部材を設けると効果が大きい。 Particularly great effect when providing the structural member when the connection point between the electronic components of the bumps and the electrodes of the substrate are separated.
【0010】 [0010]
上記構成において、有機材料中に配置した構造部材がバンプ間、電極間に存在するので、電子部品と基板を加熱、加圧接合する場合や、光照射、加圧接合する場合に構造部材による支柱が形成されるので等分布荷重が著しく低減される。 In the above configuration, among the structural members disposed in the organic material bumps, as there between the electrodes, heating the electronic component and the substrate, and when bonding pressure, the strut due to the structural member when the light irradiation, bonding pressure uniformly distributed load is significantly reduced because There is formed.
【0011】 [0011]
従って、電子部品や基板に撓みや凹みが発生し難い接合構造となり、バンプと電極の塑性変形量のばらつきが低減され、電子部品と基板との電気接合部の剥離は発生しない。 Thus, deflection and dents on the electronic component and the substrate becomes difficult junction structure occurs, variation in the plastic deformation of the bump and the electrode is reduced, peeling of the electrical joint between the electronic component and the substrate does not occur.
【0012】 [0012]
又、電子部品や基板にダミーのバンプや電極を形成する場合に比べ、電子部品や基板のサイズを小さくすることが可能となる。 Also, compared to the case of forming the dummy bump and the electrode on the electronic component and the substrate, it is possible to reduce the electronic components and the size of the substrate.
【0013】 [0013]
その結果、電子部品と基板の接合信頼性が向上し、同時にコストの上昇も抑えることが可能となる。 As a result, improved reliability of bonding the electronic component and the substrate, it is possible to suppress the increase in cost at the same time.
【0014】 [0014]
なお、さらに詳細に説明すれば、本発明は下記の構成によって前記課題を解決できた。 Incidentally, In more detail, the present invention could solve the above problems by the following configurations.
【0015】 [0015]
(1)電子部品と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と基板を加熱、加圧接合したことを特徴とする接合構造。 (1) curing shrinkage force of the electronic component and the substrate organic material, in the joining structure to be joined by heat shrinkage force, heating electronic components and a substrate with an organic material disposed structural members in advance predetermined positions, pressure junction structure, characterized in that the joined.
【0016】 [0016]
(2)電子部品と電子部品が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と電子部品を加熱、加圧接合したことを特徴とする接合構造。 (2) curing shrinkage force of the electronic component and the electronic component is an organic material, in the joining structure to be joined by heat shrinkage force, heating electronic components and electronic components using an organic material disposed structural members in advance predetermined positions, junction structure, characterized in that the joining pressure.
【0017】 [0017]
(3)基板と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて基板と基板を加熱、加圧接合したことを特徴とする接合構造。 (3) substrate and curing shrinkage force of the substrate is an organic material, in the joining structure to be joined by heat shrinkage force, heating the substrate and the substrate with an organic material disposed structural members in advance predetermined positions, and bonded under pressure junction structure, characterized in that.
【0018】 [0018]
(4)前記(1)または(2)記載の接合構造を持った電子部品と基板を搭載したことを特徴とする電子機器。 (4) (1) or (2) an electronic device, characterized in that mounting the electronic component and the substrate having a junction structure according.
【0019】 [0019]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
(第1の実施例) (First Embodiment)
図1−aが本発明の特徴を最もよく表した図であり、シリコン基板1にベアチップIC2がACF3で熱圧着接合され、ベアチップIC2のバンプ5とシリコン基板1の電極6間からACF3が排出されバンプ5と電極6が接触し電気的に導通した状態を、横断面から示したものであり、図1−bは上面から示したものである。 A best represents the diagram the features of FIG. 1-a is present invention, a bare chip IC2 to the silicon substrate 1 is thermally compression bonding with ACF 3, ACF 3 is discharged from between the bump 5 and the electrode 6 of the silicon substrate 1 of the bare chip IC2 the state in which the bump 5 and the electrode 6 are electrically connected in contact, there is shown a cross-section, Fig. 1-b is an illustration of the top surface.
【0020】 [0020]
図1において、7で示した構造部材がACF3に予め形成された構造部材で、高耐熱性の樹脂ボールを用いている。 In Figure 1, the structure member shown in 7 is a structural member which is preformed in ACF 3, and using a high heat-resistant resin ball. 構造部材7の高さは、ベアチップIC2のバンプ5の厚みとシリコン基板1の電極6の厚みに合わせて決めればよいが、バンプ5と電極6が熱圧着されて塑性変形して決まるギャップ量に合わせる事が望ましい。 The height of the structural member 7, may be determined according to the thickness of the electrode 6 having a thickness of the silicon substrate 1 of the bumps 5 of the bare chip IC 2, the bump 5 and the electrode 6 is thermally bonded to the gap amount determined by plastic deformation it is desirable to match.
【0021】 [0021]
また、構造部材7を配置する間隔は、加圧されるベアチップICの剛性により決めればよいが、剛性が低い場合は構造部材7の間隔を狭める事が望ましい。 The distance to place the structural member 7, may be determined by the stiffness of the bare chip IC pressurized, when the rigidity is low, it is desirable to reduce the distance of the structural member 7.
【0022】 [0022]
このような構成をとることによって、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。 By adopting such a configuration, the structural member 7 functions as a strut is arranged between the junction point of the bumps 5 and the electrodes 6, uniformly distributed load when the bare chip IC2 is pressurized is considerably reduced.
【0023】 [0023]
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。 As a result, there is no indentation of the bare chip IC2 due to a uniformly distributed load of pressurization, the plastic deformation amount variation of the bump 5 and the electrode 6 of the silicon substrate 1 of the bare chip IC2 is reduced, peeling of the joint is not generated, electric connection reliability is improved.
【0024】 [0024]
(第2の実施例) (Second embodiment)
図2−a、図2−bは、本発明の第2の実施形態を説明する図である。 Figure 2-a, Figure 2-b is a diagram for explaining the second embodiment of the present invention. この実施形態は、第1の実施の形態において、構造部材7に、高耐熱性樹脂ボールの代わりに金属ボールの周りを高耐熱樹脂で被覆したボールを用いた以外は、第1の実施の形態と同じ構成である。 This embodiment, in the first embodiment, the structural member 7, except for using the ball instead of the high heat resistant resin balls around the metal balls coated with a high heat-resistant resin, the first embodiment the same configuration as that.
【0025】 [0025]
このような構成でも第1の実施例と同様、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。 Like the first embodiment in such a structure, since the structural member 7 functions as a strut is arranged between the junction point of the bump 5 and the electrode 6, the uniformly distributed load significantly reduced when the bare chip IC2 is pressurized It has been.
【0026】 [0026]
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。 As a result, there is no indentation of the bare chip IC2 due to a uniformly distributed load of pressurization, the plastic deformation amount variation of the bump 5 and the electrode 6 of the silicon substrate 1 of the bare chip IC2 is reduced, peeling of the joint is not generated, electric connection reliability is improved.
【0027】 [0027]
(第3の実施例) (Third Embodiment)
図3−a、図3−bは、本発明の第3の実施形態を説明する図である。 Figure 3-a, Figure 3-b is a diagram illustrating a third embodiment of the present invention. この実施形態は、第1の実施の形態において、構造部材7の形状がボールではなく、円柱であること以外は第1の実施の形態と同じ構成である。 This embodiment, in the first embodiment, instead of the ball shape of the structural member 7, except that the cylinder has the same configuration as the first embodiment.
【0028】 [0028]
このような構成でも第1の実施例と同様、構造部材7がバンプ5と電極6の接合個所の間に配置され支柱として機能するので、ベアチップIC2が加圧された時に等分布荷重が著しく低減された。 Like the first embodiment in such a structure, since the structural member 7 functions as a strut is arranged between the junction point of the bump 5 and the electrode 6, the uniformly distributed load significantly reduced when the bare chip IC2 is pressurized It has been.
【0029】 [0029]
その結果、加圧時の等分布荷重に起因したベアチップIC2の凹みがなくなり、ベアチップIC2のバンプ5とシリコン基板1の電極6の塑性変形量ばらつきが低減され、接合部の剥離が発生しなくなり、電気的接合信頼性が向上した。 As a result, there is no indentation of the bare chip IC2 due to a uniformly distributed load of pressurization, the plastic deformation amount variation of the bump 5 and the electrode 6 of the silicon substrate 1 of the bare chip IC2 is reduced, peeling of the joint is not generated, electric connection reliability is improved.
【0030】 [0030]
以上、本発明の実施の形態について説明したが、本発明はこれに限定されるものではなく、基板としては、ガラスエポキシ基板、ガラス基板、セラミック基板など有機基板、無機基板で電子部品を搭載するものであれば全てに適用できる。 Having described embodiments of the present invention, the present invention is not limited thereto, as the substrate, mounted glass epoxy substrate, a glass substrate, an organic substrate such as a ceramic substrate, an inorganic substrate an electronic component It can be applied to all as long as it. 同様に電子部品としては、能動部品、受動部品いずれであっても本発明を適用することができる。 Similarly as the electronic components, active components, be either passive components it is possible to apply the present invention. 併せて、基板同士、電子部品同士の接合にも適用できる。 In addition, boards, can be applied to the junction between the electronic component.
【0031】 [0031]
また有機材料としては、NCF、ACP、NCPなど熱硬化性有機材料、あるいは光硬化性有機材料のいずれであっても本発明を適用することができる。 As the organic material can be applied NCF, ACP, heat-curable organic material such as NCP, or even present invention either a photocurable organic material.
【0032】 [0032]
【発明の効果】 【Effect of the invention】
以上説明したように、本発明は電子部品を有機材料を用いて基板に加熱、加圧接合、あるいは光照射、加圧接合する場合、電子部品のバンプと基板の電極による接続個所の間に位置するように、有機材料に予め構造部材を設けて接合することにより等分布荷重を著しく低減することが可能となった。 As described above, the present invention is heated to a substrate an electronic component using an organic material, pressure bonding, or light irradiation, when bonding pressure, located between the connection location by bumps and substrate electrodes of the electronic component as to, it becomes possible to significantly reduce the uniformly distributed load by joining by providing a pre structural member to the organic material.
【0033】 [0033]
その結果、電子部品や基板に撓みや凹みが発生しない接合構造となり、電子部品のバンプと基板の電極の塑性変形量ばらつきが低減され、電子部品と基板との電気接合部の剥離による接続不良が発生しなくなり接合信頼性が向上した。 As a result, the joint structure deflection and depressions on the electronic component and the substrate does not occur, the plastic deformation amount variation of the electronic component of the bumps and the electrodes of the substrate is reduced, poor connection due to peeling of the electrical joint between the electronic component and the substrate bonding reliability was improved no longer occurs.
【0034】 [0034]
又、電子部品や基板にダミーのバンプや電極を形成する場合に比べ、電子部品や基板のサイズを小さくすることが可能となり、その結果電子部品と基板のコスト上昇も抑えることが可能となった。 Also, compared to the case of forming the dummy bump and the electrode on the electronic component and the substrate, it is possible to reduce the electronic components and the size of the substrate, it becomes possible to suppress the cost increase resulting electronic component and the substrate .
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1−a】本発明の第1の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。 Is a view for explaining the first embodiment of FIG. 1-a] present invention, it is a cross-sectional view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【図1−b】本発明の第1の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。 It is a view for explaining the first embodiment of FIG. 1-b] present invention, is a top view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【図2−a】本発明の第2の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。 Is a view for explaining the second embodiment of FIG. 2-a] present invention, it is a cross-sectional view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【図2−b】本発明の第2の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。 It is a view for explaining the second embodiment of FIG. 2-b] present invention, is a top view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【図3−a】本発明の第3の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す断面図である。 Figure 3-a] is a view for explaining a third embodiment of the present invention, it is a cross-sectional view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【図3−b】本発明の第3の実施形態を説明する図であり、ベアチップICとシリコン基板がACFを介して接合された状態を示す上面図である。 Figure 3-b] is a view for explaining a third embodiment of the present invention, it is a top view showing a state where the bare chip IC and the silicon substrate are bonded via the ACF.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 シリコン基板2 ベアチップIC 1 silicon substrate 2 bare-chip IC
3 ACF 3 ACF
4 ACFに配置された構造部材(高耐熱性樹脂) 4 ACF placement structural member (highly heat-resistant resin)
5 ベアチップICのバンプ6 シリコン基板の電極7 金属コアボール(構造部材) 5 bare chip IC bumps 6 silicon substrate electrode 7 metal core ball (structural member)

Claims (4)

  1. 電子部品と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と基板を加熱、加圧接合したことを特徴とする接合構造。 Electronic components and curing shrinkage force of the substrate is an organic material, in the joining structure to be joined by heat shrinkage force, heating electronic components and a substrate with an organic material disposed structural members in advance predetermined positions, that it has joined under pressure joint structure according to claim.
  2. 電子部品と電子部品が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて電子部品と電子部品を加熱、加圧接合したことを特徴とする接合構造。 Cure shrinkage force of the electronic component and the electronic component is an organic material, in the joining structure to be joined by heat shrinkage force, heating electronic components and electronic components using an organic material disposed structural members in advance predetermined positions, pressure bonding junction structure, characterized in that the.
  3. 基板と基板が有機材料の硬化収縮力、熱収縮力によって接合される接合構造において、予め所定の位置に構造部材を配置した有機材料を用いて基板と基板を加熱、加圧接合したことを特徴とする接合構造。 Substrate and curing shrinkage force of the substrate is an organic material, characterized in joint structure joined by heat shrinkage force, heating the substrate and the substrate with an organic material disposed structural members in advance predetermined positions, that it has joined under pressure junction structure to be.
  4. 請求項1または請求項2記載の接合構造を持った電子部品と基板を搭載したことを特徴とする電子機器。 Electronic apparatus, characterized in that claim 1 or claim 2 mounted with an electronic component and a substrate having a junction structure according.
JP2002291108A 2002-10-03 2002-10-03 Joint structure and electronic equipment equipped with the same Withdrawn JP2004128259A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039960A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
WO2007039959A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
JP2011176143A (en) * 2010-02-24 2011-09-08 Sumitomo Bakelite Co Ltd Conductive connection sheet, method of connecting between terminals, method of forming connection terminal, semiconductor device, and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039960A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
WO2007039959A1 (en) * 2005-10-05 2007-04-12 Sharp Kabushiki Kaisha Wiring board and display device provided with same
US8013454B2 (en) 2005-10-05 2011-09-06 Sharp Kabushiki Kaisha Wiring substrate and display device including the same
JP2011176143A (en) * 2010-02-24 2011-09-08 Sumitomo Bakelite Co Ltd Conductive connection sheet, method of connecting between terminals, method of forming connection terminal, semiconductor device, and electronic device

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