JP2001203311A - Method for cutting lead tip of semiconductor element - Google Patents

Method for cutting lead tip of semiconductor element

Info

Publication number
JP2001203311A
JP2001203311A JP2000013339A JP2000013339A JP2001203311A JP 2001203311 A JP2001203311 A JP 2001203311A JP 2000013339 A JP2000013339 A JP 2000013339A JP 2000013339 A JP2000013339 A JP 2000013339A JP 2001203311 A JP2001203311 A JP 2001203311A
Authority
JP
Japan
Prior art keywords
lead
semiconductor element
cutting
cut
punch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000013339A
Other languages
Japanese (ja)
Inventor
Takeshi Hase
健史 長谷
Tadaharu Kataoka
忠晴 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ueno Seiki Co Ltd
Original Assignee
Ueno Seiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ueno Seiki Co Ltd filed Critical Ueno Seiki Co Ltd
Priority to JP2000013339A priority Critical patent/JP2001203311A/en
Publication of JP2001203311A publication Critical patent/JP2001203311A/en
Pending legal-status Critical Current

Links

Landscapes

  • Punching Or Piercing (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a connecting fault to a pattern at the time of mounting a substrate due to a burr generated lower than a lower surface of a lead in a method for cutting the lead tip of a semiconductor element loaded on a lead frame by an operation of a punch from above to below. SOLUTION: Before cutting of the lead 4 tip of a semiconductor element. a groove 9 is formed by a die having a protrusion on the lower side of the part to be cut, and then the lead is cut by a punch 2. Thus, the burr will not project beyond the lower surface of the lead. Accordingly, connection fault to the pattern due to the burr in mounting the semiconductor element on the substrate can be prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子のリー
ド先端の切断方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for cutting the tip of a lead of a semiconductor device.

【0002】[0002]

【従来の技術】一般にICチップ等の半導体素子は、長
尺状のリードフレーム上に一定ピッチで離間して搭載さ
れ、つながった状態で、リード成形、素子のテスト、マ
ーキング等が行われ、その後、成形済みの素子が1個の
製品としてリードフレームから切断される。この切断工
程では、リードフレーム上に搭載された半導体素子のリ
ード先端を、パンチを上から下へあるいは下から上へ動
作させて切断する方法が通常使用されている。
2. Description of the Related Art In general, semiconductor devices such as IC chips are mounted on a long lead frame at a constant pitch and are separated from each other. In a connected state, lead molding, device testing, marking, etc. are performed. The molded element is cut from the lead frame as one product. In this cutting step, a method of cutting the lead end of a semiconductor element mounted on a lead frame by operating a punch from top to bottom or from bottom to top is usually used.

【0003】図1にその切断方法を示す。図中1は半導
体素子、2はパンチ、4はリード、6は金型上型、7は
金型下型である。図示の場合は、パンチ2を上から下へ
動作させて、リード4の先端を切断している。図2は上
記方法でリード先端を切断した半導体素子を示す図であ
る。このような方法でリード先端を切断すると、図3に
拡大して示すように、リード先端部に切断面のカエリ5
がリード下面から下に突出し、半導体素子を基板に実装
する際にパターンへの接続不良が起きやすくなるという
問題があった。
FIG. 1 shows the cutting method. In the figure, 1 is a semiconductor element, 2 is a punch, 4 is a lead, 6 is an upper mold, and 7 is a lower mold. In the illustrated case, the tip of the lead 4 is cut off by operating the punch 2 from top to bottom. FIG. 2 is a view showing a semiconductor device in which the tip of a lead is cut by the above method. When the lead tip is cut by such a method, as shown in the enlarged view of FIG.
Has protruded downward from the lower surface of the lead, and there has been a problem that a connection failure to a pattern is likely to occur when the semiconductor element is mounted on a substrate.

【0004】また、パンチを下から上へ動作させてリー
ド先端を切断する方法では、抜きカスが飛散しやすく、
抜きカスによる刃物破損が起こりやすく、また使用する
金型の構造が複雑になるという問題があった。
In the method of cutting the tip of the lead by operating the punch from the bottom to the top, the scrap is easily scattered.
There has been a problem that the blade is easily damaged by the scraps, and the structure of a mold to be used is complicated.

【0005】[0005]

【発明が解決しようとする課題】本発明は、上記従来技
術の問題点を解消するためになされたもので、リード下
面より下にカエリが出ることによる基板実装時における
パターンへの接続不良を防止するとともに、抜きカスに
よる事故をなくし、金型構造を簡素化できる半導体素子
のリード先端の切断方法を提供することをその課題とす
る。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and prevents a connection failure to a pattern at the time of board mounting due to burrs appearing below the lower surface of a lead. It is another object of the present invention to provide a method of cutting a lead end of a semiconductor element, which can eliminate an accident due to a scrap and simplify a mold structure.

【0006】[0006]

【課題を解決するための手段】本発明によれば、上記課
題を解決するため、リードフレーム上に搭載された半導
体素子のリード先端を、パンチの上から下への動作によ
り切断する方法において、リード先端の切断前に、その
切断される部分の下側に、凸部を設けた金型により溝を
形成することを特徴とする半導体素子のリード先端の切
断方法が提供される。
According to the present invention, there is provided a method for cutting a lead end of a semiconductor element mounted on a lead frame by an operation from top to bottom of a punch. A method for cutting a lead end of a semiconductor element is provided, wherein a groove is formed by a mold provided with a convex portion below a part to be cut before cutting the lead end.

【0007】[0007]

【発明の実施の形態】以下、本発明の方法を詳細に説明
する。本発明の方法は、パンチによるリード切断工程の
前に、リードの切断される部分の下側に溝を形成する溝
形成工程を設けたことを特徴とするものである。図4は
溝形成工程の説明図、図5はリード切断工程の説明図で
ある。これらの図において、1は半導体素子、2はパン
チ、4はリード、6’,7’は上記溝を形成する工程に
用いる金型上型及び下型、6,7はパンチによるリード
切断工程で用いる金型上型及び下型、8は金型下型7’
に形成された凸部、9はリードの切断される部分の下側
に形成された溝を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention will be described below in detail. The method of the present invention is characterized in that a groove forming step of forming a groove below a portion where a lead is to be cut is provided before the lead cutting step with a punch. FIG. 4 is an explanatory view of a groove forming step, and FIG. 5 is an explanatory view of a lead cutting step. In these figures, 1 is a semiconductor element, 2 is a punch, 4 is a lead, 6 'and 7' are upper and lower molds used in the step of forming the groove, and 6 and 7 are lead cutting steps by a punch. Upper and lower molds used, 8 is lower mold 7 '
The reference numeral 9 denotes a groove formed below the portion where the lead is cut.

【0008】本発明では、溝形成工程において、金型下
型7’として凸部8が形成されたものを用いる。この凸
部8はリード4の幅方向に沿って延びており、リード4
の切断される部分の下側に形成する溝9と相補的な形状
をしている。凸部8の断面形状は、任意の形状とするこ
とができるが、その一例としては図4に示すような台形
形状が例示される。凸部8の半導体素子よりの端部は、
カエリをリード下面より下に出さないためには、パンチ
2の半導体素子よりの端部より若干半導体素子側に位置
していることが望ましい。凸部8の寸法は、対象となる
半導体素子及びリードの大きさに応じて適宜設定するこ
とができる。
In the present invention, in the groove forming step, a mold having a convex portion 8 is used as a lower mold 7 '. The projection 8 extends along the width direction of the lead 4,
Has a shape complementary to the groove 9 formed below the portion to be cut. The cross-sectional shape of the convex portion 8 can be any shape, and as an example, a trapezoidal shape as shown in FIG. 4 is exemplified. The end of the protrusion 8 from the semiconductor element is
In order to prevent burrs from being lower than the lower surface of the lead, it is desirable that the punch 2 is located slightly closer to the semiconductor element than the end of the punch 2 from the semiconductor element. The dimensions of the protrusions 8 can be appropriately set according to the size of the target semiconductor element and the lead.

【0009】上記溝形成工程により、リード4の先端に
は図5のような溝9が形成されるが、その後のリード切
断工程は、図5に示すように、従来と同様に、パンチ2
を上から下へ動作させることにより行うことができる。
このようにしてリード先端が切断された半導体素子を図
6に示し、切断されたリード先端部を拡大したものを図
7に示す。5はカエリであり、溝9を形成していたた
め、リード下面より下に出ることはない。従って、半導
体素子を基板に実装する際に、カエリによるパターンへ
の接続不良は完全に防止される。
By the above-described groove forming step, a groove 9 as shown in FIG. 5 is formed at the tip of the lead 4. In the subsequent lead cutting step, as shown in FIG.
By operating from top to bottom.
FIG. 6 shows the semiconductor element having the lead tip thus cut off, and FIG. 7 shows an enlarged view of the cut lead end portion. Reference numeral 5 denotes burrs, which have formed the grooves 9 and therefore do not protrude below the lower surfaces of the leads. Therefore, when mounting the semiconductor element on the substrate, poor connection to the pattern due to burrs is completely prevented.

【0010】[0010]

【発明の効果】本発明によれば、パンチによるリード切
断の前に、リードの切断される部分の下側に溝を形成す
るようにしたので、リード下面より下にカエリが出るこ
とはなくなり、半導体素子を基板に実装する際のカエリ
によるパターンへの接続不良が完全に防止できる。ま
た、パンチを上から下へ動作させることにより、リード
切断を行うので、抜きカスの飛散がなく、抜きカスによ
る刃物破損が防止でき、金型の構造を簡素化できる。
According to the present invention, before the lead is cut by the punch, a groove is formed below the portion where the lead is cut, so that no burrs appear below the lower surface of the lead, Insufficient connection to the pattern due to burrs when mounting the semiconductor element on the substrate can be completely prevented. In addition, since the lead is cut by operating the punch from the top to the bottom, there is no scattering of the scrap, the blade can be prevented from being damaged by the scrap, and the structure of the mold can be simplified.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来のリード先端の切断方法を説明するための
断面図である。
FIG. 1 is a cross-sectional view for explaining a conventional method of cutting the tip of a lead.

【図2】従来の方法でリード先端を切断した半導体素子
を示す断面図である。
FIG. 2 is a cross-sectional view showing a semiconductor device in which a lead end is cut by a conventional method.

【図3】従来の方法でリード先端を切断したリード先端
部を拡大して示す断面図である。
FIG. 3 is an enlarged sectional view showing a lead tip portion obtained by cutting the lead tip by a conventional method.

【図4】本発明の方法によりリードの下面に溝を形成す
る工程を説明するための断面図である。
FIG. 4 is a cross-sectional view for explaining a step of forming a groove on the lower surface of a lead by the method of the present invention.

【図5】本発明の方法によりリード先端を切断する工程
を説明するための断面図である。
FIG. 5 is a cross-sectional view for explaining a step of cutting a lead end by the method of the present invention.

【図6】本発明の方法でリード先端を切断した半導体素
子を示す断面図である。
FIG. 6 is a cross-sectional view showing a semiconductor device in which a lead end is cut by the method of the present invention.

【図7】本発明の方法でリード先端を切断したリード先
端部を拡大して示す断面図である。
FIG. 7 is an enlarged sectional view showing a lead tip portion obtained by cutting the lead tip by the method of the present invention.

【符号の説明】 1 半導体素子 2 パンチ 4 リード 5 カエリ 6,6’ 金型上型 7,7’ 金型下型 8 凸部 9 溝[Description of Signs] 1 semiconductor element 2 punch 4 lead 5 flash 6 and 6 'mold upper mold 7, 7' mold lower mold 8 convex part 9 groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 リードフレーム上に搭載された半導体素
子のリード先端を、パンチの上から下への動作により切
断する方法において、 リード先端の切断前に、その切断される部分の下側に、
凸部を設けた金型により溝を形成することを特徴とする
半導体素子のリード先端の切断方法。
1. A method for cutting a lead end of a semiconductor element mounted on a lead frame by an operation from a top to a bottom of a punch, comprising:
A method of cutting the tip of a lead of a semiconductor element, wherein a groove is formed by a mold having a convex portion.
JP2000013339A 2000-01-21 2000-01-21 Method for cutting lead tip of semiconductor element Pending JP2001203311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000013339A JP2001203311A (en) 2000-01-21 2000-01-21 Method for cutting lead tip of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000013339A JP2001203311A (en) 2000-01-21 2000-01-21 Method for cutting lead tip of semiconductor element

Publications (1)

Publication Number Publication Date
JP2001203311A true JP2001203311A (en) 2001-07-27

Family

ID=18540942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000013339A Pending JP2001203311A (en) 2000-01-21 2000-01-21 Method for cutting lead tip of semiconductor element

Country Status (1)

Country Link
JP (1) JP2001203311A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008218525A (en) * 2007-02-28 2008-09-18 Sanyo Electric Co Ltd Cutting method of conductive member, and method for manufacturing circuit device
CN109332470A (en) * 2018-11-07 2019-02-15 深圳振华富电子有限公司 SMT Inductor exit foot cut device
CN114769414A (en) * 2022-06-21 2022-07-22 四川旭茂微科技有限公司 Semiconductor forming and separating die

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008218525A (en) * 2007-02-28 2008-09-18 Sanyo Electric Co Ltd Cutting method of conductive member, and method for manufacturing circuit device
CN109332470A (en) * 2018-11-07 2019-02-15 深圳振华富电子有限公司 SMT Inductor exit foot cut device
CN114769414A (en) * 2022-06-21 2022-07-22 四川旭茂微科技有限公司 Semiconductor forming and separating die

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