JP2001202782A5 - - Google Patents
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- Publication number
- JP2001202782A5 JP2001202782A5 JP2000013107A JP2000013107A JP2001202782A5 JP 2001202782 A5 JP2001202782 A5 JP 2001202782A5 JP 2000013107 A JP2000013107 A JP 2000013107A JP 2000013107 A JP2000013107 A JP 2000013107A JP 2001202782 A5 JP2001202782 A5 JP 2001202782A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000013107A JP2001202782A (ja) | 2000-01-21 | 2000-01-21 | 半導体記憶装置 |
| US09/613,503 US6310808B1 (en) | 2000-01-21 | 2000-07-10 | Semiconductor memory device having structure for high-speed data processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000013107A JP2001202782A (ja) | 2000-01-21 | 2000-01-21 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001202782A JP2001202782A (ja) | 2001-07-27 |
| JP2001202782A5 true JP2001202782A5 (enExample) | 2006-11-09 |
Family
ID=18540747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000013107A Pending JP2001202782A (ja) | 2000-01-21 | 2000-01-21 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6310808B1 (enExample) |
| JP (1) | JP2001202782A (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6324110B1 (en) * | 1999-03-12 | 2001-11-27 | Monolithic Systems Technology, Inc. | High-speed read-write circuitry for semi-conductor memory |
| JP2003100079A (ja) * | 2001-09-21 | 2003-04-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
| DE10258168B4 (de) * | 2002-12-12 | 2005-07-07 | Infineon Technologies Ag | Integrierter DRAM-Halbleiterspeicher und Verfahren zum Betrieb desselben |
| KR100642636B1 (ko) | 2004-07-30 | 2006-11-10 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 라인 배치 방법 |
| US8193606B2 (en) * | 2005-02-28 | 2012-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including a memory element |
| KR100980057B1 (ko) * | 2007-06-29 | 2010-09-03 | 주식회사 하이닉스반도체 | 프리차지 제어 회로 |
| JP2009016004A (ja) * | 2007-07-09 | 2009-01-22 | Nec Electronics Corp | 半導体装置及び半導体装置の制御方法 |
| JP5291593B2 (ja) * | 2009-10-21 | 2013-09-18 | ラピスセミコンダクタ株式会社 | 半導体記憶装置 |
| JP2011248932A (ja) * | 2010-05-21 | 2011-12-08 | Panasonic Corp | 半導体記憶装置 |
| KR20170097996A (ko) * | 2016-02-19 | 2017-08-29 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| CN115798544B (zh) * | 2023-02-13 | 2023-04-28 | 长鑫存储技术有限公司 | 一种读写电路、读写方法和存储器 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528551A (en) * | 1987-05-21 | 1996-06-18 | Texas Instruments Inc | Read/write memory with plural memory cell write capability at a selected row address |
| US5594704A (en) * | 1992-04-27 | 1997-01-14 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
| US5511025A (en) * | 1993-10-18 | 1996-04-23 | Texas Instruments Incorporated | Write per bit with write mask information carried on the data path past the input data latch |
| JP3247639B2 (ja) * | 1997-08-07 | 2002-01-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体メモリ、半導体メモリのデータ読み出し方法及び書き込み方法 |
| US6125065A (en) * | 1998-09-09 | 2000-09-26 | Fujitsu Limited | Semiconductor memory with column gates and method of controlling column gates during a write mask operation |
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2000
- 2000-01-21 JP JP2000013107A patent/JP2001202782A/ja active Pending
- 2000-07-10 US US09/613,503 patent/US6310808B1/en not_active Expired - Fee Related