JP2001188683A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the speed of an interruption processing and an exception processing without necessitating a complicated program in a micro controller holding a vector table to store the leading address of a processing routine for the processings. SOLUTION: For example, a new vector table is prepared in a built-in RAM area separately from the fixed vector table written in a mask ROM. And, this integrated circuit device is constituted so as to enable easy calculation of a vector address on the new vector table based on the vector address on the fixed vector table 11 and the difference of address between the fixed vector table 11 and the new vector table when the interruption processing and the exception processing are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit device, and more particularly to a microcontroller having a vector table for storing a start address of a processing routine for interrupt processing and exception processing.

[0002]

2. Description of the Related Art Conventionally, general-purpose microcontrollers are:
It supports interrupt processing and exception processing in addition to ordinary addition, subtraction, and branch instruction processing. Here, the interrupt processing is
UART (Universal Asynchronous Receiver / Transmit
This is a means for causing a CPU (Central Processing Unit) to recognize the end of processing in peripheral megacells, such as the completion of transmission of ter). On the other hand, exception processing means that the occurrence of division by zero, etc.
This is a means to make the PU aware. Also, the interrupt processing and the exception processing here mean that the above-described processing is recognized by a program and the processing is executed by the CPU.

FIG. 10 is a diagram showing a schematic configuration of a conventional (existing) microcontroller.

The microcontroller has, for example, C
PU 101, RAM (built-in RAM area) 102, ROM
(Built-in ROM area) 103 and peripheral megacells (in this case, UART1
04a, SIO (Serial Input Output) 104b, timer 104c), and an interrupt control circuit 105 for instructing the CPU 101 to generate an interrupt.
6 and the data bus 107 are mutually connected. The interrupt control circuit 105
Has an internal register (not shown) for judging the priority of an interrupt request from a peripheral megacell and holding the contents of the interrupt request. The CPU 101 determines the megacell requesting the interrupt and the type of the interrupt. It has the function of instructing.

[0005] In this case, the ROM 103 is merely used.
Is used in most cases. Also, the read / write signal is omitted.

A control program for a microcontroller is generally composed of a processing program in small block units called a subroutine. The activation and release of the subroutine program are normally controlled by interrupt processing and exception processing. The head address of the subroutine program is stored in a vector area (in this case, addresses FFE0H to FFFFH) used as a vector table, as shown in FIG. 11, for example.

FIG. 12 shows a list of vector tables in the microcontroller. Here, an example in which 16 types of interrupt processing and exception processing are provided will be described.

The vector table stores, for example, a memory (in this case, 800 bytes in a built-in ROM area) of a subroutine program prepared for each interrupt factor (interrupt type).
The head addresses (vector addresses) on addresses 0H to FFDFH are stored, respectively.

In each vector table, the order from the starting point (for example, the address on the memory address map, the youngest base address in the vector area (in this case, the address FFE0H)) is determined in accordance with the respective vector addresses. Assigned.

In this case, for example, as shown in FIG.
The size of each vector table is 16 bits. Then, the lower address (even address) is followed by 8 bits of the upper 16-bit address,
The lower 8 bits are stored at the next address (odd address).

Next, the conventional operation of the microcontroller in the above configuration will be described. Here, a case where a transmission completion interrupt request is generated from the UART 104a will be described as an example.

First, a transmission completion interrupt request from the UART 104a is sent to the interrupt control circuit 105. Then, an interrupt generation signal (1 bit) is output from the interrupt control circuit 105 to the CPU 101. Further, the interrupt control circuit 105 determines a transmission completion interrupt request from the UART 104a and holds the content (interruption factor information) in an internal register.

On the other hand, the CPU having received the interrupt generation signal
101 reads the contents of the internal register of the interrupt control circuit 105 via the buses 106 and 107, and recognizes what interrupt request has been issued from any of the megacells. The vector address (in this case, the address FFEAH) corresponding to the interrupt factor corresponding to the request is stored in the ROM.
The data is output from the vector table to the address bus 106 to read the data from the vector table.

A series of these processes are performed by a microprogram in the CPU 101 or a hard-wired circuit (not shown).

In this way, the CPU 101 executes the subroutine program at the corresponding address in the ROM 103 in accordance with the above-mentioned vector address.
The control of the PU 101 branches.

By the way, in the conventional microcontroller, the position (address) of the vector area is fixed, and its contents cannot be changed. In particular, when the vector table is formed using a mask ROM, changing the contents means remanufacturing the mask ROM. As a result, there were problems in terms of manufacturing cost and efficiency.

In addition, an EPRO is used to form the vector table.
Some use OTP (One Time-PROM) such as M (Erasable and Programmable Read Only Memory), but the contents cannot be changed by writing.

On the other hand, by using the RAM 102, the contents of the vector table can be changed. That is, a vector area is newly provided in the built-in RAM area and used as a vector table. For example, a fixed vector table stored in a mask ROM is stored in an internal RAM.
Move to the vector area provided in the area. By doing so, without remanufacturing the mask ROM,
The contents of the vector table can be changed on the RAM 102.

However, even when the RAM 102 is used, the position of the vector area in the mask ROM cannot be changed. For example, in the case of a general-purpose microcontroller, the position of the vector area is fixed for control. Therefore, in order to use a vector table newly provided in the built-in RAM area, a complicated program was required.

[0020]

As described above, conventionally, when the RAM is used, the contents of the vector table can be changed, but the position of the vector area cannot be changed. However, there is a problem that a complicated program is required.

Therefore, the present invention provides an integrated circuit device which can speed up the processing when an interrupt processing and an exception processing occur without requiring a complicated program, and can further improve versatility. It is intended to be.

[0022]

In order to achieve the above object, in an integrated circuit device according to the present invention, a routine program for interrupt processing and exception processing is stored.
A vector table for storing a branch destination address on a memory, at least a plurality of vector areas each storing at least two types of vector tables, and selecting means for selecting one of the vector areas; A calculating means for executing the interrupt processing and the exception processing based on the branch destination address stored in the vector table stored in the vector area selected by the selecting means.

Also, in the integrated circuit device of the present invention, a first vector area for storing a branch destination address on a memory for storing a first routine program for interrupt processing and exception processing, Apart from the first vector area, a second vector area storing a branch destination address on a memory for storing a second routine program, a storage location of the branch destination address in the first vector area,
A register area for storing position difference data with respect to a storage location of a branch destination address in the second vector area, and a branch destination address stored in the first vector area or stored in the first vector area Computing means for executing the interrupt processing and the exception processing based on the branch destination address stored in the second vector area, which is obtained from the storage position of the obtained branch destination address and the position difference data. ing.

According to the integrated circuit device of the present invention, the vector area can be easily switched without depending on a complicated program. As a result, it is possible to improve the complexity of the processing when the interrupt processing and the exception processing occur.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 show a first embodiment of the present invention. FIG. 1 shows an outline of a general-purpose microcontroller (see FIG. 10), and FIG. 2 shows an example of a memory address map. Also, here, the RAM (00 in the internal RAM area) is used.
An example will be described in which an interrupt process from a megacell and an exception process (see FIG. 12) are executed using a vector table newly provided in (addresses 40H to 023FH) 102.

In FIG. 1, a fixed vector table (first vector area) 11 is, for example, as shown in FIG.
Original vector area (in this case, addresses FFE0H to FFF
FH), various subroutine programs (first routine program) for interrupt processing and exception processing
Is stored in the memory (built-in ROM area) 103 as a vector address.

In this case, the fixed vector table 11
Each size is, for example, as shown in FIG.
It is 16 bits (upper address 8 bits, lower address 8 bits).

A new vector table (second vector area) 12 stores a vector area (in this case, 0220 in this case) configured using an internal RAM area as shown in FIG.
At the addresses H to 023FH, the head addresses in the memory 103 for storing various subroutine programs (second routine programs) for interrupt processing and exception processing are stored as vector addresses.

In this case, the second routine program is
All or a part of the subroutine program in the first routine program may be different, or the first routine program itself may be used.

The size of the new vector table 12 is, for example, 16 as shown in FIG.
Bits (upper address 8 bits, lower address 8 bits).

The vector table difference storage register unit 13
For example, as shown in FIG. 2, the register area (in this case,
An address difference (position difference data) on the memory address map between each vector address in the fixed vector table 11 and each vector address in the new vector table 12 is provided at a specific address position within the addresses 0000H to 003FH). Is stored.

The subtracting section 14 has a fixed vector table 11
The above vector address and the position difference data from the vector table difference storage register section 13 are input, and the vector address on the new vector table 12 corresponding to the vector address on the fixed vector table 11 is obtained from the difference. It is to be calculated.

The selector unit (selection means) 15 is adapted to provide a vector address on the fixed vector table 11 or the subtraction unit 14 in accordance with the vector table selection instruction signal.
Is to select one of the vector addresses on the new vector table 12 as the final vector address on the basis of the calculation result.

The vector table selection instruction signal is controlled using, for example, a register provided at a specific address position in the register area or a specific external input terminal.

The processing section (arithmetic means) 16 executes a subroutine program of a corresponding address in the built-in ROM area based on, for example, the final vector address selected by the selector section 15 to execute a predetermined interrupt processing. , Perform exception processing.

It should be noted that the series of operations described here are based on the CP
In U101, processing is performed by software.

Next, the operation of the microcontroller (CPU 101) in the above configuration will be described.
Here, a case where a transmission completion interrupt request is generated from the UART 104a will be described as an example.

For example, suppose that an interrupt generation signal is output from interrupt control circuit 105 to CPU 101 in response to a transmission completion interrupt request from UART 104a.

Then, the CPU 101 sets the buses 106 and 1
A read request signal for reading the content (interrupt factor information) of the internal register of the interrupt control circuit 105 is output via the switch 07. Then, based on the contents of the internal register in response to the read request, the CPU 101
It recognizes the generation of the transmission completion interrupt request from 104a.

In the CPU 101, for example, based on the vector address (FFEAH address) of the UART interrupt on the fixed vector table 11 and the output from the vector table difference storage register 13, the subtractor 14 A vector address (FFEA) on the new vector table 12 for the UART interrupt processing
(Address H + position difference data).

Then, the vector address (address FFEAH + position difference data) corresponding to the above-mentioned interrupt factor is stored in the selector 1 based on the vector table selection instruction signal.
5 and make it the final vector address.

Here, when an instruction to select a new vector table 12 is given, first, the power of the microcontroller is turned on or the system is reset (simply reset).
For example, a microcontroller is started by executing a conventional reset process using a vector address on a fixed vector table 11 configured using a mask ROM (execution of a predetermined program). In this state, the vector table selection instruction signal is controlled so as to select the fixed vector table 11.

Thereafter, the selection of a new vector table 12 is instructed by controlling the vector table selection instruction signal using a register or a specific external input terminal.

Thereafter, the processing section 16 executes a subroutine program in the built-in ROM area corresponding to the final vector address selected by the selector section 15, thereby executing a predetermined UART interrupt processing.

When the data bus 107 in the microcontroller has 8 bits, the vector address (16
Bit) is output in two parts. Usually, the order is as follows: upper address (upper 8 bits), lower address (lower 8 bits).
Bit), but vice versa.

As described above, the conventional fixed vector table 11 and the new vector table 12 generated by moving the vector table 11 can be used as the vector table selection instruction signal without using a complicated program. It can be switched easily according to. Therefore, the use efficiency of the microcontroller can be remarkably improved, for example, higher-speed processing becomes possible.

In particular, by switching the vector tables 11 and 12, the branch destination (subroutine program) at the time of occurrence of interrupt processing or exception processing can be efficiently selected.

Further, as shown in FIG. 2, when a new vector table 12 is provided in the built-in RAM area, the contents of the vector table 12 can be freely rewritten. Further, the vector table 12 can be provided at an arbitrary address position in the internal RAM area as needed.

The new vector table 12 stores RA
Not only in the case of the M102 but also in the case of being provided in an EPROM or an EEPROM, the contents can be freely rewritten.

Further, the number of new vector tables 12 is not limited to one, and a plurality of vector tables can be provided.

(Second Embodiment) FIGS. 3 and 4 show a second embodiment of the present invention. FIG. 3 schematically shows a general-purpose microcontroller (see FIG. 10), and FIG. 4 shows an example of a memory address map. Here, a ROM (built-in ROM area) 10
An example in which a plurality of vector tables are provided in advance in 3 will be described. However, since the overall configuration is substantially the same as in FIGS. 1 and 2, the same portions are denoted by the same reference numerals and detailed description thereof will be omitted.

In this case, for example, as shown in FIG. 4, in addition to the fixed vector table 11, three types of new vector tables (vector areas (new 1) to (new 3)) 12
a, 12b, and 12c are provided in the ROM 103 in advance.

Further, in addition to the configuration shown in FIG. 1, for example, the CPU 101 stores the address difference (position difference data) from the fixed vector table 11 into three types of new vector tables 1.
Vector table difference storage register sections 13a, 13b, 13c for storing each of 2a, 12b, 12c, and the vector table difference storage register sections 13a, 13b, 13c.
A vector table difference storage register switching register section 19 and a selector section 20 are provided as specifying means for selecting one of the above (see FIG. 3).

According to such a configuration, it is possible to remarkably improve the program efficiency by switching the branch destination according to the selected vector tables 12a, 12b, and 12c.

The new vector tables 12a, 12a
b and 12c are not limited to three types, but may be two or more types.

The vector table difference storage register 1
The numbers 3a, 13b and 13c do not necessarily have to be the same as the number of new vector tables 12a, 12b and 12c. That is, it is sufficient to prepare only the vector table to be used.

Further, a new vector table 12a, 1
It is not necessary to provide all of the 2b and 12c in the ROM 103, and some or all of them may be provided in the RAM 102.

(Third Embodiment) FIGS. 5 to 8 show a third embodiment of the present invention. Here,
As described above, a microcontroller (see FIGS. 10 and 12) having 16 types of interrupt processing and exception processing will be described as an example.

When a microcontroller is actually used, a control program containing all interrupt processing and exception processing is rarely created. Therefore, in the present embodiment, a case will be described in which four types of interrupt processing and exception processing are executed among 16 types of interrupt processing and exception processing. In this case, 12 types of interrupt processing and exception processing are not performed. However, in the above-described first and second embodiments, it is necessary to secure a vector area even for interrupt processing and exception processing that are not performed. Therefore, in the present embodiment, interrupt processing and exception processing that are not performed are excluded from the vector table to reduce the size of the vector area.

In FIG. 5, the generated interrupt type judging section 31
Is based on an interrupt generation signal (several bits) from the interrupt control circuit 105, and recognizes which of the 16 types of interrupt processing and exception processing originally provided by the microcontroller has occurred. Things.

Vector table use instruction register 32
Stores an instruction to use a new vector table 12 'provided in the built-in RAM area as shown in FIG. 6, for example. The vector table use instruction register section 32 includes a register area (in this case, 000
(Addresses 0H to 003FH).

Assuming that the interrupt processing and the exception processing that can be executed when the new vector table 12 'is used are four types shown in FIG. 7, for example, addresses 0238H to 023FH in the built-in RAM area are stored. Used as a vector area.

Vector table type indication register 33
Stores instructions for indicating types of interrupt processing and exception processing that can be executed by using a new vector table 12 'as shown in FIG. 8, for example. In this case, a new vector table 12 '
, "1" is set to bits corresponding to interrupt processing and exception processing that can be performed.

The vector table type indicating register 33 is provided at a specific address position in the register area.

The vector table use confirming unit 34 performs the interrupt processing recognized by the generated interrupt type determining unit 31 when the use of the new vector table 12 ′ is instructed by the vector table use instruction register 32. ,
The exception processing is performed by the vector table type indication register 3
3 is to determine whether or not the type of interrupt processing and exception processing on the new vector table 12 'that can be executed is identical.

When it is not determined that they coincide with each other, that is, when an interrupt process and an exception process other than the four types occur, the vector table use confirmation unit 34 performs a predetermined error process.

Interrupt vector base instruction register section 35
Stores the base address (in this case, address 0238H) of the new vector table 12 '. The interrupt vector base instruction register section 35 is provided at a specific address position in the register area.

The vector address calculation unit 36 calculates the final vector address based on the outputs of the interrupt vector base instruction register unit 35, the generated interrupt type determination unit 31, and the vector table type instruction register unit 33. Is what you do. This vector address calculation unit 36
For example, the subtractor 14 and the selector 15 shown in FIG.
It is mainly configured.

The processing unit 37 executes a subroutine program at a corresponding address in the internal ROM area based on the final vector address calculated by the vector address calculation unit 36, for example, to execute a predetermined interrupt processing, exception, The processing is performed.

According to such a configuration, for example, when there are four types of interrupt processing and exception processing that can be performed, the size of the vector area used for the new vector table 12 'is 8 bits. I'm done. As a result, the area (for 24 bytes) to be originally allocated to the 12 types of interrupt processing and exception processing that cannot be performed can be effectively used in other processing.

In the present embodiment, a case has been described in which four types of interrupt processing and exception processing can be performed. However, the present invention is not limited to this, and the type and the number can be arbitrarily set.

In addition to the four types of processing that can be performed, error processing is performed when 12 types of interrupt processing and exception processing occur. For example,
When 12 types of interrupt processing and exception processing that cannot be performed in the present embodiment occur, it is also possible to easily select a fixed vector table 11 and perform predetermined interrupt processing and exception processing. It is.

Furthermore, in each of the above-described embodiments, the CPU is processed by software in order to use the existing microcontroller as it is. However, the same can be realized by adding hardware. It is possible.

The case where the size of the vector table is set to 16 bits has been described. However, when the upper bits of all vector addresses are common, for example, as shown in FIG. Can be a bit. In this case, a register or the like is prepared and a common upper address (8 bits) is stored therein. This makes it possible to significantly reduce the size (capacity) of the entire vector table,
This is particularly effective when the capacity of the M102 or the ROM 103 is small.

Of course, various modifications can be made without departing from the scope of the present invention.

[0077]

As described above, according to the present invention, it is possible to speed up processing when an interrupt process or an exception process occurs without requiring a complicated program, and to further improve versatility. An integrated circuit device capable of performing the above can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating an operation of a microcontroller according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a memory address map in the microcontroller.

FIG. 3 is a schematic diagram illustrating an operation of a microcontroller according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of a memory address map in the microcontroller.

FIG. 5 is a schematic diagram illustrating an operation of a microcontroller according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram showing an example of a memory address map in the microcontroller.

FIG. 7 is a schematic diagram showing a list of vector tables in the microcontroller.

FIG. 8 is a schematic diagram showing a configuration example of a vector table type instruction register unit in the microcontroller.

FIG. 9 is a schematic diagram showing another example of the configuration of the vector table according to the present invention.

FIG. 10 is a schematic configuration diagram of a microcontroller shown to explain a conventional technique and its problems.

FIG. 11 Similarly, in the microcontroller,
FIG. 2 is a schematic diagram showing an example of a memory address map.

FIG. 12 Similarly, in the microcontroller,
FIG. 3 is a schematic diagram showing a list of vector tables.

FIG. 13 Similarly, in the microcontroller,
FIG. 3 is a schematic diagram illustrating a configuration example of a vector table.

[Explanation of symbols]

11 ... fixed vector table 12, 12 ', 12a, 12b, 12c ... new vector table 13, 13a, 13b, 13c ... vector table difference storage register section 14 ... subtraction section 15 ... selector section 16 ... processing section 19 ... vector Table difference storage register switching register section 20 ... Selector section 31 ... Occurrence interrupt type determination section 32 ... Vector table use instruction register section 33 ... Vector table type instruction register section 34 ... Vector table use confirmation section 35 ... Interrupt vector base instruction register section 36 ... Vector address calculation unit 37 ... Processing unit

Claims (20)

[Claims] 1. An integrated circuit device having a vector table for storing a routine address for interrupt processing and exception processing and for storing a branch destination address on a memory, wherein at least two or more types of vector tables are provided. Based on a plurality of vector areas to be stored, selecting means for selecting one of the vector areas, and a branch destination address selected by the selecting means and stored in a vector table stored in the vector area. An integrated circuit device comprising: an arithmetic unit for performing the interrupt processing and the exception processing. 2. The integrated circuit device according to claim 1, wherein the instruction to said selecting means is issued using a register. 3. The apparatus according to claim 1, wherein the instruction to said selecting means is made by using an external input terminal of the apparatus.
3. The integrated circuit device according to claim 1. 4. The integrated circuit device according to claim 1, wherein the plurality of vector areas are all provided in a ROM (Read Only Memory). 5. A method according to claim 1, wherein said plurality of vector areas are partially
2. The integrated circuit device according to claim 1, wherein the integrated circuit device is provided in an AM (random access memory). 6. A first vector area for storing a branch destination address on a memory for storing a first routine program for interrupt processing and exception processing, and a first vector area separately from the first vector area. A second vector area for storing a branch destination address on a memory for storing a second routine program, a storage location of a branch destination address in the first vector area, and a branch destination address in the second vector area. A register area for storing positional difference data with respect to a storage location; a branch destination address stored in the first vector area; or a storage location and a location of a branch destination address stored in the first vector area. Calculated from the difference data,
An integrated circuit device comprising: an arithmetic unit that executes the interrupt processing and the exception processing based on a branch destination address stored in the second vector area. 7. The first routine program has a plurality of subroutine programs, and the first vector area stores a plurality of branch destination addresses respectively corresponding to the plurality of subroutine programs. The integrated circuit device according to claim 6, wherein: 8. The integrated circuit device according to claim 7, wherein said first vector area is provided in a ROM. 9. The second routine program includes a plurality of subroutine programs, and the second vector area stores a plurality of branch destination addresses respectively corresponding to the plurality of subroutine programs. The integrated circuit device according to claim 6, wherein: 10. The apparatus according to claim 9, wherein the second vector area stores a plurality of branch destination addresses respectively corresponding to a plurality of subroutine programs in the first routine program. Integrated circuit device. 11. The integrated circuit device according to claim 9, wherein said second routine program has the same subroutine program as said first routine program. 12. The integrated circuit device according to claim 9, wherein at least a part of the second routine program is different from a subroutine program in the first routine program. 13. The integrated circuit device according to claim 9, wherein the second routine program has only a subroutine program different from the first routine program. 14. The integrated circuit device according to claim 9, wherein said second vector area is provided in a RAM. 15. The integrated circuit device according to claim 9, wherein said second vector area is provided in a ROM. 16. The integrated circuit device according to claim 15, wherein a plurality of second vector areas are provided in said ROM. 17. The integrated circuit device according to claim 6, further comprising a specifying unit for specifying one of said second vector areas. 18. The integrated circuit device according to claim 6, further comprising an upper address register for storing a common upper address of the branch destination address. 19. The method according to claim 19, wherein the operation unit further includes a selection unit that selects one of the first and second vector areas, and the instruction to the selection unit is performed using a register. The integrated circuit device according to claim 6, wherein 20. The arithmetic unit further includes a selection unit for selecting any one of the first and second vector areas, and the instruction to the selection unit is performed by using an external input terminal of the device. 7. The integrated circuit device according to claim 6, wherein: