JP2008090455A - Multiprocessor signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a high speed arithmetic operation by reducing access quantity to an external memory, and efficiently performing the data transfer of processing data even in the case of signal processing when it is necessary to perform the high speed arithmetic operation of data whose capacity is large. <P>SOLUTION: This multiprocessor signal processor is provided with a first processor 2, a second processor 4, a third processor 6, a first local shared memory 8 as a memory connected to an external bus 12, and shared by the first processor 2 and the second processor 4; and a second local shared memory 10 as a memory connected to the external bus 12, and shared by the second processor 4 and the third processor 6, wherein the first local shared memory 8 is provided with a first bank 8A, a second bank 8B, and a third bank 8C, and the second local shared memory 10 is provided with a first bank 10A and a second bank 10B and a third bank 10C. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multiprocessor signal processing apparatus including a plurality of processors.

  2. Description of the Related Art Conventionally, in signal processing that handles a large amount of data at high speed, such as image processing, a technique is known in which the calculation speed is increased by performing calculation by pipeline processing using a multiprocessor.

  When such a technique is used, in order to input the output from one processor to the other processor, a method of performing input / output via an external memory accessible by all the processors can be considered. However, according to this method, when the amount of data to be handled is large as in image processing, the access amount of the external memory becomes too large, and the external memory tends to reach the limit of the operating frequency.

For this reason, for example, the multiprocessor signal processing device disclosed in Patent Document 1 includes a memory (shared memory) that is shared only between adjacent processors, thereby reducing the amount of access to a specific memory. It prevents the increase.
JP 2002-207710 A

  However, since the technology disclosed in Patent Document 1 uses inter-processor communication, each processor is in an inoperable state during inter-processor communication. In other words, the multiprocessor signal processing device provided by the technique disclosed in Patent Document 1 has poor calculation efficiency.

  Furthermore, considering that the shared memory requires a high-speed access function, a relatively expensive memory must be used as the shared memory. Therefore, practically, a large capacity cannot be expected for the shared memory.

  In addition to the shared memory, when a large-capacity memory having a relatively low price but a relatively low price is provided, means for efficiently transferring data between the memory and the shared memory is provided. It becomes necessary newly.

  The present invention has been made in view of the above circumstances, and reduces the amount of access to the external memory and transfers the processed data even during signal processing where a large amount of data must be calculated at high speed. It is an object of the present invention to provide a multiprocessor signal processing apparatus that can perform high-speed computation by performing efficiently.

  To achieve the above object, a multiprocessor signal processing device according to a first aspect of the present invention is a multiprocessor signal processing device comprising a plurality of processors arranged in parallel, and is connected to an external bus, And a local shared memory which is a memory shared by adjacent processors among the plurality of processors, a control processor connected to the external bus and controlling the plurality of processors, and connected to the external bus And an external memory connected to the external bus and a DMA controller for transferring data between the external memory and the local shared memory, the local shared memory comprising a plurality of banks It is characterized by having.

In order to achieve the above object, a multiprocessor signal processing apparatus according to a second aspect of the present invention is the multiprocessor signal processing apparatus according to the first aspect, wherein the multiprocessor signal processing apparatus includes a plurality of parallel processors. The processor located at both ends is connected to a local end memory which is a memory not shared with the other processors, and the local end memory has a plurality of banks. To achieve, a multiprocessor signal processing device according to a third aspect of the present invention is the multiprocessor signal processing device according to the first aspect or the second aspect, wherein each of the processors, the external bus, And a local non-shared memory which is a memory connected to the.

  In order to achieve the above object, a multiprocessor signal processing apparatus according to a fourth aspect of the present invention is the multiprocessor signal processing apparatus according to any one of the first to third aspects. Each of the local shared memory and each of the local end memories is provided with a bank selection register for selecting a bank for each of the processors connected to the local shared memory. The selection register selects a bank for accessing each local shared memory or the local end memory from each processor by a virtual address.

  In order to achieve the above object, a multiprocessor signal processing device according to a fifth aspect of the present invention is the multiprocessor signal processing device according to the fourth aspect, wherein the bank selection register uses the virtual address to A bank for selecting each local shared memory or the local end memory from the bus is selected.

  To achieve the above object, a multiprocessor signal processing apparatus according to a sixth aspect of the present invention is a multiprocessor signal processing apparatus comprising a plurality of processors arranged in parallel, and is connected to an external bus, And a local shared memory that is a memory shared by adjacent processors, an external memory that is a memory connected to the external bus, and data between the external memory and the local shared memory that is connected to the external bus. A DMA controller for performing transfer, wherein each of the local shared memories has a plurality of banks, and at least one of the plurality of processors is connected to the external bus, and the external bus The processor connected to the processor controls the plurality of processors excluding the processor. .

  In order to achieve the above object, a multiprocessor signal processing apparatus according to a seventh aspect of the present invention is the multiprocessor signal processing apparatus according to the fourth to sixth aspects, wherein the plurality of processors At least one of them is a hard accelerator.

  According to the present invention, even at the time of signal processing in which a large amount of data must be calculated at high speed, the amount of access to the external memory can be reduced and the processing data can be efficiently transferred to perform high speed calculation. It is possible to provide a multiprocessor signal processing device that enables this.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First embodiment]
The multiprocessor signal processing apparatus according to the first embodiment of the present invention will be described below. Here, for convenience of explanation, a multiprocessor signal processing apparatus including three signal processing processors will be described as an example.

FIG. 1 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the first embodiment. As shown in FIG. 1, the multiprocessor signal processing apparatus according to the first embodiment is
The first signal processing processor 2, the second signal processing processor 4, the third signal processing processor 6, the first signal processing processor 2, and the first signal processing processor 4 share the first signal processing processor 4. A local shared memory 8, a second local shared memory 10 shared by the second signal processing processor 4 and the third signal processing processor 6, a control processor 14, a DMA (Direct Memory Access) controller 16, and And an external memory 18.

  Here, the first shared memory 8 includes a first bank 8A, a second bank 8B, and a third bank 8C. Similarly, the second shared memory 10 includes a first bank 10A, a second bank 10B, and a third bank 10C.

  The first signal processing processor 2 and the first local shared memory 8 are connected by an internal bus 11A, and the first local shared memory 8 and the second signal processing processor 4 are connected by an internal bus 11B. The second signal processing processor 4 and the second local shared memory 10 are connected by an internal bus 11C, and the second local shared memory 10 and the third signal processing processor 6 are connected by an internal bus 11D. Has been.

  The first local shared memory 8 and the second local shared memory 10 are connected to a control processor 14, a DMA controller 16, and an external memory 18 by an external bus 12.

  In the multiprocessor signal processing apparatus configured as described above, for example, consider the case where the following signal processing is performed. That is, block data obtained by dividing image data, which is large-capacity data stored in the external memory 18, into several parts is sequentially input to the first signal processor 2 to perform the first processing. Then, the output from the first signal processing processor 2 is input to the second signal processing processor 4 to perform the second processing, and the output from the second signal processing processor 4 is further converted into the third signal processing. Consider a process in which a third process is input to the processor 6 and the output from the third signal processor 6 is finally stored in the external memory 18.

  Hereinafter, the data flow in such processing will be described with reference to FIGS.

  The block data stored in the external memory 18 is DMA-transferred by the DMA controller 16 to the third bank 8C of the first local shared memory 8 (process a).

  At the same time as the processing a, the block data already transferred by the previous DMA transfer and stored in the second bank 8B is subjected to the first processing by the first signal processing processor 2, and the processing result Is output to the second bank 8B (process b).

  Note that the processing result of the first processing performed by the first signal processing processor 2 is stored in the first bank 8A.

  Simultaneously with the processing b, the processing result of the first processing by the first signal processing processor 2 is output from the first bank 8A to the second signal processing processor 4 (processing c), and The second processing is performed by the second signal processing processor 4, and the processing result is output to the third bank 10C in the second local shared memory 10 (processing d).

  Note that the processing result of the second processing performed by the second signal processing processor 4 is stored in the second bank 10B of the second local shared memory 10 already.

  Simultaneously with the processing d, the second processing result of the second signal processing processor 4 from the previous time is output from the second bank 10B to the third signal processing processor 6, and for the third signal processing. The third process is performed by the processor 6, and the process result is output to the second bank 10B in the second local shared memory 10 (process e).

  Note that the processing result of the third processing by the third signal processing processor 6 in the previous time is already stored in the first bank 10A of the second local shared memory.

  Simultaneously with the processing e, the processing result of the third processing performed by the third signal processing processor 6 is DMA-transferred from the first bank 10A to the external memory 18 by the DMA controller 16 (processing f). ).

  Then, the fact that all the processes in the processes a to f have been completed is transmitted to the control processor 14 by means such as an interrupt signal.

  The state of bus access shown in FIG. 2 when executing the processing a through the processing f is referred to as phase 1.

  Here, in the next block data processing, as shown in FIG. 3, the first signal processing processor 2, the second signal processing processor 4, the third signal processing processor 6, and the DMA are processed. The bank accessed by the controller 16 is shifted one by one, and the same processing is executed again. The bus access state shown in FIG.

  In the next block data processing, as shown in FIG. 4, the first signal processing processor 2, the second signal processing processor 4, the third signal processing processor 6, and the DMA are processed. The bank accessed by the controller 16 is shifted one by one, and the same processing is executed again. The bus access state shown in FIG.

  Therefore, the bank to be accessed by the first signal processing processor 2, the second signal processing processor 4, the third signal processing processor 6 and the DMA controller 16 also in the processing of the next block data. Since one by one is shifted, the bank access state returns to the phase 1 state shown in FIG. In this way, the process is repeated until the above-described processing is performed on the entire image data constituted by each block data.

  By performing processing in such a procedure, the amount of access to the external memory 18 can be reduced, and the first signal processing processor 2, the second signal processing processor 4, and the third signal processing can be performed. While performing signal processing in the signal processing processor 6, data transfer can be performed simultaneously.

  Although the description has been made assuming that image data is large-capacity data here, the data to be processed is not limited to image data.

  In the multiprocessor signal processing apparatus according to the first embodiment, parameter setting for DMA transfer, register setting for starting DMA transfer, the first signal processing processor 2, and the second signal processing The processing start register setting in the processor 4 and the third signal processing processor 6 is performed by the control processor 14.

  As described above, according to the first embodiment, even during signal processing where a large amount of data must be calculated at high speed, the amount of access to the external memory can be reduced and the data of the processed data can be transferred. It is possible to provide a multiprocessor signal processing device capable of performing high-speed computation by performing efficiently.

  Specifically, different banks in the first local shared memory 8 and the second local shared memory 10 include two adjacent signal processing processors, the control processor 14, and the DMA controller 16, respectively. Can be accessed simultaneously. As a result, the amount of access to the external memory 18 can be reduced, and the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 are performing calculations. Even so, the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 are used by the DMA controller 16 and the control processor 14 in the next calculation. Data is sent from the external memory 18 to the first local shared memory 8 and the second local shared memory 10, or the first signal processing processor 2, the second signal processing processor 4, and the third signal. The calculation result of the processor 6 for processing is sent from the first local shared memory 8 and the second local shared memory 10 before It is possible to send to the external memory 18.

  As described above, according to the multiprocessor signal processing apparatus of the first embodiment, the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 are used. Data transfer of processing data can be performed while performing signal processing. Therefore, as shown in FIG. 5, the processing time in the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 ("first signal processing shown in FIG. 5" Data processor 2 ”,“ second signal processor 4 ”, and“ third signal processor 6 ”are equivalent to the data transfer time (“ input DMA ”and“ output DMA ”shown in FIG. 5). ), The time required for data transfer can be substantially ignored.

[Second Embodiment]
Next, a multiprocessor signal processing apparatus according to a second embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the first embodiment will be described. FIG. 6 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the second embodiment.

  In the multiprocessor signal processing apparatus according to the second embodiment, as shown in FIG. 6, a first local end memory 20 is connected to the first signal processing processor 2 by an internal bus 11E. Similarly, a local end memory 22 is connected to the third signal processing processor 6 by an internal bus 11F. The first local end memory 20 and the second local end memory 22 are memories having the same specifications as the local shared memory.

  That is, the first local end memory 20 includes a first bank 20A, a second bank 20B, and a third bank 20C. Similarly, the second local end memory 22 includes a first bank 22A, a second bank 22B, and a third bank 22C.

  As described above, according to the second embodiment, a multiprocessor signal processing apparatus that achieves a more efficient data flow in addition to the same effects as the multiprocessor signal processing apparatus according to the first embodiment. Can be provided.

  Specifically, in the multiprocessor signal processing apparatus according to the second embodiment, a more efficient data flow is realized by providing the first local end memory 20 and the second local end memory 22.

  Here, as the local end memory, the two local end memories of the first local end memory 20 and the second local end memory 22 are provided, but it is of course possible to provide only one of them.

[Third Embodiment]
Next, a multiprocessor signal processing apparatus according to a third embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the second embodiment will be described. FIG. 7 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the third embodiment.

  As described in the first embodiment, when the bank access state shown in FIG. 2 shifts to the bank access state shown in FIG. 3, for example, the first local shared memory accessed by the first signal processing processor 2 The bank in 8 is switched from the second bank 8B to the third bank 8C.

  Therefore, for example, when the first signal processing processor 2 wants to use a part of the processing result by the first signal processing processor 2 in the phase 1 state even in the phase 2 state, the first signal processing processor 2 An efficient data flow is achieved by providing a non-shared memory associated with the first signal processing processor 2 instead of the local shared memory 8.

  That is, in addition to the first local shared memory 8 and the second local shared memory 10, the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 are associated with each other. By providing a local non-shared memory, which is a non-shared memory, a more efficient data flow can be realized.

  Therefore, in the multiprocessor signal processing apparatus according to the third embodiment, as shown in FIG. 7, a first local non-shared memory 24 is provided in association with the first signal processing processor 2, and the second signal A second local unshared memory 26 is provided in association with the processing processor 4, and a third local non-shared memory 28 is provided in association with the third signal processing processor 6.

  Thereby, for example, when there is a parameter that the first signal processing processor 2 uses in common in any phase state shown in FIGS. 2 to 4, the same parameter is stored in the first local shared memory 8. It is not necessary to store in all banks, and efficient data flow can be realized by storing only in the first local non-shared memory 24.

  Further, regarding the storage of data in the middle of computation, a more efficient data flow can be obtained by using the first local non-shared memory 24, the second local non-shared memory 26, and the third local non-shared memory 28. Can be realized.

  As described above, according to the third embodiment, the same effect as that of the multiprocessor signal processing apparatus according to the second embodiment can be obtained, and a more efficient data flow can be realized. A signal processing apparatus can be provided.

  Specifically, the first local non-shared memory 24, the second local non-shared memory 26, and the third local non-shared memory 28 are part of the calculation results in the phase 1 shown in FIG. Thus, it is possible to realize a more efficient data flow by storing data used in the phase 2 shown in FIG. 3 and storing parameters used in common in any phase.

  That is, according to the multiprocessor signal processing device according to the third embodiment, the memory capacity of the first local shared memory 8 and the second local shared memory 10 can be reduced, and various signal processing can be supported. can do.

[Fourth Embodiment]
Next, a multiprocessor signal processing apparatus according to a fourth embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the third embodiment will be described.

  FIG. 8 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the fourth embodiment. As shown in the figure, in the multiprocessor signal processing apparatus according to the fourth embodiment, a bank selection register 30 is selected for the first local end memory 20 and a bank is selected for the first local shared memory 8. A register 32 is provided with a bank selection register 34 connected to the second local shared memory 10 and a bank selection register 36 connected to the second local end memory 22. That is, in the multiprocessor signal processing apparatus according to the fourth embodiment, a register for designating the bank number (first to third) of the memory is provided for each memory.

  FIG. 9 is a diagram showing a configuration example of an address space of the second signal processing processor 4 in the multiprocessor signal processing apparatus according to the fourth embodiment. FIG. 10 is a diagram showing a register for selecting which bank of the first local shared memory 8 the virtual address indicates. FIG. 11 shows a register for selecting which bank the virtual address indicates the second local shared memory 10.

  Here, in the address space of the second signal processing processor 4 shown in FIG. 9, 0x00000 and 0x04000 are virtual addresses. As shown in the figure, 0x01000 corresponds to the first bank 8A of the first local shared memory 8, 0x02000 corresponds to the second bank 8B of the first local shared memory 8, and 0x03000 corresponds to the first local shared memory 8. This corresponds to the third bank 8C of the shared memory 8.

  The bank to which the virtual address 0x00000 points is determined by the register setting shown in FIG. That is, the 2-bit values 00, 01, and 10 of the register indicate the first bank 8A, the second bank 8B, and the third bank 8C, respectively. The 2-bit value 11 is not used.

  For example, as shown in FIG. 10, since the virtual address when accessing the first local shared memory 8 from the second signal processor 4 is 10 in binary, it corresponds to the third bank 8C. ing.

  On the other hand, 0x05000 corresponds to the first bank 10A of the second local shared memory 10, 0x06000 corresponds to the second bank 10B of the second local shared memory 10, and 0x07000 corresponds to the third bank of the third local shared memory 10. Corresponds to bank 10C.

  The bank to which the virtual address 0x04000 indicates is determined by the register setting shown in FIG. That is, the 2-bit values 00, 01, and 10 of the register indicate the first bank 10A, the second bank 10B, and the third bank 10C, respectively. The 2-bit value 11 is not used.

  For example, as shown in FIG. 11, since the virtual address when accessing the second local shared memory 10 from the second signal processing processor 4 is 00 in binary, it corresponds to the first bank 10A. is doing.

  As for the virtual addresses for accessing the first local end memory 20 and the second local end memory 22, as in the case of the first local shared memory 8 and the second local shared memory 10, Of course, it is possible to set a register to indicate a bank.

  As described above, according to the fourth embodiment, the same effect as that of the multiprocessor signal processing apparatus according to the third embodiment can be obtained, and a more efficient data flow can be realized. A signal processing apparatus can be provided.

  That is, according to the multiprocessor signal processing device of the fourth embodiment, the phase changes without rewriting the address by switching the setting of the bank selection registers 30, 32, 34, and 36 when the phase changes. You can run the same program as before. In other words, it is not necessary to write addresses in the three phases when a predetermined program is created.

[Fifth Embodiment]
Next, a multiprocessor signal processing apparatus according to a fifth embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the fourth embodiment will be described. The configuration of the multiprocessor signal processing apparatus according to the fifth embodiment is the same as the configuration of the multiprocessor signal processing apparatus according to the fourth embodiment shown in FIG.

  FIG. 12 is a diagram showing an address space used when accessing from the external bus 12 in the multiprocessor signal processing apparatus according to the fifth embodiment. In other words, FIG. 12 is a diagram showing an address space when accessing from the control processor 14 or the DMA controller 16.

  FIG. 13 is a diagram showing a register for selecting which bank of the first local shared memory 8 the virtual address indicates. FIG. 14 is a diagram showing a register for selecting which bank of the second local shared memory 10 the virtual address indicates.

  Here, of the addresses when accessing from the external bus 12 shown in FIG. 12, 0x800000 and 0x804000 are virtual addresses. As shown in the figure, 0x801000 corresponds to the first bank 8A of the first local shared memory 8, 0x802000 corresponds to the second bank 8B of the first local shared memory 8, and 0x803000 corresponds to the first local shared memory 8. This corresponds to the third bank 8C of the shared memory 8.

  The bank to which the virtual address 0x800000 points is determined by the register setting shown in FIG. That is, the 2-bit values 00, 01, and 10 of the register indicate the first bank 8A, the second bank 8B, and the third bank 8C, respectively. The 2-bit value 11 is not used.

  For example, as shown in FIG. 13, since the virtual address when accessing the first local shared memory 8 from the external bus 12 is 00 in binary, it corresponds to the first bank 8A.

  On the other hand, 0x805000 corresponds to the first bank 10A of the second local shared memory 10, 0x806000 corresponds to the second bank 10B of the second local shared memory 10, and 0x807000 corresponds to the third bank of the third local shared memory 10. Corresponds to bank 10C.

  The bank to which the virtual address 0x804000 points is determined by the register setting shown in FIG. That is, the 2-bit values 00, 01, and 10 of the register indicate the first bank 10A, the second bank 10B, and the third bank 10C, respectively. The 2-bit value 11 is not used.

  For example, since the virtual address when accessing the second local shared memory 10 from the external bus 12 is 10 in binary, it corresponds to the third bank 10C.

  As for the virtual addresses for accessing the first local end memory 20 and the second local end memory 22, as in the case of the first local shared memory 8 and the second local shared memory 10, Of course, it is possible to set a register to indicate a bank.

  As described above, according to the fifth embodiment, the same effect as that of the multiprocessor signal processing apparatus according to the fourth embodiment can be obtained, and a more efficient data flow can be realized. A signal processing apparatus can be provided.

  Specifically, according to the multiprocessor signal processing apparatus according to the fifth embodiment, from the external bus 12, the first shared memory 8, the second local shared memory 10, the first local end memory 20, It is possible to use a virtual address when accessing the second local end memory 22.

[Sixth Embodiment]
Next, a multiprocessor signal processing apparatus according to the sixth embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the fifth embodiment will be described.

  FIG. 15 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the sixth embodiment.

  As shown in the figure, in the multiprocessor signal processing device according to the sixth embodiment, the control processor 14 included in the multiprocessor signal processing device according to the fifth embodiment is not provided. A two-signal processor 4 is connected to the external bus 12 by a bus 40.

  In the multiprocessor signal processing apparatus according to the sixth embodiment, the second signal processing processor 4 performs processing as the control processor 14 through the external bus 12 and the bus 40.

  Here, the processing as the control processor 14 includes, for example, DMA control, control of the first signal processing processor 2 and the second signal processing processor 4, setting of each bank selection register, Access to the first local shared memory 8 and the second local shared memory 10, access to the first local end memory 20 and the second local end memory 22, the first local non-shared memory 24, the second local This is processing such as access to the non-shared memory 26 and the third local non-shared memory 28.

  As described above, according to the sixth embodiment, there is provided a multiprocessor signal processing apparatus having the same effects as the multiprocessor signal processing apparatus according to the fifth embodiment without providing the control processor 14. Can be provided.

  As described above, the second signal processing processor 4 does not have the function as the control processor 14, but the first signal processing processor 2 or the third signal processing processor 6. Of course, the function of the control processor 14 may be assigned.

  Of course, by connecting a plurality of signal processing processors to the external bus 12, the plurality of signal processing processors may cooperate to perform the processing as the control processor 14.

[Seventh Embodiment]
A multiprocessor signal processing apparatus according to a seventh embodiment of the present invention will be described. Only differences from the multiprocessor signal processing apparatus according to the fifth embodiment will be described.

  FIG. 16 is a block diagram showing the configuration of the multiprocessor signal processing apparatus according to the seventh embodiment.

  As shown in the figure, the multiprocessor signal processing apparatus according to the seventh embodiment includes a hard accelerator 50 specialized for special processing instead of the third signal processing processor 6. That is, the hard accelerator 50 is connected to the second local end memory 22, the second local shared memory 10, and the third local non-shared memory 28.

  Under such a configuration, a predetermined value can be written in a register corresponding to the hard accelerator 50 by the control processor 14 to cause the hard accelerator 50 to execute a special process.

  As described above, according to the seventh embodiment, the same effects as the multiprocessor signal processing apparatus according to the fifth embodiment can be obtained, and the hard accelerator 50 can perform special processing. A processor signal processing apparatus can be provided.

  As mentioned above, although this invention was demonstrated based on 1st Embodiment thru | or 7th Embodiment, this invention is not limited to embodiment mentioned above, A various deformation | transformation and application are within the range of the summary of this invention. Of course it is possible.

  For example, in the first to seventh embodiments, the description has been made assuming that three signal processing processors are used as the signal processing processors. However, what is necessary is that the number of signal processing processors is two or more. Of course, it may be individual.

  The processor actually used as the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 includes various processors such as a RISC processor, a DSP, and a SIMD. Of course, the embodiments described above can be applied to any type of processor. Further, the first signal processing processor 2, the second signal processing processor 4, and the third signal processing processor 6 do not need to use the same type of processors, but use different types of processors. Of course.

  Note that various processors such as RISC processor, DSP, and SIMD can be used as the processor actually used as the control processor 14.

  Further, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram showing a configuration of a multiprocessor signal processing apparatus according to a first embodiment of the present invention. The figure which shows the data flow in the signal processing by the multiprocessor signal processing apparatus which concerns on 1st Embodiment of this invention. The figure which shows the data flow in the signal processing by the multiprocessor signal processing apparatus which concerns on 1st Embodiment of this invention. The figure which shows the data flow in the signal processing by the multiprocessor signal processing apparatus which concerns on 1st Embodiment of this invention. The figure which shows typically the signal processing time by the multiprocessor signal processing apparatus which concerns on 1st Embodiment of this invention. The block diagram which shows the structure of the multiprocessor signal processing apparatus which concerns on 2nd Embodiment of this invention. The block diagram which shows the structure of the multiprocessor signal processing apparatus which concerns on 3rd Embodiment of this invention. The block diagram which shows the structure of the multiprocessor signal processing apparatus which concerns on 4th Embodiment of this invention. The figure which shows the example of 1 structure of the address space of the processor for 2nd signal processing in the multiprocessor signal processing apparatus which concerns on 4th Embodiment of this invention. The figure which shows the register | resistor which selects which bank of a 1st local shared memory a virtual address points out. The figure which shows the register | resistor which selects which bank of a 2nd local shared memory a virtual address points out. The figure which shows the address space used when accessing from an external bus in the multiprocessor signal processing apparatus which concerns on 5th Embodiment of this invention. The figure which shows the register | resistor which selects which bank of a 1st local shared memory a virtual address points out. The figure which shows the register | resistor which selects which bank of a 2nd local shared memory a virtual address points out. The block diagram which shows the structure of the multiprocessor signal processing apparatus which concerns on 6th Embodiment of this invention. The block diagram which shows the structure of the multiprocessor signal processing apparatus which concerns on 7th Embodiment of this invention.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 2 ... Processor for 1st signal processing, 4 ... Processor for 2nd signal processing, 6 ... Processor for 3rd signal processing, 8 ... 1st local shared memory, 8A ... 1st bank, 8B ... 2nd bank, 8C ... 1st 3 banks, 10 ... second local shared memory, 10A ... first bank, 10B ... second bank, 10C ... third bank, 11A, 11B, 11C, 11D, 11E, 11F ... internal bus, 12 ... external bus, 14 ... Control processor, 16 ... DMA controller, 18 ... External memory, 20 ... First local end memory, 20A ... First bank, 20B ... Second bank, 20C ... Third bank, 22 ... Second local end memory, 22A ... 1st bank, 22B ... 2nd bank, 22C ... 3rd bank, 24 ... 1st local unshared memory, 26 ... 2nd b Cal unshared memory, 28 ... third local unshared memory, 30, 32, 34, 36 ... bank select register, 40 ... bus, 50 ... hard acceleration.

Claims (7)

A multiprocessor signal processing apparatus comprising a plurality of processors arranged in parallel,
A local shared memory that is connected to an external bus and is a memory shared by adjacent processors among the plurality of processors;
A control processor connected to the external bus for controlling the plurality of processors;
An external memory that is a memory connected to the external bus;
A DMA controller connected to the external bus for transferring data between the external memory and the local shared memory;
Comprising
The multiprocessor signal processing apparatus, wherein the local shared memory has a plurality of banks. Among the plurality of processors arranged side by side, the processors located at both ends are provided with a local end memory that is a memory not shared with the other processors,
The multiprocessor signal processing apparatus according to claim 1, wherein the local end memory includes a plurality of banks.   3. The multiprocessor signal processing apparatus according to claim 1, further comprising a local non-shared memory that is a memory connected to each of the processors and the external bus. Each local shared memory and each local end memory are provided with a bank selection register for selecting a bank for each processor connected to each local memory,
4. The bank selection register selects a bank for accessing each local shared memory or each local end memory from each processor by a virtual address. 5. A multiprocessor signal processing device according to claim 1.   5. The multiprocessor signal processing apparatus according to claim 4, wherein the bank selection register selects a bank for accessing the local shared memory or the local end memory from the external bus by a virtual address. . A multiprocessor signal processing apparatus comprising a plurality of processors arranged in parallel,
A local shared memory that is connected to the external bus and is shared by adjacent processors;
An external memory that is a memory connected to the external bus;
A DMA controller connected to the external bus for transferring data between the external memory and the local shared memory;
Comprising
Each of the local shared memories has a plurality of banks, and at least one of the plurality of processors is connected to the external bus, and the processor connected to the external bus excludes the processor. A multiprocessor signal processing apparatus for controlling the plurality of processors.   7. The multiprocessor signal processing apparatus according to claim 4, wherein at least one of the plurality of processors is a hard accelerator.

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