JP2001168094A - Wiring structure, wiring forming method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure, a wiring forming method and a semiconductor device which allows the radiation area to be increased, without deteriorating the substrate strength. SOLUTION: In a multi-finger, emitter-up type hetero-junction bipolar transistor, an air-bridge-like compact lower layer wiring 12 for interconnecting electrodes 8 is formed, then a substrate 2 is dipped in an Au plating liquid (at a liquid temperature of 65 deg.C) having an Au content of e.g. 3 grams/liter, and a current is fed to the plating lower film at a current density of 3 mA/cm2 to electroplate the substrate, thereby forming an upper wiring 13 with the plating metal growing in a dendritic shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure, a wiring forming method, and a semiconductor device.

[0002]

2. Description of the Related Art In a high-output transistor such as a high-output bipolar transistor or a field-effect transistor, it is necessary to supply a large current to the element in order to obtain a high output. As a result, the amount of heat generated increases, the temperature rise increases with the drive time, and the temperature exceeds the temperature range in which the transistor operates normally. In the worst case, the transistor is destroyed. In particular, GaAs has a thermal conductivity of 54 W / m ° C., and a thermal conductivity of Si of 150 W / m ° C.
Since it is about 1/3 smaller than W / m ° C., in a semiconductor device manufactured using a GaAs substrate, an increase in element temperature is an important problem.

Conventionally, to reduce the thermal resistance of a semiconductor device formed on a GaAs substrate, a GaAs substrate has
The thickness is reduced to about 0 μm, and a heat sink made of thick Au plating is formed on the back surface of the GaAs substrate so that heat is radiated from the heat sink (InGaP / GaAs).
Application of HBT power amplifier for mobile phone; Journal of Applied Electronic Properties, Vol. 4, No. 4 (published September 1, 1998), 1
36-141).

Further, Japanese Patent Application Laid-Open Nos. 8-204181 and 7-111272 disclose a structure in which a heat radiating member is provided on an electrode portion.

Further, there is a case where a heat radiating plate is formed on a substrate, the heat radiating plate is connected to an electrode near a heat-generating portion by a thick wiring layer, and heat is radiated through the wiring layer and the heat radiating plate. Development of AlGaAs HBT MMIC for Mobile Phone; Journal of Applied Electronic Properties, Vol. 4, No. 4, September 1998
Published on March 1), pages 130-135).

[0006]

However, the heat dissipating members and the heat dissipating plates formed on the electrode portions and the wiring layers are formed of a dense material, so that a sufficient heat dissipating area cannot be obtained and the heat dissipating efficiency is reduced. It was low. Also, in the method of reducing the thermal resistance by thinning the semiconductor substrate and providing the Au plating thick film on the back surface, the heat radiation area can be increased, but the substrate is easily broken, and the handling in the subsequent steps becomes difficult. There was a problem.

[0007]

DISCLOSURE OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a wiring structure capable of increasing a heat radiation area without reducing the strength of a substrate. To provide a wiring forming method and a semiconductor device.

Thus, in the wiring structure and the semiconductor device according to the present invention, fine voids are formed in at least a part of the inside of the metal wiring. Here, in the present specification, the fine voids are not limited to those in which the corresponding portions of the metal wiring are formed in a porous shape (preferably continuous air bubbles), and are caused by fine wrinkles and grooves on the surface. It may be one in which a void is formed. The wiring is not limited to a wiring drawn from an electrode or a pad or a wiring connecting electrodes or pads, but also includes an electrode or a pad itself. The part of the wiring may refer to, for example, a partial section along the length direction of the wiring, or may refer to a part of the layer in the case of a multilayer wiring.

If a minute gap is formed in at least a part of the inside of the metal wiring as described above, the heat radiation area in that part can be increased, and the heat radiation efficiency can be improved. In particular, a large heat dissipation area can be obtained even with fine wiring in which a large heat dissipation member could not be provided.

The metal wiring is desirably provided near the heat-generating portion, and is preferably used, for example, as a metal wire for connecting electrodes located near the heat-generating portion.

In order to form a metal wiring having such fine voids, there is a method of performing electrolytic plating using a plating solution having a small content of a plating metal. Electroplating is performed using a plating solution having a low plating metal content, for example, a plating solution having a plating metal content of about 2/3 or less of the minimum plating metal content for obtaining a dense plating metal layer. In such a case, since a dense metal wiring cannot be obtained, the metal wiring includes fine voids.

Further, in another wiring structure and a semiconductor device according to the present invention, dendrites are formed on at least a part of the surface or inside of the metal wiring. Here, the dendritic shape refers to a shape as if the metal element is roughly deposited and growing as a dendritic shape. According to the dendrite, the heat radiation area can be increased, and thus the heat radiation efficiency from the metal wiring can be increased. In particular, a large heat dissipation area can be obtained even with fine wiring in which a large heat dissipation member could not be provided.

This metal wiring is desirably provided near the heat-generating portion, and is preferably used, for example, as a metal wire connecting electrodes located near the heat-generating portion.

In order to form a metal wiring having such minute voids, there is a method in which electrolytic plating is performed using a plating solution having a low plating metal content. Electroplating is performed using a plating solution having a low plating metal content, for example, a plating solution having a plating metal content of about 2/3 or less of the minimum plating metal content for obtaining a dense plating metal layer. And, as the plated metal grows in a tree shape,
Fine dendrites can be formed.

[0015]

(First Embodiment) FIG. 1 (a)
(B), (c), and (d) are cross-sectional views showing one embodiment of the present invention, in which a wiring 1 for connecting between emitter electrodes 8 is formed in a multi-finger emitter-up heterojunction bipolar transistor. Is represented. FIG. 1A shows a basic structure of an emitter-up type heterojunction bipolar transistor. A collector contact layer (n-GaAs layer) 3 is formed by doping Si at a high concentration on a semi-insulating GaAs substrate 2, and unit element portions 4 are arranged on the collector contact layer 3. Each unit element portion 4 includes a collector layer (GaAs layer) 5 from the lower layer,
Base layer (C-doped p-GaAs layer) 6, Emitter layer (Si-doped n-InGaP layer) 7
The emitter layer 7 has a base layer 6
A wider gap material is used. Further, an emitter electrode 8 is formed on the emitter layer 7,
A base electrode 9 is formed on the base layer 6, and a collector electrode 10 is formed on the upper surface of the collector contact layer 3 between the unit element portions 4. Such an emitter-up type heterojunction bipolar transistor has high efficiency and
It has a feature of low distortion power, and the portion near the center of the bonding surface between the collector layer 5 and the base layer 6 becomes a large heat-generating portion. In this emitter-up type heterojunction bipolar transistor, the emitter electrodes 8 of each unit element portion 4 are connected to each other by a wiring 1 having a two-layer structure having an air bridge structure as described below.

When the structure as shown in FIG. 1A is completed, a photoresist 11 is applied to the entire upper surface of the substrate 2, and then a part of the photoresist 11 is opened by photolithography to form an emitter electrode 8 from the photoresist 11. Expose. Then, after forming a plating base film 12a of a desired pattern by vapor deposition, sputtering, chemical plating, or the like, the substrate 2 is immersed in an Au plating solution (solution temperature 65 ° C.) having, for example, an Au content of 10 g / liter, and plating is performed. Base film 12a
By applying an electric current at a current density of 3 mA / cm ² to perform electroplating, Au is deposited on the plating base film 12a, and as shown in FIG.
A fine Au plating layer of μm is formed.

Next, as shown in FIG.
Au plating solution containing 3 g / L Au (solution
The substrate 2 is immersed in the substrate at a temperature of 65 ° C.
cm ²Current at a current density to perform electrolytic plating.
Then, a 2 μm thick Au plating layer is formed as the upper wiring 13.
To achieve. Thereafter, the photoresist 11 is peeled off.
As a result, as shown in FIG.
Consists of a lower wiring 12 and an upper wiring 13 between the emitter electrodes 8
The air bridge-shaped wiring 1 is formed.

FIGS. 2 and 3 show the case where the wiring is formed using the plating solution having a small content of the plating metal as described above, and the case where the wiring is formed using the plating solution having a sufficient content of the plating metal. This is shown in comparison with the case of performing (normal electrolytic plating method). FIGS. 3A and 3B show a perspective view and a side view of a wiring formed by a normal electrolytic plating method, which is a metal wiring of a dense material. In contrast,
When the wiring is formed using a plating solution having a small content of the plating metal, the plating metal grows like a tree on the lower wiring 12 as shown in FIG. For this reason, the upper layer wiring 13 is a metal wiring of a coarse density having a large void inside the tree-like portion or between the tree-like portions, and a wiring having a large surface area can be obtained. Further, in FIG. 2, the space between the projections growing in a tree-like manner with a small deposition amount of the plating metal is large, but when the deposition amount of the plating metal increases and the space between the projections is buried, the upper layer wiring 13 becomes It becomes porous.

When the wiring 1 is formed in this manner, the Au plating layer of the lower wiring 12 has a dense structure and a required current capacity can be obtained, and the Au plating layer of the upper wiring 13 has a large void. As a result, the surface area (radiation area) can be increased, so that the heat transmitted to the wiring 1 through the emitter electrode 8 from the portion generating a large amount of heat can be effectively radiated into the atmosphere. Therefore, the thermal resistance of the heterojunction bipolar transistor can be reduced, and the transistor can operate stably up to a large current range.

In the above embodiment, an emitter-up type heterojunction bipolar transistor has been described. However, in a collector-up type heterojunction bipolar transistor, a wiring connecting collector electrodes may be formed as described above. The wiring structure is not limited to two layers, and may be a multilayer structure of three or more layers.

(Second Embodiment) FIGS. 4A, 4B, 5 and 6 show another embodiment of the present invention.
The wiring structure of the present invention is applied to a crossover wiring connecting between drain electrodes 25 of a field effect transistor formed on a substrate 22.

FIGS. 4A and 4B show crossover wiring 2
8A and 8B are a plan view and a cross-sectional view illustrating a structure of a field-effect transistor on which No. 8 is formed. As shown in FIGS. 4A and 4B, an active layer 23 is formed on a GaAs substrate 22, and a comb-shaped drain electrode 24 is provided on the active layer 23. I have. A source electrode 25 is provided between the fingers of the drain electrode 24. In the gap between the finger of the drain electrode 24 and the source electrode 25, a shallow recess 29 is formed in the surface of the active layer 23. In the recess 29, the finger is inserted between the finger of the drain electrode 24 and the source electrode 25. In this manner, a comb-shaped gate electrode 26 is formed.

In order to electrically connect source electrodes 25 of this field effect transistor, a drain electrode 24
An insulating film 27 is formed on the substrate 22 so as to cross the fingers of the gate electrode 26 and the source electrode 25, and the upper surface of the source electrode 25 is exposed from the insulating film 27 by opening a part of the insulating film 27. A 100-nm-thick Ti layer on the insulating film 27 in order from the lower layer,
A crossover wiring 28 composed of a Pt layer having a thickness of 50 nm and an Au layer having a thickness of 1000 nm is formed. The crossover wiring 28 formed in this manner is
Is electrically connected to the source electrode 25 through the opening.

When the formation of the crossover wiring 28 is completed, a photoresist 30 is applied to the entire substrate from above the crossover wiring 28 and the crossover wiring 28 is formed.
Is appropriately patterned so that a part of the substrate is exposed, and a plating base film 31 is formed by a sputtering method or the like. Then, a photoresist 32 is applied, and patterning is performed so that a portion of the crossover wiring 28 exposed by the photoresist 30 is exposed. And, for example, when the content of Au is 3
Substrate 2 in gram / liter gold plating solution (solution temperature 65 ° C)
2 is immersed in the plating base film 31 and a current density of 3 mA / cm ² is applied to perform electrolytic plating, thereby obtaining a thickness of 3 μm.
Then, a heat radiating portion 33 is formed on the exposed portion of the crossover wiring 28 as shown in FIG. Then
As shown in FIG. 6, the photoresist 30 is peeled from the substrate 22. The heat radiating portion 33 formed integrally with the crossover wiring 28 in this manner is also electrolytically plated using a plating solution having a small content of plating metal.
Is a rough metal layer having voids inside, the surface area of the heat dissipating portion 33 is increased, and heat can be effectively dissipated into the atmosphere.
Can be reduced. Therefore, heat generated in the element can be effectively radiated, and the field effect transistor can be stably operated up to a large current range.

In the above embodiment, the crossover wiring connecting the source electrodes of the field effect transistors has been described. However, the present invention can be applied to the crossover wiring connecting the drain electrodes of the field effect transistors. it can. Furthermore, other than the crossover wiring, the source electrode, the drain electrode, and the gate electrode of the field effect transistor and the lead wiring of each electrode,
The present invention can also be used for a collector electrode, an emitter electrode, and a base electrode of a bipolar transistor and a lead wiring of each electrode.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are diagrams illustrating a method for forming a metal wiring according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a metal wiring manufactured by the same method as the upper wiring of the metal wiring according to the first embodiment.

FIGS. 3 (a) and 3 (b) are a perspective view and a side view showing, on an enlarged scale, a metal wiring produced by a normal electrolytic plating method.

4A is a plan view and a cross-sectional view illustrating a method for forming a metal wiring according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line XX of FIG.

FIG. 5 is a cross-sectional view showing a step of forming a heat radiating portion on the crossover wiring of FIG.

FIG. 6 is a cross-sectional view of a field effect transistor having a heat radiating portion formed on a crossover wiring.

[Explanation of symbols]

 Reference Signs List 1 wiring 8 emitter electrode 12 lower layer wiring 13 upper layer wiring 21 wiring 25 source electrode 28 crossover wiring 33 radiator

Claims (7)

[Claims] 1. A wiring structure in which a metal wiring is formed on a substrate, wherein fine voids are formed in at least a part of the inside of the metal wiring. 2. A wiring structure in which metal wiring is formed on a substrate, wherein a tree-like projection is formed on at least a part of the surface or inside of the metal wiring. 3. A semiconductor device having a wiring structure in which a metal wiring is formed on a semiconductor substrate, wherein fine voids are formed in at least a part of the inside of the metal wiring. 4. A semiconductor device in which a metal wiring is formed on a semiconductor substrate, wherein a tree-like projection is formed on at least a part of the surface or inside of the metal wiring. 5. The semiconductor device according to claim 3, wherein the metal wiring connects between electrodes located near a heat generating portion. 6. A wiring forming method, wherein a metal layer having fine voids is formed by performing electroplating using a plating solution having a low plating metal content. 7. A wiring forming method, wherein a plating metal is grown in a tree shape by performing electrolytic plating using a plating solution having a small content of the plating metal.