JP2006229218A - Method for manufacturing semiconductor device and resulting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a device, which is a semiconductor device, especially a high frequency and high power device having a plurality of gates formed like fingers, such as HEMT, and is smaller than a well-known air bridge structure, and is required to be high in heat dissipating properties. <P>SOLUTION: The method is suitable for producing the high power device, such as high electron mobility transistor (HEMT). The semiconductor device has a plurality of groups composed of a source, a drain, and a gate contact, or a plurality of groups composed of an emitter, a base, and a collector contact, and respective kinds of contacts in the groups are connected with a common gate, drain and source (or base, collector, emitter) contact. The device is not produced by the air bridge structures, but by etching vias through the semiconductor layer, and directly connected to a contact layer on the backside of the device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a plurality of source-gate-drain combinations, in particular, a high gate having a plurality of gates in a finger shape, that is, having at least two or more gate contacts on the same substrate. It relates to devices designed to operate at high frequencies and high power levels, such as electron mobility transistors (HEMTs).

  In general, high frequency and power devices face the challenge of thermal management. In HEMT devices, heat is generated, particularly in the channel, but in a very narrow region near the gate region. This heat must be removed in an effective manner.

  The default way to fabricate a HEMT with a plurality of gates in the form of fingers is to grow a semiconductor stack (eg, a GaN / AlGaN stack) on a first substrate, for example a sapphire substrate, to form ohmic contacts, gates To provide metal and contact metal and passivation layers and to add on-device structures called “air bridges” to connect adjacent contacts with similar functions. Then, flip chip bumps are added around the HEMT, or flip chip bumps are added to the second substrate. The first substrate is then cut into small pieces to form individual devices, which are subsequently attached to the second substrate by flip chip techniques. An air bridge collects the heat generated in the HEMT and removes it laterally. This heat is further removed vertically by flip chip bumps. However, this will result in a device having a significant height.

  US 2003/0040145 A1 describes a method for moving and stacking semiconductor devices. According to this method, a single-gate HEMT device is formed on a first substrate, the first substrate is cut into individual devices, and the individual devices are separated through a bonding layer. It can be manufactured by attaching to two substrates. Applying the same method to a HEMT having a plurality of gates in a finger shape is not a trivial step in view of the need to provide a connection between adjacent contacts in a different manner compared to an air bridge structure.

  U.S. Patent Application Publication No. 2001/105043 relates to a semiconductor device and a method of manufacturing the same, in which a plurality of bipolar transistors are manufactured on a substrate. This substrate is inverted onto a second substrate, and the active area of the device is connected by a metal layer that is applied to the back of the device after the creation of the via hole. These transistors are then cut into small pieces, for example HEMTs, but individual single gate devices are formed. In this disclosure, it is not necessary to connect corresponding regions (eg, bases) of separate transistors into a single device (eg, having multiple bases), so this document avoids air bridges. There is no response to the problem of doing.

  U.S. Pat. No. 6,214,639 describes a multi-fingered HEMT in which a source region, a gate region, and a drain region are through-holes to a lateral region connected to the device's multiple sources, drains, and gates. By making contact from the back of the device. However, this technique requires the provision of at least one air bridge. This is indicated by the dashed line in FIG. 1a of US Pat. No. 6,214,639, over region 14 representing the gate contact region. In these broken lines, the region 12 crosses the gate region. At these locations, an air bridge is required to separate the contact regions 12 and 14.

  US Patent Application Publication No. 2005/0127397 describes a GaN device having a thermal diffusion layer and a thermal via. However, the problem of avoiding air bridges is not addressed here. Furthermore, this heat sink is not used because it connects separate areas of the device.

US Patent Application Publication No. 2003/0040145 US Patent Application Publication No. 2001/0005043 US Pat. No. 6,214,639 US Patent Application Publication No. 2005/0127397

  The present invention is a semiconductor device, particularly a high-frequency and high-power device such as a HEMT having a plurality of gates in a finger shape, which is smaller than a known air bridge structure and has specifications required for heat dissipation. It is an object to provide a method for manufacturing a device that is still in the range of

  The present invention relates to a method as defined in the appended claims and to a device manufactured by applying this method. As claimed in claim 1, the present invention comprises a plurality (ie, at least two) groups of gate / drain / source contacts, or the same but base / collector / emitter contacts, The present invention relates to a method for manufacturing a semiconductor device in which each type of contact in the group is connected to a common gate, drain, and source (or base, collector, emitter) output contact. Preferred embodiments are HEMTs with multiple gates in the form of fingers and multiple base bipolar transistors. In all of the following description, the term “gate, source, drain” contact is used for the sake of brevity. However, it should be noted that these expressions can always be replaced by “base, emitter, collector” respectively.

  The basic features of the invention are set forth in the appended claim 1. A first substrate having a semiconductor stack or semiconductor layer on the front side, wherein a plurality of gate contacts are respectively formed on the layer to produce a plurality of source-gate-drain structures. A first substrate is provided that is positioned between the contacts. This first substrate is probably, but not necessarily, reversed, onto the second substrate, then penetrates the semiconductor layer and if the first substrate has not been removed, or is partially removed by a thinning step. If so, contact is made to the device from the back (the opposite side of the gate / source / drain) by etching the via through the first substrate itself. According to another embodiment, the first substrate is completely removed after the device is inverted onto the second substrate, and the vias are etched into the semiconductor layer.

  In all embodiments, vias are etched in a specific manner with respect to the ohmic contact. The term “ohmic contact” refers to a contact region that forms a direct ohmic contact with an active region defined as a source and drain on a semiconductor layer.

  According to the invention, vias are provided directly on each of the at least one ohmic contact, for example directly on all source contacts, so that the ohmic contacts are exposed and subsequently applied. The contact layer can be contacted. In this way, direct contact can be made with at least one ohmic contact (eg, all source ohmic contacts). The remaining types of ohmic contacts can be contacted in other ways, such as vias to the side contact areas (ie, vias not overlying the actual ohmic contact) it can. Alternatively, all two types of ohmic contacts (preferably source and drain) may be in direct contact via via holes provided directly on these types of contacts.

  By providing a via directly over at least one type of contact, i.e., making direct contact to that type of ohmic contact, there is no need to apply an air bridge to achieve the required connection. This will be described in more detail with reference to the drawings.

According to the first embodiment, the method of the present invention comprises the following basic steps.
A first substrate having a semiconductor stack or semiconductor layer on the front side, wherein a plurality of gate contacts are respectively provided on said layer to produce a plurality of source-gate-drain structures; Providing a first substrate located between (ohmic contacts).
A step of preparing a second substrate provided with an adhesive layer.
Attaching the first substrate to the second substrate by attaching the front surface of the first substrate to the adhesive layer of the second substrate; This means that the gate contact is in direct contact with the adhesive layer if no additional layer is deposited over the gate contact.
After the step of attaching the first substrate, removing the first substrate from the semiconductor layer and exposing a back surface of the semiconductor layer;
Etching the via through the semiconductor layer in the manner described above.
Manufacturing a connection contact layer on the semiconductor layer to provide a connection between the source-gate-drain structures; This provides a functional device on the second substrate.

  The last two steps constitute the connection step on the backside of the final device, which (in the multi-gate device) the connection between the source / gate / drain structures is achieved by an air bridge structure It is the main unique feature compared to technology. Preferably, a contact metal layer is fabricated on the contacts before attaching the first substrate to the second substrate.

  The method of the present invention is applicable to HEMT devices with a plurality of gates in the form of fingers (shortly, multiple fingers), which is a preferred embodiment and will be described in detail below. However, the present invention is applicable to any device in which there are multiple source-gate-drain structures, whether they are close together in a region of the substrate or located in separate regions of the substrate.

  The first substrate may be a sapphire, silicon, or glass substrate. It may also be a GaAs, Ge, InP, SiC, or AlN substrate. The second substrate is preferably a low cost substrate. The second substrate may be a glass, silicon, or polymer based substrate. According to a further embodiment, the second substrate may be a multi-chip-module insulating stack (MCM-D). The MCM-D stack can have passive components such as resistors or capacitors. The removal of the first substrate can be performed by wet etching, dry etching, laser ablation, or laser lift-off (or a combination of these techniques).

  The semiconductor layer can be made of a Group III nitride material. The group III nitride material is a material composed of a group III nitride of the periodic table. Group III nitride materials are known to those skilled in the art as wide band gap materials. The Group III nitride material may be GaN, where GaN is understood to be a material comprising at least GaN, such as, but not limited to, AlGaN, InGaN, AlInGaN, GaAsPN, and the like.

  Furthermore, the semiconductor layer may consist of a stack of layers, at least one of which consists of a group III nitride material. Furthermore, the devices listed in the present invention may have a diamond layer instead of a Group III nitride material.

  In other preferred embodiments, the source and drain contacts are made of an alloy comprising Ti, Al, Ni, Mo, Ta, Pt, Pd, Si, V, Nb, Zr, and / or Au. . The contacts are preferably formed of Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ti / Al / Mo / Au, or Ti / Al / Pt / Au.

  The adhesive layer is preferably manufactured from a thermally conductive adhesive material for the purpose of obtaining sufficient heat dissipation in the completed device. This adhesive material is composed of organic polymer, SU-8, polyimide, BCB, silicone, fluid oxide, and heat conductive epoxy such as epoxy with filler (floating particles to increase thermal conductivity). You can select from the group to be played. The thickness of this heat conductive adhesive layer is preferably between 500 nm and 10 μm, more preferably between 500 nm and 1 μm.

  According to a preferred embodiment, prior to attaching the first substrate to the second substrate, a layer having the combined function of passivation and thermal diffusion is applied to the gate / source / drain contacts on the first substrate. Can be deposited on top.

This passivation and thermal diffusion layer
-Protects the gate and exposed semiconductor surface and improves the electrical properties of the top surface,
-It has two functions of diffusing heat in order to minimize the thermal resistance of the adhesive layer.

  This passivation and thermal diffusion layer is a layer having a high thermal conductivity (greater than 150 W / mK). Therefore, in the attaching step, the heat diffusion layer is attached to the heat conductive adhesive layer. In this case, the heat conductive adhesive layer may be the same as the previous embodiment. However, since the thermal conductivity of the thermal diffusion layer is preferably better than a typical adhesive layer (<10 W / mK), application of the thermal diffusion layer further improves thermal performance. The passivation and thermal diffusion layer can be formed of AlN, AlSiC, high resistance Si, SiC, Si nitride, or diamond. Conveniently, a combination of two successive layers, a first layer as a passivation layer and a second layer as a thermal diffusion layer, can be used to provide optimum performance.

  A second passivation layer can be applied to the semiconductor layer after via etching and before backside connection.

  An advantage of the present invention is that the active side of the semiconductor device is protected and essentially unaffected. A further advantage is that the resulting structure is smaller compared to devices manufactured by applying an airborne bridge structure. Devices manufactured in accordance with the present invention are highly integrated, have short connections and flat features, allowing further 3D integration.

  In the second embodiment, the method has several further steps following each step of the first embodiment. After the connection between the source / gate / drain structures is established, the second substrate on which the now completed and connected device is mounted is inverted and the surface on which the connection layer of the second substrate is mounted Can be attached to a third substrate, preferably an MCM substrate, to attach the second substrate to the third substrate. The second substrate and the original adhesive layer can then be removed and a via can be etched to apply a heat sink that can better dissipate heat. This will be described in more detail with respect to multi-finger HEMT devices.

  According to the third embodiment, the first substrate is not attached to the second substrate. Vias are manufactured through the back side of the first substrate, e.g. exposing the source region. Perhaps a thinning operation can be applied to the substrate prior to via etching. After forming the via (in the manner of claim 1) and applying the contact layer, the first substrate is attached to the second substrate (equivalent to the third substrate of the previous embodiment) Also good.

In summary, the advantages of the present invention are as follows.
• An additional heat conduction path to the active device is created. This means that heat can be removed both in the vertical direction (eg towards the second substrate, which is the MCM) and in the horizontal direction (via metal contacts). Since the vertical distance between the device and the substrate is small, the thermal resistance of this conduction path is suppressed.
・ Aerial bridge on semiconductor substrate is not required.
• The electrical connection to the HEMT is very short. This means that there is less parasitism and as a result, improved RF behavior.
-The final structure is very flat. This facilitates further packaging and system integration.

Further, the advantages related to MCM are still effective.
MCM is more suitable for larger metal thickness (improves thermal conductivity)
The device can be inspected before MCM integration.
MCM adds functionality to the device by integrating several active components that may be derived from passive elements or various techniques.
-Substrate cost is lower than MMIC.

  A preferred embodiment of the present invention relates to the manufacture of a multi-finger HEMT device by a method having the features described above. FIG. 1 shows the various steps of the HEMT manufacturing process according to the first embodiment of the invention. In the following, these steps will be described in more detail.

  1a: A sapphire substrate 1 having a semiconductor stack on its upper surface is prepared. This stack is composed of a GaN layer 2 and an AlGaN layer 3. The GaN film has a thickness of 1 to 5 μm and is grown on the sapphire substrate by MOCVD (metal organic chemical vapor deposition). The upper layer 3 made of an AlGaN (15 to 30 nm) film is grown on the upper surface (two-dimensional electron gas, 2-DEG) so that a high concentration of electrons is generated at the interface.

  FIG. 1b: Mesa etching is performed to make individual devices independent on the substrate. This etch must pass through the 2-DEG interface 4.

  FIG. 1c: Metal stack 5 is deposited for drain and source contacts. Source and drain contacts are deposited together. A typical stack is Ti / Al / x / Au (x = Mo, Pt, Ti,...) And the thicknesses are 20/40/25/50 nm, respectively. The thickness of each layer is optimized according to the GaN / AlGaN layer. Annealing at high temperatures is performed (at 800-1000 ° C.) to promote alloy formation to make the contact properties ohmic.

  FIG. 1d: The gate contact 6 is manufactured in an e-beam process. The material used for the gate may be Ni / Au or Pt / Au (20/200 nm).

  FIG. 1e: Optionally, a contact metal layer 7 is applied (eg TiW / Au / TiW).

FIG. 1f: a passivation layer is deposited over the device (100 nm Si ₃ N ₄ , not visible in the figure) and a thermal diffusion layer 8 is deposited over the passivation layer (eg 0.5 ˜1 μm AlN). After this step, the substrate 1 is preferably chopped small to form individual devices.

  FIG. 1 g: A second substrate 9 is prepared, and a heat conductive adhesive layer 10 is provided on the second substrate. Passive components may be present on the second substrate. The HEMT device and the first substrate are inverted and bonded to the adhesive layer so that the thermal diffusion layer 8 is in direct contact with the adhesive layer 10. The adhesive used may be BCB or SU-8.

  FIG. 1h: The first substrate is removed, possibly using laser lift-off. A laser pulse having an energy higher than the band gap of GaN is applied to the sapphire substrate. The pulse is absorbed at the GaN / sapphire interface, resulting in local decomposition into Ga and N2. Ga has a very low melting point, which means that the substrate can be removed at low temperatures. The remaining Ga can be removed by a short immersion in HCl.

  FIG. 1 i: Around the HEMT device, the adhesion layer is removed using SF6 / O2 etching. A via 11 is provided in the GaN / AlGaN active layer using Cl2 etching.

  In the illustration of FIG. 1i, these vias have been etched to expose the source, drain, and gate contacts to the outside world (ie, leave the contacts uncovered), so that These source contacts can be contacted directly in process steps.

  In the cross section i of FIG. 1, vias are shown only for the source contacts. However, it is necessary to contact the gate and drain as well. FIG. 3 shows a top view of the HEMT device of FIG. 1, including the locations where the mesas 40 and vias 11 are generated. While direct contact is made to the source contact region 29, the drain and gate regions are connected to the side contact regions 30 and 31 and contacted through a single via 52 to each of the contact regions 30 and 31. It is manufactured to be taken. However, it should be noted that the present invention is not limited to direct contact to the source contact (ie, as shown in FIG. 3). The same is true for the gate or drain contact, in which case the remaining two contacts can be contacted through a lateral region in the plane of the device. As a further alternative, all contact areas may be contacted directly, i.e. without side contact areas.

  FIG. 1 j: Optionally, for example, a passivation layer 12 of Si nitride is deposited on the back side. This layer protects the backside of the GaN and may affect the electronic properties of the HEMT.

  In FIG. 1 k: a contact layer 13 to the gate / source / drain contacts is deposited, for example using Cu electroplating.

  These steps result in a multi-finger HEMT device manufactured according to the first embodiment.

  As already mentioned, the present invention is characterized in that the via 11 is manufactured in direct contact with at least one of the device's ohmic contacts. In FIGS. 4a and 4b, several options are shown for a 6-gate HEMT case. The so-called “ohmic contacts” of the source (29) and drain (50) are shown in outline. The gate contact 51 can also be seen. In FIG. 4a, the via 11 is etched directly on the source contact 29, exposing these contacts so that they can be connected by the connection layer 13 (FIG. 1). There are no vias fabricated directly above the drain and gate contacts. Instead, these contacts are contacted through side regions 30 and 31 (also referred to as contact pads), and one via 52 is fabricated in each of the side regions 30 and 31. Yes. In the device of FIG. 4a, contact pads 53 for the two outer source regions are also shown. Additional vias 54 can be provided on these outer contact pads. However, the latter is not essential for the present invention.

  In the embodiment of FIG. 4 b, the via 11 is manufactured so as to be in direct contact with all the source and drain regions 29 and 50. A contact pad 30 for the drain still exists, but may be omitted in this embodiment. As an alternative, the via 11 may be provided so as to be in direct contact with all kinds of contacts (source, drain, and gate). In this case, it may be necessary to manufacture the gate with a larger width.

  In the embodiment shown in FIGS. 3 and 4, the source layer 29 can be connected to each other by the connection layer 13 having an appropriate pattern, and the drain and gate regions 50 and 51 can be connected to each other. It is clear that the contacts (eg all drains) need not be connected by an air bridge. Airborne bridges are necessary if all types of ohmic contacts are contacted via the side contact pads, as in US Pat. No. 6,214,639. This represents an improvement achieved by the present invention over the prior art.

  According to the second embodiment, some additional steps are performed as shown in FIG.

  FIG. 2 a: The same steps as already described are applied to obtain gate source and drain contact regions 5 and 6 on the substrate 1. A passivation layer 20 is deposited on the contacts 5 and 6, and an etch stop layer 21 is provided on the passivation layer.

  FIG. 2b: The substrate 1 is inverted and bonded to the second substrate 9, after which the first substrate 1 is removed in the same way as in the first embodiment. The bonding layer 10 according to this embodiment is not necessarily a heat conductive adhesive layer. The bonding layer 10 may be SU8 / BCB or metal.

  FIG. 2c: Via 11 is etched into the contact area. In principle, only vias to the source contacts are sufficient in this case, but this has the disadvantage that the device cannot be measured until it is bonded to the third substrate. Therefore, in the preferred case of this embodiment, vias are manufactured to all contact regions (source, drain, gate) as shown in FIG.

  FIG. 2 d: Connection is established by the back contact layer 13. Thus, the device shown in FIG. 2d is different from the first embodiment in that there are thermal and electrical side contacts between the back contact layer 13 and the second substrate 9, This corresponds to the completed device of the first embodiment shown in FIG. 1k. This contact does not exist in the second embodiment because the second substrate is removed anyway (see later).

  FIG. 2e: According to the second embodiment, third substrates 22a, 22b, preferably MCM substrates (eg AlN substrates) having good thermal conductivity, are provided here. The lower layer 22a is a substrate, and the upper layer 22b is a metal layer patterned to contact the source. A bonding layer 23 is provided on the third substrate. Here, the second substrate is inverted and attached to the third substrate by attaching the side holding the connection layer 13 to the third substrate by the bonding layer 23. The bonding layer 23 is preferably a layer having good thermal conductivity. The bonding layer 23 may be a metal bonding layer.

  FIG. 2f: Subsequently, the second substrate 9 and the adhesive layer 10 are removed. This can be done by an etching step that is stopped by the etch stop layer 21. However, the second substrate may be removed in other ways that may not require an etch stop layer.

  FIG. 2g: The etch stop layer is removed and vias can be etched into the passivation layer 20 on the gate / source / drain contacts (5, 6), and a heat sink 24 can be deposited over the contacts.

  Preferably, according to the second embodiment, the first substrate 1 is not cut into small corners until it is inverted and attached to the second substrate. Instead, the first substrate is inverted and attached as a whole, and possibly several HEMT devices are attached to the second substrate. The cutting is preferably performed after the first substrate is inverted and attached to the second substrate. The individual devices are then inverted and attached to a third substrate, as shown in FIG. 2e.

  The second embodiment of the method of the present invention provides several additional advantages over the prior art. Heat removal can be obtained at both the front and back of the device. On the back side, heat can be removed to the third substrate 22 via the adhesive layer 23 and the connecting layer 13, while on the front side, a heat sink can be manufactured to further improve the efficiency of heat removal. With the device produced according to the second embodiment, the entire device (with source contacts) can be inspected before integrating the HEMT into the circuit on the third substrate.

  In the second embodiment, vias can be manufactured into the ohmic region in the manner shown in FIGS. 5a and 5b, ie without manufacturing vias 52 to the side contact pads 30 and 31. It is. This is because after the device has been attached to the third substrate, these areas can be contacted in a known manner without the use of an air bridge.

  According to the third embodiment, the via is etched through the back surface of the first substrate itself without inverting the first substrate onto the second substrate. See FIG. This is only possible for the first substrate 1 made of a specific material, preferably Si. On this Si, as in the previous embodiment, there are further semiconductor layers (2, 3), for example GaN / AlGaN. Layer 2 + 3 is shown as a single layer in FIG. 6, but is preferably a bilayer similar to FIG. As seen in FIG. 6A, the device, including all the gate / drain / source contacts 7 and the passivation layer 8, is formed on the first substrate in the same manner as previously described with respect to the first embodiment. Manufactured. Vias 60 are etched through the passivation layer 8 to contact the lateral contact pads. See FIG. 6B.

  In this embodiment, the via 11 is manufactured through the Si substrate 1 and the semiconductor layers 2 and 3 (see C in FIG. 6). Perhaps the backside of the substrate can be thinned prior to via fabrication. This is the case of the illustrated embodiment, and the thickness of the substrate 1 decreases between B and C in FIG. This thinning can be performed by etching the substrate from behind, or by grinding and / or polishing the substrate from the back. A connection layer 13 is applied to the back side of the substrate, resulting in a completed device. See FIG.

  As already mentioned, the connection layer 13 is patterned in a suitable manner so that the ohmic contacts can be correctly connected. FIG. 7 shows some examples of how this patterning can be performed for the 6-gate HEMT case shown in FIG.

  FIGS. 7A and 7B show two possibilities that can be used in the device according to the first embodiment. Connection layer 13 presents three distinct regions, thus allowing common contact to the gate, drain, and source, respectively.

  C and D of FIG. 7 show one or two separate regions for the connection layer 13. This design can only be used in embodiment 2 since one or two additional contact layers need to be applied to the front side of the device after the device is attached to the third substrate (FIG. 2). ).

a to k show the steps of the method according to the first embodiment of the invention for producing a multi-finger HEMT. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. Fig. 4 shows a step of a method according to a second embodiment. FIG. 2 shows a top view of a HEMT device and describes the shape of the contact region in a preferred embodiment of the device. Fig. 6 illustrates one of the design options for a 6-gate HEMT according to the present invention. Fig. 4 shows another option for designing a 6-gate HEMT according to the present invention. Fig. 4 shows one further option for the design of a 6-gate HEMT according to the invention. Fig. 4 shows another one of the further options for the design of a 6-gate HEMT according to the present invention. A to D1 are diagrams illustrating an example in the case where the via is etched through the back surface of the first substrate itself in the third embodiment. AD is a figure which shows the example of patterning of a connection layer.

Claims (24)

A plurality of groups consisting of source, drain and gate contacts, or groups consisting of emitter, base and collector contacts, each type of contact of said group having a common gate, drain and A method for manufacturing a semiconductor device connected to a source (or base, collector, emitter) contact comprising:
Having a semiconductor layer (2, 3) on the front side, on which a plurality of gate contacts (6) are respectively located between the source and drain ohmic contacts (5) Providing a first substrate (1), wherein a plurality of base contacts (6) are respectively located between the emitter and collector ohmic contacts (5);
Etching vias (11) through the backside of the semiconductor layer to produce vias directly on each of the at least one contact, for example on all source ohmic contacts; Exposing the contact;
Manufacturing a contact contact layer (13) on the back side of the semiconductor layer to provide a connection between the source-gate-drain group or the emitter-base-collector group, thereby on a second substrate; Providing a semiconductor device.   Method according to claim 1, wherein vias are produced over all of one type of contact and other contacts are connected to the lateral regions (30, 31).   The method of claim 2, wherein a via is fabricated over the lateral region and through the back surface of the semiconductor layer.   4. A method according to claim 1, 2 or 3, wherein vias are fabricated directly on all source contacts and vias are fabricated directly on all drain contacts. A plurality of gate contacts (6) each having a semiconductor layer (2, 3) on the front surface, each positioned between source and drain contacts (5), each of which is an emitter And providing a first substrate (1) having a plurality of base contacts (6) located between the collector contacts (5);
-Preparing a second substrate (9) provided with an adhesive layer (10);
By attaching the front surface of the first substrate containing the gate / source / drain or base / emitter / collector contacts to the adhesive layer (10) of the second substrate (9); Attaching the substrate to the second substrate;
After the step of attaching the first substrate and before the step of manufacturing the via (11), the first substrate (1) is removed from the semiconductor layer (2, 3), and the semiconductor layer ( Exposing the back of (2, 3);
After the step of manufacturing the via (11), a connection contact layer (13) is manufactured on the backside of the semiconductor layer, between the source-gate-drain group or the emitter-base-collector group. Providing a connection, thereby providing a semiconductor device on the second substrate.   The adhesive layer (10) was selected from the group consisting of organic polymers, thermally conductive epoxies (eg, filled epoxy), SU-8, polyimide, BCB, silicone, and flowable oxides. The method according to claim 5, comprising a heat conductive adhesive layer material. The method according to claim 5 or 6, further comprising applying a contact metal layer (7) to the contacts (5, 6) prior to attaching the first substrate to the second substrate. . Applying a passivation and thermal diffusion layer (8) to the contacts (5, 6) or the contact metal layer (7) before attaching the first substrate to the second substrate. A method according to any one of claims 5 to 7.   9. The method of claim 8, wherein the passivation and thermal diffusion layer is composed of AlN, AlSiC, high resistance Si, SiC, or Si nitride.   The method according to claim 5, wherein a passivation layer is applied to the contact, and a thermal diffusion layer is applied to the passivation layer. After the step of manufacturing the via (11) in the semiconductor layer and before the step of manufacturing the connection contact layer (13), a passivation layer (12) is applied to the back surface of the semiconductor layer (2, 3). The method according to any one of claims 5 to 10, further comprising a step.   The method according to claim 5, wherein the semiconductor device is a HEMT including a plurality of gates in a finger shape.   12. A method according to any one of claims 5 to 11 wherein the semiconductor device is a multi-base bipolar transistor. Providing a third substrate (22) provided with a bonding layer (23);
Attaching the second substrate (9) to the third substrate by attaching the side of the second substrate containing the semiconductor device to the bonding layer (23) on the third substrate; And mounting step,
-Removing the second substrate (9) and the adhesive layer (10) and providing a semiconductor device on the third substrate. Method.   Prior to attaching the first substrate (1) to the second substrate (9), a passivation layer (20) over the gate / source / drain (or base / emitter / collector) contacts (5, 6). ) And an etch stop layer (21) are produced, and the second substrate (9) and the adhesive layer (10) are removed by an etching process stopped by the etch stop layer (21). the method of. 12. The method of claim 14 or 11, further comprising fabricating a heat sink (24) over the source, gate, and drain (or emitter, base, collector) contacts after removing the second substrate. The method described.   17. A method as claimed in any one of claims 14 to 16, wherein the via is manufactured to contact only one type of contact (e.g. source, drain or gate).   14. The first substrate in the form of a plurality of individual devices is cut into small pieces to form individual devices before being attached to the second substrate. the method of.   18. The second substrate in the form of a plurality of individual devices is cut into small pieces to form individual devices before being attached to the third substrate. the method of.   The method according to any one of claims 1 to 19, wherein the semiconductor layer comprises a stack of a GaN layer and an AlGaN layer.   The via (11) is manufactured through the first substrate, and after manufacturing the via (11), the connection layer (13) is manufactured on the back of the first substrate. 5. The method according to any one of items 1 to 4.   The method according to claim 21, wherein a thinning operation is applied to the first substrate prior to the manufacture of the via (11).   23. A method according to claim 21 or 22, wherein the device is attached to a second substrate by attaching the back side of the first substrate containing the connection layer (13) to another substrate. A semiconductor device manufactured according to the method of any one of claims 1 to 23.