JP2023089810A - Semiconductor device, method of manufacturing semiconductor device, and electronic equipment - Google Patents

Abstract

To achieve a high-quality semiconductor device including a diamond layer.SOLUTION: A semiconductor device 1 includes: a semiconductor layer 10; a diamond layer 20 provided in an inner region AR2 provided inside an outer peripheral region AR1 on a principal surface 10a of the semiconductor layer; and a protection film 140 provided in the outer peripheral region AR1. A via hole 80 extending into a semiconductor layer 10 while penetrating through the diamond layer 20 in the inner region AR2 is provided, and a via wire 90 is provided in the via hole 80. The semiconductor device 1 is obtained by dicing at a position on a lateral face 10b of the semiconductor layer 10. Since the diamond layer 20 does not exist at the position, a blade is used for dicing. In the semiconductor device 1, generation of dust of the via wire 90 at the dicing using the blade is suppressed, and thereby, short circuit caused by the dust of the via wire 90 can be suppressed. A high-quality semiconductor device 1 can be obtained at a high yield.SELECTED DRAWING: Figure 8

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

A gallium nitride (GaN)-based high electron mobility transistor (HEMT) is provided with a nucleation layer on the lower surface of the active layer, the upper surface of which is provided with a metal contact, and chemical vapor deposition (CVD). ) method is known to provide a diamond layer. Further known in the art is the provision of vias extending part way into the active layer from the back contact metal provided on the back side of the diamond layer, or vias extending from the back contact metal to metal contacts on the top surface of the active layer.

U.S. Patent Application Publication No. 2014/0141595

As for semiconductor devices, a technique of bonding a highly thermally conductive diamond layer as a heat spreader to a semiconductor layer that generates heat during operation, and a technique of providing a via wiring extending through the diamond layer and extending into the semiconductor layer are known.

By the way, in the manufacture of such a semiconductor device using a diamond layer, it is conceivable to separate the semiconductor layers of a plurality of semiconductor devices formed in a wafer state together with the diamond layer into individual pieces. One of the common singulation methods is dicing using a blade, but it is difficult to employ a diamond layer in a semiconductor device using a diamond layer because the diamond layer is hard. As another method of singulation, there is also a method of dicing using a laser. However, with this method, there is a risk that the semiconductor device will be damaged by the heat generated during laser irradiation, or that dust generated by laser ablation will cause a short circuit.

As yet another method of singulation, via holes for via wiring that penetrates the diamond layer and the semiconductor layer are formed, and at the same time, the diamond layer and the semiconductor layer in the regions corresponding to the dicing lines are removed by etching to form trenches. , a method of dicing is also conceivable. However, in this method, when the via wiring is formed, the metal material of the via wiring, which is formed in the trench as well as in the via hole, may generate dust during dicing and cause a short circuit.

SUMMARY OF THE INVENTION In one aspect, the present invention aims to provide a high quality semiconductor device including a diamond layer.

In one aspect, a semiconductor layer, a diamond layer provided in an inner region inside an outer peripheral region on the main surface of the semiconductor layer, a protective film provided in the outer peripheral region on the main surface of the semiconductor layer, A semiconductor device is provided that includes a via hole that penetrates a diamond layer and extends into the semiconductor layer, and a via wiring that is provided in the via hole.

In one aspect, the step of forming a diamond layer on the main surface of a semiconductor layer, the diamond layer in a first region corresponding to a dicing line for dividing the semiconductor layer into individual pieces, and the individual pieces to be divided. etching the diamond layer in a second region corresponding to a first via hole formed in the semiconductor layer to form a trench penetrating the diamond layer in the first region and the diamond layer in the second region; forming a second via hole penetrating through the trench; forming a protective film covering the main surface of the semiconductor layer in the trench; and using the protective film as a mask, the semiconductor layer in the second via hole to form the first via hole communicating with the second via hole and extending into the semiconductor layer; forming via wiring in the communicating first via hole and the second via hole; A method of manufacturing a semiconductor device is provided, including a step of dicing the semiconductor layer and the protective film covering the main surface in the trench at the position of the formed first region.

In one aspect, an electronic device including the semiconductor device as described above is provided.

In one aspect, it enables the realization of high quality semiconductor devices containing diamond layers.

It is a figure explaining the example of a semiconductor device. FIG. 2 is a diagram (part 1) illustrating an example of a method for manufacturing a semiconductor device; FIG. 12 is a diagram (part 2) illustrating an example of a method for manufacturing a semiconductor device; FIG. 3 is a diagram (part 3) illustrating an example of a method for manufacturing a semiconductor device; FIG. 10 is a diagram (part 4) for explaining an example of a method for manufacturing a semiconductor device; FIG. 15 is a diagram (No. 5) explaining an example of a method for manufacturing a semiconductor device; FIG. 10 is a diagram (part 6) for explaining an example of a method for manufacturing a semiconductor device; 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; FIG. FIG. 3 is a diagram (part 1) explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 2 is a diagram (part 2) illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a diagram (part 3) explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram (part 4) explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 5) explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a diagram (part 6) explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; It is a figure explaining an example of the semiconductor package concerning a 2nd embodiment. FIG. 11 is a diagram illustrating an example of a power factor correction circuit according to a third embodiment; FIG. It is a figure explaining an example of the power supply device which concerns on 4th Embodiment. It is a figure explaining an example of the amplifier based on 5th Embodiment.

First, an example of a semiconductor device will be described.
FIG. 1 is a diagram illustrating an example of a semiconductor device. FIG. 1A schematically shows a fragmentary cross-sectional view of a first example of a semiconductor device. FIG. 1B schematically shows a fragmentary cross-sectional view of a second example of a semiconductor device.

A semiconductor device 1A shown in FIG. 1A is an example of a semiconductor device including a HEMT. A semiconductor device 1</b>A has a semiconductor layer 10 including a laminated structure of a first semiconductor layer 11 and a second semiconductor layer 12 . For example, SiC (silicon carbide) is used for the first semiconductor layer 11 , and nitride semiconductor such as GaN and AlGaN (aluminum gallium nitride) is used for the second semiconductor layer 12 . The second semiconductor layer 12 is provided with a gate electrode 30, a source electrode 40, and a drain electrode 50. As an example of a transistor, electrons of two dimensional electron gas (2DEG) are used as carriers for the source electrode 40 and the drain electrode. A HEMT that forms a current path with the electrode 50 is formed. The second semiconductor layer 12 is further provided with an etching stopper 60 connected to the source electrode 40 through the wiring 70 . A metal material, for example, is used for the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70. FIG. For the wiring 70, metal wires or the like are used in addition to a metal layer formed on an insulating film (not shown).

The semiconductor device 1A is provided with a via hole 80 that penetrates the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 12) and reaches the etching stopper 60. As shown in FIG. The etching stopper 60 has a function of stopping etching from the main surface 10a side of the semiconductor layer 10 using the mask layer 120 as a mask when forming the via hole 80 by etching. It has a function as an electrode layer. A via wiring 90 is provided in the via hole 80 . Via wiring 90 extends from inside via hole 80 to main surface 10 a of semiconductor layer 10 . A metal material, for example, is used for the via wiring 90 .

In semiconductor device 1A, via wiring 90 is set to a ground (GND) potential. The source electrode 40 is GND-connected through the wiring 70 , the etching stopper 60 and the via wiring 90 . A structure in which the source electrode 40 is connected to the GND through the via wiring 90 is one of the structures capable of reducing the source inductance, and is advantageous in terms of characteristics.

By the way, a semiconductor device generates heat during operation, and the heat may deteriorate the characteristics of a transistor. Until now, various heat dissipation techniques have been proposed for suppressing the influence of such heat and operating transistors. As one of heat dissipation techniques, a technique using a diamond layer with high thermal conductivity as a heat spreader is known.

A semiconductor device 1B shown in FIG. 1B is an example of a semiconductor device using a diamond layer 20 as a heat spreader.
For example, in the semiconductor device 1B, the semiconductor layer 10 (the first semiconductor layer 11 thereof) is thinned, and the diamond layer 20 is bonded to the main surface 10a of the thinned semiconductor layer 10 . When the semiconductor layer 10 is thinned, the thermal resistance between the transistor that generates heat during operation and the diamond layer 20 is reduced, which is advantageous for heat dissipation. Here, if the thermal resistance of the bonding interface between the semiconductor layer 10 and the diamond layer 20 is high, the efficiency of heat conduction from the semiconductor layer 10 to the diamond layer 20 is lowered, and the effect of using the diamond layer 20 as a heat spreader is weakened. Therefore, the bonding between the semiconductor layer 10 and the diamond layer 20 employs a method such as surface activation bonding or atomic diffusion bonding that relatively reduces the interfacial thermal resistance.

In the semiconductor device 1B, a via hole 80 which is formed by etching using the mask layer 120 as a mask, penetrates the diamond layer 20 and the semiconductor layer 10 and reaches the etching stopper 60 is provided. A via wiring 90 is provided in the via hole 80 . Via wiring 90 extends from inside via hole 80 to main surface 20 a of diamond layer 20 on the opposite side of semiconductor layer 10 .

The semiconductor device 1B shown in FIG. 1B differs from the semiconductor device 1A shown in FIG. 1A in that it has such a configuration.
In the semiconductor device 1B, the diamond layer 20 with high thermal conductivity bonded to the semiconductor layer 10 functions as a heat spreader. As a result, the heat dissipation of the transistor that is formed in the semiconductor layer 10 and generates heat during operation is enhanced, and the deterioration of its characteristics due to heat is suppressed.

By the way, in manufacturing the semiconductor device 1B using the diamond layer 20 as described above, the semiconductor layer 10 and the diamond layer 20 joined to the semiconductor layer 10 of the plurality of semiconductor devices 1B formed in a wafer state are integrally divided. It is conceivable to separate them into individual pieces.

As one of the general singulation techniques, there is a technique of dicing using a blade, but in the semiconductor device 1B in which the diamond layer 20 is used, the diamond layer 20 is hard and difficult to employ. As another method of singulation, there is also a method of dicing using a laser. However, in this method, there is a risk that the semiconductor device 1B may be damaged by heat during laser irradiation, or a short circuit may occur due to dust generated by laser ablation.

As still another method of singulation, the following method is also conceivable. That is, simultaneously with the formation of the via hole 80 for the via wiring 90 penetrating the diamond layer 20 and the semiconductor layer 10, the diamond layer 20 and the semiconductor layer 10 in the region corresponding to the dicing line are removed by etching to form a trench, It is a method of dicing. Such a method will be described with reference to FIGS. 2 to 7. FIG.

2 to 7 are diagrams for explaining an example of a method for manufacturing a semiconductor device. 2 to 7 schematically show cross-sectional views of essential parts of each step of an example of a method of manufacturing a semiconductor device. Each step will be described below in order.

FIG. 2 is a diagram showing an example of a process of attaching a support to a laminate and forming a mask layer. FIG. 2A schematically shows a plan view of the relevant part of the process. FIG. 2B schematically shows a cross-sectional view of the relevant part of the process. 2(A) is a schematic plan view of the laminate 2 shown in FIG. 2(B) as viewed from the diamond layer 20 side. FIG. 2(B) is a schematic sectional view taken along line II--II in FIG. 2(A).

2A and 2B, that is, the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 10) provided with the gate electrode 30, the source electrode 40, the drain electrode 50, and the like. A laminate 2 is provided comprising a layer 12) and a diamond layer 20 bonded to the semiconductor layer 10 . The laminate 2 includes semiconductor layers 10 and diamond layers 20 of a plurality of semiconductor devices formed in a wafer state. 2(A) and 2(B) (and FIGS. 3(A) and 3(B), FIGS. 4(A) and 4(B), FIGS. 5(A) and 5(B), FIG. 6(A) and 6(B), and FIGS. 7(A) and 7(B)) show a part of such a wafer-state laminate 2. As shown in FIG.

For example, the semiconductor layer 10 is formed by stacking a second semiconductor layer 12 including a channel layer such as GaN and a barrier layer such as AlGaN on a first semiconductor layer 11 as an underlying layer such as SiC. A gate electrode 30 , a source electrode 40 , a drain electrode 50 , an etching stopper 60 and a wiring 70 are formed at predetermined positions of the second semiconductor layer 12 in the semiconductor layer 10 . Thereby, a structure having a HEMT in which a current path is formed in the second semiconductor layer 12 of the semiconductor layer 10 is formed. A diamond layer 20 is bonded to the first semiconductor layer 11 side main surface 10a of the semiconductor layer 10 in the formed structure by a method such as surface activation bonding or atomic diffusion bonding. For example, such a method is used to obtain a laminate 2 having a laminate structure as shown in FIG. 2(B).

As shown in FIG. 2B, a support 110 is attached using an adhesive 100 to the main surface of the laminate 2 obtained, on which the gate electrode 30, the source electrode 40, the drain electrode 50, and the like are provided. be. A mask layer 120 having an opening 121 in a predetermined region is formed on the main surface 20a of the diamond layer 20 of the laminate 2 that is bonded to the semiconductor layer 10 . The openings 121 of the mask layer 120 are provided in the dicing line region 2a (first region) and via formation region 2b (second region) of the laminate 2 . The dicing line region 2a is a region corresponding to a dicing line for dividing the laminate 2 into individual semiconductor devices (the semiconductor layers 10 thereof) by dicing. The via forming region 2b is a region corresponding to a via formed in each piece of semiconductor device (the semiconductor layer 10 thereof) divided by dicing the stacked body 2 .

The mask layer 120 is formed by dry etching the diamond layer 20 using an oxygen-containing gas (O-based gas) and a fluorine-containing gas (F-based gas) or a chlorine-containing gas (Cl-based gas). A material is used that is resistant to dry etching of the semiconductor layer 10 using . For example, the mask layer 120 is made of an insulating material such as SiO ₂ (silicon oxide) or a metal material such as Ni (nickel) or Al (aluminum). When an insulating material such as SiO ₂ is used for the mask layer 120, its thickness is set to 10 μm or more, for example. When a metal material such as Ni or Al is used for the mask layer 120, its thickness is set, for example, on the order of several μm.

FIG. 3 is a diagram showing an example of the diamond layer etching process. FIG. 3A schematically shows a plan view of the relevant part of the process. FIG. 3B schematically shows a cross-sectional view of a main part of the process. 3(A) is a schematic plan view of the laminate 2 shown in FIG. 3(B) as viewed from the diamond layer 20 side. FIG. 3(B) is a schematic sectional view taken along line III--III in FIG. 3(A).

After preparing the laminate 2 in which the support 110 is attached to the semiconductor layer 10 side using the adhesive 100 and the mask layer 120 is formed on the diamond layer 20 side, the diamond layer 20 is dry-etched using the mask layer 120 as a mask. is done. An O-based gas is used for the dry etching of the diamond layer 20 . By dry etching using the mask layer 120 as a mask, the diamond layer 20 in the dicing line region 2a and the via forming region 2b of the laminate 2 is removed as shown in FIGS. 3A and 3B. The semiconductor layer 10 (the first semiconductor layer 11 thereof) functions as an etching stopper during dry etching of the diamond layer 20 .

By dry-etching the diamond layer 20 using the mask layer 120, the dicing line region 2a of the laminate 2 has the semiconductor layer 10 extending through the diamond layer 20 as shown in FIGS. 3(A) and 3(B). A trench 21 is formed that reaches the . By dry etching the diamond layer 20 using the mask layer 120, the semiconductor layer 10 penetrates the diamond layer 20 and is formed in the via forming region 2b of the laminate 2 as shown in FIGS. 3(A) and 3(B). A via hole 22 reaching to is formed.

The trenches 21 are formed so as to surround each diamond layer 20 (or to separate each diamond layer 20) of the plurality of semiconductor devices included in the laminate 2. As shown in FIG. The via holes 22 are formed in the diamond layers 20 of each semiconductor device included in the laminate 2 .

FIG. 4 is a diagram showing an example of the semiconductor layer etching process. FIG. 4A schematically shows a plan view of the relevant part of the process. FIG. 4B schematically shows a cross-sectional view of a main part of the process. 4(A) is a schematic plan view of the laminate 2 shown in FIG. 4(B) as viewed from the diamond layer 20 side. FIG. 4(B) is a schematic cross-sectional view taken along line IV--IV of FIG. 4(A).

After forming the trenches 21 and the via holes 22 by dry etching the diamond layer 20, the semiconductor layer 10 in the trenches 21 and the via holes 22 is dry-etched using the mask layer 120 as a mask. For the dry etching of the semiconductor layer 10, an F-based gas or an F-based gas and a Cl-based gas is used. For example, an F-based gas is used to dry-etch both the first semiconductor layer 11 of SiC and the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN in the semiconductor layer 10 . Alternatively, an F-based gas is used to dry-etch the first semiconductor layer 11 of SiC in the semiconductor layer 10, and a Cl-based gas is used to dry-etch the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN. be.

By dry etching the semiconductor layer 10 using the mask layer 120 as a mask, the dicing line region 2a of the laminate 2 communicates with the trench 21 of the diamond layer 20 as shown in FIGS. 4(A) and 4(B). A trench 13 penetrating through the semiconductor layer 10 is formed. As a result, a trench 81 extending through the diamond layer 20 and the semiconductor layer 10 and reaching the adhesive 100 is formed in the dicing line region 2 a of the laminate 2 . By dry etching the semiconductor layer 10 using the mask layer 120 as a mask, the via forming region 2b of the laminate 2 communicates with the via hole 22 of the diamond layer 20, as shown in FIGS. 4(A) and 4(B). Then, a via hole 14 penetrating the semiconductor layer 10 is formed. As a result, a via hole 80 extending through the diamond layer 20 and the semiconductor layer 10 and reaching the etching stopper 60 is formed in the via forming region 2 b of the laminate 2 .

For the formation of the trenches 13 and the via holes 14 in the semiconductor layer 10, wet etching can be used in addition to dry etching. In this case, a material having resistance to wet etching is used for the mask layer 120 .

The trenches 81 are formed so as to surround the diamond layers 20 and the semiconductor layers 10 of the plurality of semiconductor devices included in the laminate 2 (or to separate the diamond layers 20 and the semiconductor layers 10 from each other). be. The via holes 80 are formed in the diamond layer 20 and the semiconductor layer 10 of each semiconductor device included in the laminate 2 .

FIG. 5 is a diagram showing an example of a via wiring forming process. FIG. 5A schematically shows a plan view of the relevant part of the process. FIG. 5B schematically shows a cross-sectional view of a main part of the process. 5(A) is a schematic plan view of the laminate 2 shown in FIG. 5(B) as viewed from the diamond layer 20 side. FIG. 5(B) is a schematic cross-sectional view taken along line VV of FIG. 5(A).

After forming trenches 81 penetrating the diamond layer 20 and the semiconductor layer 10 in the dicing line region 2a and via holes 80 penetrating the diamond layer 20 and the semiconductor layer 10 in the via formation region 2b of the laminate 2, FIG. And as shown in FIG. 5B, via wiring 90 is formed. For example, a layered structure of Ti (titanium) and Au (gold) is formed as a seed layer in the trench 81 and the via hole 80 of the layered body 2 and on the mask layer 120 by sputtering, and is used as the power supply layer. A via wiring 90 is formed by electrolytic plating of Au.

The via wiring 90 is formed continuously from above the mask layer 120 in the via hole 80 provided to penetrate the diamond layer 20 and the semiconductor layer 10 and is connected to the etching stopper 60 at the bottom of the via hole 80 . In addition to being formed in the via hole 80 as described above, the via wiring 90 is also formed continuously from above the mask layer 120 in the trench 81 provided to penetrate the diamond layer 20 and the semiconductor layer 10 . A via wiring 90 formed in the trench 81 is provided on the adhesive 100 at the bottom of the trench 81 .

FIG. 6 is a diagram showing an example of the support separation process. FIG. 6A schematically shows a plan view of the relevant part of the process. FIG. 6B schematically shows a cross-sectional view of the relevant part of the process. 6(A) is a schematic plan view of the laminate 2 shown in FIG. 6(B) as viewed from the diamond layer 20 side. FIG. 6(B) is a schematic cross-sectional view taken along line VI-VI of FIG. 6(A).

After the via wiring 90 is formed, the support 110 is peeled off together with the adhesive 100 from the laminate 2 to be separated, as shown in FIGS. 6(A) and 6(B). After separating the support 110 and the adhesive 100, the laminated body 2 is formed with the via wiring 90 exposed in the region of the trench 81, that is, the dicing line region 2a, as shown in the P1 portion of FIG. 6B. existing structure.

FIG. 7 is a diagram showing an example of the dicing process. FIG. 7A schematically shows a plan view of the relevant part of the process. FIG. 7B schematically shows a cross-sectional view of the relevant part of the process. 7(A) is a schematic plan view of the laminate 2 shown in FIG. 7(B) as viewed from the diamond layer 20 side. Illustration of the dicing tape 150 shown in FIG. 7(B) is omitted in FIG. 7(A). FIG. 7(B) is a schematic cross-sectional view taken along line VII--VII of FIG. 7(A).

After the support 110 and the adhesive 100 are separated, the laminate 2 is adhered to the dicing tape 150 on the diamond layer 20 side, as shown in FIGS. 7(A) and 7(B). It is diced and divided into individual pieces. Individual pieces divided by dicing are obtained as semiconductor devices 1Ba.

Here, for dicing the laminate 2, for example, a method of dicing using a blade 130 as shown in FIG. 7B can be used. In the laminated body 2, the element existing in the dicing line region 2a is the via wiring 90, and the diamond layer 20 does not exist. can do.

If the diamond layer 20 exists in the dicing line region 2a, the diamond layer 20 is hard and dicing with the blade 130 is difficult. Dicing by 130 is possible. Moreover, by not using a laser for dicing, damage to the semiconductor device 1Ba due to heat during laser irradiation and short-circuit caused by dust generated by laser ablation can be suppressed. Restrictions on the structure and manufacturing process of the semiconductor device 1Ba due to the laser transmittance in the cut portion can also be suppressed.

However, in the method of dicing the via wiring 90 in the dicing line region 2a by the blade 130, when the via wiring 90 is diced, dust is generated from the relatively fragile metal material of the via wiring 90 in the diced portion P2. obtain. If such metal material dust adheres to conductor portions such as the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70, it may cause a short circuit. Therefore, the method as shown in FIGS. 2 to 7 may fail to realize a high-quality semiconductor device 1Ba including a diamond layer.

In view of the above points, a configuration and method as described in the following first embodiment are adopted to realize a high-quality semiconductor device including a diamond layer.
[First embodiment]
FIG. 8 is a diagram illustrating an example of the semiconductor device according to the first embodiment. FIG. 8 schematically shows a fragmentary cross-sectional view of an example of the semiconductor device according to the first embodiment.

A semiconductor device 1 shown in FIG. 8 is an example of a semiconductor device including a HEMT. The semiconductor device 1 has a semiconductor layer 10 including a laminated structure of a first semiconductor layer 11 and a second semiconductor layer 12 . For example, SiC is used for the first semiconductor layer 11 , and nitride semiconductor such as GaN and AlGaN is used for the second semiconductor layer 12 . The second semiconductor layer 12 is provided with a gate electrode 30, a source electrode 40, and a drain electrode 50. As an example of a transistor, a current path is formed between the source electrode 40 and the drain electrode 50 using 2DEG electrons as carriers. A HEMT is formed. The second semiconductor layer 12 is further provided with an etching stopper 60 (electrode layer) connected to the source electrode 40 through the wiring 70 . A metal material, for example, is used for the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70. FIG. For the wiring 70, metal wires or the like are used in addition to a metal layer formed on an insulating film (not shown).

In the semiconductor device 1, a diamond layer 20 functioning as a heat spreader is provided on the main surface 10a of the semiconductor layer 10 opposite to the main surface on which the gate electrode 30, the source electrode 40, the drain electrode 50, and the like are provided. For example, by thinning the semiconductor layer 10 (the first semiconductor layer 11 thereof), the thermal resistance between the HEMT, which generates heat during operation, and the diamond layer 20 is reduced. In the semiconductor device 1, the diamond layer 20 is provided in the inner region AR2 of the major surface 10a of the semiconductor layer 10 inside the outer peripheral region AR1. Here, the inner area AR2 is an area surrounded by the outer area AR1. The diamond layer 20 is bonded to the inner region AR2 of the main surface 10a of the semiconductor layer 10 by a method such as surface activation bonding or atomic diffusion bonding, which relatively reduces the interfacial thermal resistance with the semiconductor layer 10 .

In the semiconductor device 1, the main surface 20a of the diamond layer 20 opposite to the semiconductor layer 10 has openings 121 in a region corresponding to the outer peripheral region AR1 and a region corresponding to the via hole 80 provided in the inner region AR2. A masking layer 120 having a is provided. A material that is resistant to dry etching of the diamond layer 20 using an O-based gas and dry etching of the semiconductor layer 10 using an F-based gas or a Cl-based gas is used for the mask layer 120 . For example, the mask layer 120 is made of an insulating material such as SiO ₂ (for example, having a thickness of 10 μm or more) or a metal material such as Ni or Al (for example, having a thickness of several μm order).

In the semiconductor device 1, a protective film 140 is provided in the outer peripheral area AR1 of the main surface 10a of the semiconductor layer 10, that is, the outer peripheral area AR1 of the main surface 10a of the semiconductor layer 10 not covered with the diamond layer 20. The protective film 140 covers the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10, extends from the outer peripheral region AR1 to the side surface 20b of the diamond layer 20 (corresponding to the inner side surface of the trench 21 described later), and further extends to the main surface of the diamond layer 20. It is provided so as to extend over the mask layer 120 provided on the surface 20a. A material that is resistant to dry etching of the semiconductor layer 10 using an F-based gas or a Cl-based gas is used for the protective film 140 . For example, the protective film 140 is made of a metal material such as Ni or Al with a thickness of 1 μm to 5 μm.

The semiconductor device 1 is provided with a via hole 80 that penetrates the diamond layer 20 and extends into the semiconductor layer 10 . The via hole 80 penetrates the diamond layer 20 provided in the inner region AR2 of the main surface 10a of the semiconductor layer 10 and the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 12) to reach the etching stopper 60. be provided. The etching stopper 60 has a function of stopping etching from the main surface 20a side of the diamond layer 20 when the via hole 80 is formed by etching, and a function as an electrode layer connected to the source electrode 40 through the wiring 70.

The protective film 140 is provided on the surface of the diamond layer 20 excluding the via hole 80, that is, on the main surface 20a and the side surface 20b, continuously from the outer peripheral region AR1. In the example of FIG. 8, the mask layer 120 extends from the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10 to the side surface 20b of the diamond layer 20, and further on the mask layer 120 provided on the main surface 20a of the diamond layer 20 (main surface 20a) is shown extending over a portion of the protective film 140. FIG. In addition, the protective film 140 may be provided so as to extend over the entire surface of the mask layer 120 as long as it is provided on the surface of the diamond layer 20 excluding the via hole 80 .

In the semiconductor device 1 , a via wiring 90 is provided in the via hole 80 . Via wiring 90 extends from inside via hole 80 onto mask layer 120 provided on main surface 20 a of diamond layer 20 . The via wiring 90 is further provided to extend over the mask layer 120 , the side surface 20 b of the diamond layer 20 , and the protective film 140 provided in the outer peripheral region AR 1 of the main surface 10 a of the semiconductor layer 10 . The via wiring 90 is provided so as to cover the protective film 140 and the diamond layer 20 and is partially provided in the via hole 80 . A metal material, for example, is used for the via wiring 90 .

In the manufacture of the semiconductor device 1 having the configuration described above, the semiconductor layers 10 of the plurality of semiconductor devices 1 formed in a wafer state are integrally divided with the diamond layer 20 to be bonded thereto, and singulated. be done. In the case of the semiconductor device 1 shown in FIG. 8, the semiconductor layer 10 is diced at the position of the side surface 10b to separate into individual pieces. In the semiconductor device 1, the semiconductor layer 10, the protective film 140, and the via wiring 90 are present at the diced position, but the hard diamond layer 20 is not present. Therefore, the semiconductor device 1 is singulated by dicing using a blade.

In the semiconductor device 1, as in the method shown in FIGS. 2 to 7, the via wiring 90 does not exist on the main surface where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided. Even if dicing is performed with a blade, generation of dust from the metal material of the via wiring 90 can be suppressed. In the semiconductor device 1, the generation of dust from the metal material during dicing is thus suppressed. Occurrence of a short due to this is suppressed. Therefore, a high-quality semiconductor device 1 including the diamond layer 20 is realized.

Next, an example of a method for manufacturing the semiconductor device 1 having the configuration described above will be described with reference to FIGS. 9 to 14. FIG.
9 to 14 are diagrams for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment. In the manufacturing method of the semiconductor device according to the first embodiment, the steps up to the steps shown in FIGS. 2 and 3 can be the same. Processes subsequent to the processes shown in FIGS. 2 and 3 will be sequentially described below with reference to FIGS. 9 to 14. FIG.

FIG. 9 is a diagram showing an example of a protective film forming process according to the first embodiment. FIG. 9A schematically shows a plan view of the relevant part of the process. FIG. 9B schematically shows a cross-sectional view of the relevant part of the process. 9A is a schematic plan view of the laminate 2 shown in FIG. 9B as viewed from the diamond layer 20 side. FIG. 9B is a schematic cross-sectional view taken along line IX-IX of FIG. 9A.

In manufacturing the semiconductor device 1, as described above, the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 12) provided with the gate electrode 30, the source electrode 40, the drain electrode 50, and the like, and the semiconductor layer 10 A laminate 2 is provided comprising a bonded diamond layer 20 (FIG. 2). The laminate 2 includes semiconductor layers 10 and diamond layers 20 of a plurality of semiconductor devices 1 formed in a wafer state. 2(A) and 2(B) (and FIGS. 3(A) and 3(B), FIGS. 9(A) and 9(B), FIGS. 10(A) and 10(B), FIG. 11(A) and 11(B), FIGS. 12(A) and 12(B), FIGS. 13(A) and 13(B), and FIG. part of the

A support 110 is attached using an adhesive 100 to the main surface side of the laminated body 2 where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, and the main surface 20a of the diamond layer 20 is: A mask layer 120 having openings 121 in predetermined regions is formed (FIG. 2). Openings 121 of mask layer 120 are provided in dicing line region 2a and via formation region 2b (FIG. 2). The dicing line region 2a is a region corresponding to a dicing line for dividing the laminate 2 into individual pieces of the semiconductor device 1 (its semiconductor layer 10) by dicing. The via forming region 2 b is a region corresponding to a via formed in each piece of the semiconductor device 1 (the semiconductor layer 10 thereof) divided by dicing the stacked body 2 .

Then, using the mask layer 120 as a mask, the diamond layer 20 is dry-etched using an O-based gas (FIG. 3). By this dry etching, a trench 21 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the dicing line region 2a of the laminate 2, and a trench 21 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the via formation region 2b. A via hole 22 reaching 10 is formed (FIG. 3).

The trenches 21 are formed so as to surround each diamond layer 20 (or separate each diamond layer 20) of the plurality of semiconductor devices 1 included in the laminate 2. As shown in FIG. The via holes 22 are formed in the diamond layers 20 of each semiconductor device 1 included in the laminate 2 .

After forming trenches 21 and via holes 22 by dry etching the diamond layer 20, as shown in FIGS. 9A and 9B, a protective film 140 is formed in the trenches 21 in the dicing line region 2a. The protective film 140 is formed using a metal material such as Ni or Al that is resistant to F-based gas or Cl-based gas used for dry etching of the semiconductor layer 10 . The protective film 140 covers the inner surface of the trench 21 , that is, the main surface 10 a of the semiconductor layer 10 at the bottom of the trench 21 and the inner side surfaces of the trench 21 , and covers the mask layer 120 provided on the main surface 20 a of the diamond layer 20 . formed to extend.

As shown in FIGS. 9A and 9B, the protective film 140 is continuous from the major surface 10a of the semiconductor layer 10 at the bottom of the trench 21 so as to cover the surface of the diamond layer 20 excluding the via hole 22. formed by The protective film 140 is not formed inside the via hole 22 . That is, in the via formation region 2b, the main surface 10a of the semiconductor layer 10 at the bottom of the via hole 22 and the inner side surface of the via hole 22 are exposed. 9A and 9B show the protective film 140 formed so as to extend from the inner surface of the trench 21 to part of the mask layer 120. As shown in FIG. In addition, the protective film 140 may be formed to extend over the mask layer 120 as long as it is formed on the surface of the diamond layer 20 excluding the via holes 22 . Here, the subsequent steps will be described taking as an example the case where the protective film 140 is formed as shown in FIGS. 9A and 9B.

FIG. 10 is a diagram showing an example of the semiconductor layer etching process according to the first embodiment. FIG. 10A schematically shows a plan view of the relevant part of the process. FIG. 10B schematically shows a fragmentary cross-sectional view of the process. 10(A) is a schematic plan view of the laminate 2 shown in FIG. 10(B) as viewed from the diamond layer 20 side. FIG. 10(B) is a schematic cross-sectional view taken along line XX of FIG. 10(A).

After forming the protective film 140, as shown in FIGS. 10A and 10B, dry etching of the semiconductor layer 10 is performed using the mask layer 120 and the protective film 140 as masks. When the protective film 140 is formed on the entire mask layer 120, dry etching of the semiconductor layer 10 is performed using the protective film 140 covering the mask layer 120 as a mask. For the dry etching of the semiconductor layer 10, an F-based gas or an F-based gas and a Cl-based gas is used. For example, an F-based gas is used to dry-etch both the first semiconductor layer 11 of SiC and the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN in the semiconductor layer 10 . Alternatively, an F-based gas is used to dry-etch the first semiconductor layer 11 of SiC in the semiconductor layer 10, and a Cl-based gas is used to dry-etch the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN. be.

By dry etching the semiconductor layer 10 using the mask layer 120 and the protective film 140 as a mask, the diamond layer 20 is formed in the via forming region 2b of the laminate 2 as shown in FIGS. 10A and 10B. A via hole 14 communicating with the via hole 22 and penetrating the semiconductor layer 10 is formed. As a result, a via hole 80 extending through the diamond layer 20 and the semiconductor layer 10 and reaching the etching stopper 60 is formed in the via forming region 2 b of the laminate 2 .

In addition to dry etching, wet etching can also be used to form the via holes 14 in the semiconductor layer 10 . In this case, a material resistant to wet etching is used for the mask layer 120 and the protective film 140 .

The via holes 80 are formed in the diamond layer 20 and the semiconductor layer 10 of each semiconductor device 1 included in the laminate 2 .
On the other hand, during the dry etching of the semiconductor layer 10 in the via formation region 2b, the trench 21 of the diamond layer 20 formed in the dicing line region 2a of the laminate 2 is resistant to the dry etching of the semiconductor layer 10. is covered with a protective film 140 having Therefore, in the dicing line region 2a, the semiconductor layer 10 is not etched, and the trenches 21 of the diamond layer 20 remain covered with the protective film 140. As shown in FIG.

FIG. 11 is a diagram showing an example of a via wiring formation process according to the first embodiment. FIG. 11A schematically shows a plan view of the relevant part of the process. FIG. 11B schematically shows a fragmentary cross-sectional view of the process. 11(A) is a schematic plan view of the laminate 2 shown in FIG. 11(B) as viewed from the diamond layer 20 side. FIG. 11(B) is a schematic cross-sectional view taken along line XI-XI of FIG. 11(A).

After forming the via hole 80 penetrating the diamond layer 20 and the semiconductor layer 10 in the via formation region 2b of the laminated body 2, a via wiring 90 is formed as shown in FIGS. 11A and 11B. . The via wiring 90 covers the inner surface of the via hole 80, that is, the etching stopper 60 at the bottom of the via hole 80 and the inner side surface of the via hole 80, and extends over the mask layer 120 provided on the main surface 20a of the diamond layer 20. It is formed. The via wiring 90 covers the trench 21 of the diamond layer 20 in the dicing line region 2a, that is, the inner surface of the trench 21 that penetrates the diamond layer 20 but does not extend into the semiconductor layer 10, and extends over the mask layer 120. 140 is also formed. The via wiring 90 is formed so as to cover the diamond layer 20 provided with the mask layer 120 and the protective film 140 of the trench 21, and partly provided in the via hole 80 (via holes 22 and 14).

For example, a stack structure of Ti and Au is formed as a seed layer in the via hole 80 of the stack 2, on the mask layer 120, and on the protective film 140 covering the trench 21 using a sputtering method, and is used as the power supply layer. A via wiring 90 is formed by electrolytic plating of Au.

FIG. 12 is a diagram showing an example of the support separating process according to the first embodiment. FIG. 12A schematically shows a plan view of the relevant part of the process. FIG. 12B schematically shows a fragmentary cross-sectional view of the process. 12(A) is a schematic plan view of the laminate 2 shown in FIG. 12(B) as viewed from the diamond layer 20 side. FIG. 12(B) is a schematic cross-sectional view taken along line XII-XII of FIG. 12(A).

After the via wiring 90 is formed, the support 110 is peeled off together with the adhesive 100 from the laminate 2 to be separated, as shown in FIGS. 12(A) and 12(B). In the laminated body 2 after separating the support 110 and the adhesive 100, the via wiring 90 is not exposed on the main surface where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, and the dicing line region on the main surface side is formed. 2a has a structure in which the via wiring 90 is not exposed.

FIG. 13 is a diagram showing an example of the dicing process according to the first embodiment. FIG. 13A schematically shows a plan view of the relevant part of the process. FIG. 13B schematically shows a fragmentary cross-sectional view of the process. 13(A) is a schematic plan view of the laminate 2 shown in FIG. 13(B) as viewed from the diamond layer 20 side. Illustration of the dicing tape 150 shown in FIG. 13(B) is omitted in FIG. 13(A). FIG. 13(B) is a schematic cross-sectional view taken along line XIII--XIII of FIG. 13(A).

After separating the support 110 and the adhesive 100, as shown in FIGS. 13(A) and 13(B), the diamond layer 20 side of the laminated body 2 is attached to the dicing tape 150, and the dicing line region 2a is positioned. It is diced and divided into individual pieces. Each individual piece divided by dicing becomes the semiconductor device 1 . For dicing the laminate 2, for example, a method of dicing using a blade 130 as shown in FIG. 13B is used. In the laminate 2, the semiconductor layer 10, the protective film 140, and the via wiring 90 are present at the diced positions, but the hard diamond layer 20 is not present. Therefore, the semiconductor device 1 is singulated by dicing using the blade 130 .

In the dicing using the blade 130, the semiconductor layer 10, the protective film 140 and the via wiring 90 are diced with the blade 130 from the main surface side where the gate electrode 30, the source electrode 40 and the drain electrode 50 are provided. be. Since the via wiring 90 does not exist on the main surface where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, dust is generated from the metal material of the via wiring 90 even if dicing is performed with the blade 130 from the main surface side. is suppressed. Since the generation of metal dust during dicing is suppressed in this way, the adhesion of metal dust to conductor portions such as the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70, resulting in Suppresses the occurrence of short circuits.

In each semiconductor device 1 separated into individual pieces by dicing, of the main surface 10a of the semiconductor layer 10, a region in which the trench 21 of the diamond layer 20 (the trench 21 cut by dicing) is formed (the trench 21 is cut) bottom surface) corresponds to the outer peripheral area AR1 shown in FIG. In each semiconductor device 1 separated into individual pieces by dicing, of the main surface 10a of the semiconductor layer 10, a region in which the trench 21 (the trench 21 cut by dicing) of the diamond layer 20 is formed (the trench 21 cut The area inside the bottom surface) corresponds to the inside area AR2 shown in FIG.

FIG. 14 is a diagram showing an example of the pick-up process according to the first embodiment. FIG. 14 schematically shows a cross-sectional view of the relevant part of the process.
After dicing with the blade 130, each diced piece is picked up from the dicing tape 150 as shown in FIG. Thereby, the semiconductor device 1 having the configuration as shown in FIG. 14 and FIG. 8 is obtained.

In manufacturing the semiconductor device 1 (FIGS. 9 to 14), a trench 21 is formed in the diamond layer 20 in the dicing line region 2a, and the trench 21 is covered with the protective film 140. As shown in FIG. Then, dicing is performed along the dicing line region 2a to cut the semiconductor layer 10 at the positions of the trenches 21 of the diamond layer 20 covered with the protective film 140 . As a result, in each semiconductor device 1 (FIG. 8) obtained by dicing, the diamond layer 20 is formed in the inner area AR2 inside the outer peripheral area AR1 corresponding to the bottom surface of the trench 21 on the main surface 10a of the semiconductor layer 10. and the peripheral area AR1 is covered with the protective film 140. As shown in FIG.

Alternatively, it can be said that each semiconductor device 1 ( FIG. 8 ) obtained by dicing has the side surface 10 b of the semiconductor layer 10 protruding outside the side surface 20 b of the diamond layer 20 . In each semiconductor device 1 obtained, the diamond layer 20 is formed in the inner area AR2 inside the outer peripheral area AR1 corresponding to the projecting portion of the main surface 10a of the semiconductor layer 10, and the outer peripheral area AR1 is protected. It can also be said that the structure is covered with the film 140 .

Each semiconductor device 1 (FIG. 8) obtained by dicing is provided with a via hole 80 extending into the semiconductor layer 10 through the outer peripheral region AR1 and the diamond layer 20 surrounded by the protective film 140 provided there. , and the via wiring 90 is provided there.

In manufacturing the semiconductor device 1 (FIGS. 9 to 14), the blade 130 is used for dicing the semiconductor layer 10, the protective film 140 and the via wiring 90 in the dicing line region 2a as described above. In dicing using the blade 130 from the main surface side where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, dust of the metal material of the via wiring 90 is generated because the via wiring 90 does not exist on the main surface. is suppressed. Therefore, it is possible to suppress adhesion of metallic dust to conductive portions such as the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, the wiring 70, and the occurrence of a short circuit due to the dust. This makes it possible to manufacture the semiconductor device 1 while suppressing a decrease in yield.

In the manufacture of the semiconductor device 1 (FIGS. 9 to 14), dicing using a blade 130 is possible, so dicing using a laser is not required. By not using a laser for dicing, it is possible to prevent the semiconductor device 1 from being damaged by heat during laser irradiation, and short-circuiting due to dust generated by laser ablation. Restrictions on the structure and manufacturing process of the semiconductor device 1 due to making the cut portion laser-transmissive can also be suppressed.

According to the configuration and method described in the first embodiment, a high-quality semiconductor device 1 including the diamond layer 20 is realized, and such a high-quality semiconductor device 1 is realized while suppressing a decrease in yield. be done.

In the semiconductor device 1 described above, silicon (Si), GaN, aluminum nitride (AlN), SOI (Semiconductor On Insulator), or the like is used in addition to SiC for the first semiconductor layer 11 of the semiconductor layer 10 . may In addition to GaN and AlGaN, nitride semiconductors such as InGaN (indium gallium nitride), InAlGaN (indium aluminum gallium nitride), and AlN may be used for the second semiconductor layer 12 of the semiconductor layer 10 . The second semiconductor layer 12 may contain one or more of such nitride semiconductors. The second semiconductor layer 12 may use a semiconductor such as Si, or a compound semiconductor such as SiC, GaAs (gallium arsenide), InP (indium phosphide), or SiGe (silicon germanium). may be contained in one or more. Even when such various materials are used for the semiconductor layer 10, the semiconductor device 1 can be formed according to the above example.

In the semiconductor device 1 described above, the semiconductor layer 10 includes not only the HEMT using 2DEG electrons as carriers, but also a transistor, MIS, using two dimensional hole gas (2DHG) holes as carriers. Various semiconductor elements such as an insulated gate transistor having a (metal insulator semiconductor) structure, an insulated gate bipolar transistor (IGBT), a diode, and the like may be provided. A plurality of semiconductor elements of the same type or different types may be mixed on the semiconductor layer 10 .

In the semiconductor device 1 described above, the number of via holes 80 and the number of etching stoppers 60 are not limited to one, respectively. The semiconductor device 1 may be provided with a plurality of via holes 80 passing through the diamond layer 20 and the semiconductor layer 10 and connected to one or more etching stoppers 60 .

The first embodiment has been described above. The semiconductor device 1 having the configuration described in the first embodiment can be applied to various electronic devices. As an example, a case where the semiconductor device 1 having the configuration described above is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.

[Second embodiment]
Here, an application example of the semiconductor device 1 having the configuration as described above to a semiconductor package will be described as a second embodiment.

FIG. 15 is a diagram illustrating an example of a semiconductor package according to the second embodiment. FIG. 15 schematically shows a plan view of essential parts of an example of a semiconductor package according to the second embodiment.

A semiconductor package 200 shown in FIG. 15 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1 (FIG. 8, etc.) described in the first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

A semiconductor device 1 including a transistor such as a HEMT is mounted on a die pad 210a of a lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 30 a connected to the gate electrode 30 , a pad 40 a connected to the source electrode 40 , and a pad 50 a connected to the drain electrode 50 . Pad 30a, pad 40a and pad 50a are respectively connected to gate lead 211, source lead 212 and drain lead 213 of lead frame 210 using wires 230 such as Al. The via wiring 90 connected to the source electrode 40 may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder. The lead frame 210, the semiconductor device 1 mounted thereon, and the wire 230 connecting them are sealed with a resin 220 so that the gate lead 211, the source lead 212, and the drain lead 213 are partially exposed.

A semiconductor package 200 having such a configuration is obtained by using the semiconductor device 1 described in the first embodiment.
As described above, in the manufacture of the semiconductor device 1, the diamond layer 20 in the dicing line region 2a of the laminated body 2 in a wafer state including the semiconductor layer 10 and the diamond layer 20 bonded to the main surface 10a thereof. A penetrating trench 21 is etched. Then, the trench 21 is covered with the protective film 140, the via hole 80 is formed in the semiconductor layer 10 by etching, the via wiring 90 is formed there, and dicing is performed at the position of the trench 21 covered with the protective film 140. . By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is bonded, and the protective film 140 is provided in the outer peripheral region AR1. A semiconductor device 1 is obtained. In the manufacture of the semiconductor device 1, the blade 130 is used for dicing, the diamond layer 20 in the dicing line region 2a is removed, and the semiconductor layer 10 remains. The occurrence of shorts caused by the dust can be suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. A high-quality semiconductor package 200 is realized by using such a semiconductor device 1 .

[Third embodiment]
Here, an application example of the semiconductor device 1 having the configuration as described above to a power factor correction circuit will be described as a third embodiment.

FIG. 16 is a diagram illustrating an example of a power factor correction circuit according to the third embodiment. FIG. 16 shows an equivalent circuit diagram of an example of the power factor correction circuit according to the third embodiment.
A power factor correction (PFC) circuit 300 shown in FIG. 16 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360 and an alternating current power supply 370 (AC).

In the PFC circuit 300, the drain electrode of the switch element 310, the anode terminal of the diode 320 and one terminal of the choke coil 330 are connected. A source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350 . The other terminal of capacitor 340 and the other terminal of choke coil 330 are connected. The other terminal of capacitor 350 and the cathode terminal of diode 320 are connected. A gate driver is connected to the gate electrode of the switch element 310 . An alternating current power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360 , and a direct current power supply (DC) is taken out between both terminals of the capacitor 350 .

For example, the semiconductor device 1 including a transistor such as a HEMT is used for the switch element 310 of the PFC circuit 300 having such a configuration.
As described above, in the manufacture of the semiconductor device 1, the diamond layer 20 in the dicing line region 2a of the laminated body 2 in a wafer state including the semiconductor layer 10 and the diamond layer 20 bonded to the main surface 10a thereof. A penetrating trench 21 is etched. Then, the trench 21 is covered with the protective film 140, the via hole 80 is formed in the semiconductor layer 10 by etching, the via wiring 90 is formed there, and dicing is performed at the position of the trench 21 covered with the protective film 140. . By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is bonded, and the protective film 140 is provided in the outer peripheral region AR1. A semiconductor device 1 is obtained. In the manufacture of the semiconductor device 1, the blade 130 is used for dicing, the diamond layer 20 in the dicing line region 2a is removed, and the semiconductor layer 10 remains. The occurrence of shorts caused by the dust can be suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. Using such a semiconductor device 1, a high-quality PFC circuit 300 is realized.

[Fourth embodiment]
Here, an application example of the semiconductor device 1 having the configuration as described above to a power supply device will be described as a fourth embodiment.

FIG. 17 is a diagram illustrating an example of a power supply device according to the fourth embodiment. FIG. 17 shows an equivalent circuit diagram of an example of the power supply device according to the fourth embodiment.
A power supply device 400 shown in FIG. 17 includes a primary circuit 410 , a secondary circuit 420 , and a transformer 430 provided between the primary circuit 410 and the secondary circuit 420 .

The primary side circuit 410 includes the PFC circuit 300 as described in the third embodiment and an inverter circuit, such as a full bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. be The full-bridge inverter circuit 440 includes a plurality of (here, four as an example) switch elements 441 , 442 , 443 and 444 .

The secondary circuit 420 includes a plurality of (here, three as an example) switch elements 421 , 422 and 423 .
For example, in the power supply device 400 having such a configuration, the switch element 310 of the PFC circuit 300 and the switch elements 441 to 444 of the full-bridge inverter circuit 440 included in the primary side circuit 410 include the above semiconductors such as HEMTs. A device 1 is used. For example, the switch elements 421 to 423 of the secondary side circuit 420 of the power supply device 400 use ordinary MIS transistors using Si.

As described above, in the manufacture of the semiconductor device 1, the diamond layer 20 in the dicing line region 2a of the laminated body 2 in a wafer state including the semiconductor layer 10 and the diamond layer 20 bonded to the main surface 10a thereof. A penetrating trench 21 is etched. Then, the trench 21 is covered with the protective film 140, the via hole 80 is formed in the semiconductor layer 10 by etching, the via wiring 90 is formed there, and dicing is performed at the position of the trench 21 covered with the protective film 140. . By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is bonded, and the protective film 140 is provided in the outer peripheral region AR1. A semiconductor device 1 is obtained. In the manufacture of the semiconductor device 1, the blade 130 is used for dicing, the diamond layer 20 in the dicing line region 2a is removed, and the semiconductor layer 10 remains. The occurrence of shorts caused by the dust can be suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. A high-quality power supply device 400 is realized by using such a semiconductor device 1 .

[Fifth embodiment]
Here, an application example of the semiconductor device 1 having the configuration as described above to an amplifier will be described as a fifth embodiment.

FIG. 18 is a diagram explaining an example of an amplifier according to the fifth embodiment. FIG. 18 shows an equivalent circuit diagram of an example of the amplifier according to the fifth embodiment.
Amplifier 500 shown in FIG. 18 includes digital predistortion circuit 510 , mixer 520 , mixer 530 and power amplifier 540 .

Digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the nonlinear distortion-compensated input signal SI and the AC signal. Power amplifier 540 amplifies a signal obtained by mixing input signal SI with an AC signal. In the amplifier 500 , for example, by switching a switch, the output signal SO can be mixed with an AC signal in the mixer 530 and sent to the digital predistortion circuit 510 . Amplifier 500 can be used as a high frequency amplifier and a high power amplifier.

The semiconductor device 1 including a transistor such as a HEMT is used for the power amplifier 540 of the amplifier 500 having such a configuration.
As described above, in the manufacture of the semiconductor device 1, the diamond layer 20 in the dicing line region 2a of the laminated body 2 in a wafer state including the semiconductor layer 10 and the diamond layer 20 bonded to the main surface 10a thereof. A penetrating trench 21 is etched. Then, the trench 21 is covered with the protective film 140, the via hole 80 is formed in the semiconductor layer 10 by etching, the via wiring 90 is formed there, and dicing is performed at the position of the trench 21 covered with the protective film 140. . By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is bonded, and the protective film 140 is provided in the outer peripheral region AR1. A semiconductor device 1 is obtained. In the manufacture of the semiconductor device 1, the blade 130 is used for dicing, the diamond layer 20 in the dicing line region 2a is removed, and the semiconductor layer 10 remains. The occurrence of shorts caused by the dust can be suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. Using such a semiconductor device 1, a high-quality amplifier 500 is realized.

Various electronic devices to which the semiconductor device 1 is applied (semiconductor package 200, PFC circuit 300, power supply device 400, amplifier 500, etc. described in the second to fifth embodiments) are mounted on various electronic devices or electronic devices. can do. For example, it can be installed in various electronic devices or devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, and manufacturing devices. It is possible.

The following supplementary remarks are disclosed with respect to the embodiment described above.
(Appendix 1) A semiconductor layer;
a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer;
a protective film provided in the peripheral region on the main surface of the semiconductor layer;
a via hole extending through the diamond layer and into the semiconductor layer;
and a via wiring provided in the via hole.

(Appendix 2) The semiconductor device according to appendix 1, wherein a metal material is used for the protective film.
(Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the protective film is provided continuously from the outer peripheral region on the surface of the diamond layer excluding the via hole.

(Appendix 4) The semiconductor device according to any one of appendices 1 to 3, wherein the via wiring is provided so as to cover the protective film and the diamond layer, and a part of the via wiring is provided in the via hole.

(Appendix 5) including an electrode layer provided on a side of the semiconductor layer opposite to the diamond layer,
the via hole penetrates the semiconductor layer and reaches the electrode layer;
5. The semiconductor device according to any one of appendices 1 to 4, wherein the via wiring is connected to the electrode layer.

(Appendix 6) The semiconductor layer is
a first semiconductor layer on the diamond layer side;
6. The semiconductor device according to any one of appendices 1 to 5, further comprising: a second semiconductor layer laminated on a side opposite to the diamond layer side of the first semiconductor layer, in which a current path is formed.

(Appendix 7) forming a diamond layer on the main surface of the semiconductor layer;
the diamond layer in a first region corresponding to a dicing line for dividing the semiconductor layer into pieces; and the diamond layer in a second region corresponding to a first via hole formed in each piece of the semiconductor layer to be divided. to form a trench penetrating the diamond layer in the first region and forming a second via hole penetrating the diamond layer in the second region;
forming a protective film covering the main surface of the semiconductor layer in the trench;
etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole communicating with the second via hole and extending into the semiconductor layer;
forming a via wiring in the communicating first via hole and the second via hole;
a step of dicing the semiconductor layer and the protective film covering the main surface in the trench at the position of the first region where the trench is formed.

(Appendix 8) The method of manufacturing a semiconductor device according to appendix 7, wherein a metal material is used for the protective film.
(Supplementary Note 9) The step of forming the protective film includes forming the protective film continuously from the main surface of the semiconductor layer in the trench on the surface of the diamond layer excluding the second via hole. 9. The method of manufacturing a semiconductor device according to appendix 7 or 8, characterized by comprising a step of:

(Supplementary Note 10) The step of etching the first region and the second region of the diamond layer to form the trench and the second via hole may include etching the first region of the diamond layer using a gas containing oxygen. a step of dry etching the region and the second region;
The step of etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole includes etching the semiconductor layer in the second via hole using a gas containing fluorine or chlorine. 10. The method of manufacturing a semiconductor device according to any one of Appendices 7 to 9, further comprising a step of dry etching.

(Supplementary Note 11) The step of forming the via wiring includes forming the via wiring so as to cover the protective film and the diamond layer and to be partially provided in the first via hole and the second via hole. 11. The method of manufacturing a semiconductor device according to any one of Supplements 7 to 10, characterized by:

(Appendix 12) including a step of forming an electrode layer on a side of the semiconductor layer opposite to the diamond layer,
forming the first via hole includes forming the first via hole reaching the electrode layer;
12. The method of manufacturing a semiconductor device according to any one of Supplements 7 to 11, wherein the step of forming the via wiring includes a step of forming the via wiring connected to the electrode layer.

(Appendix 13) The semiconductor layer is
a first semiconductor layer on the diamond layer side;
13. The semiconductor device according to any one of Appendices 7 to 12, further comprising a second semiconductor layer laminated on the side opposite to the diamond layer side of the first semiconductor layer and forming a current path. Production method.

(Appendix 14) A semiconductor layer;
a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer;
a protective film provided in the peripheral region on the main surface of the semiconductor layer;
a via hole extending through the diamond layer and into the semiconductor layer;
and a via wiring provided in the via hole. An electronic device comprising: a semiconductor device.

Reference Signs List 1, 1A, 1B, 1Ba semiconductor device 2 laminate 2a dicing line region 2b via forming region 10 semiconductor layers 10a, 20a main surfaces 10b, 20b side surfaces 11 first semiconductor layer 12 second semiconductor layer 13, 21, 81 trench 14, 22, 80 via hole 20 diamond layer 30 gate electrode 30a, 40a, 50a pad 40 source electrode 50 drain electrode 60 etching stopper 70 wiring 90 via wiring 100 adhesive 110 support 120 mask layer 121 opening 130 blade 140 protective film 150 dicing tape 200 semiconductor package 210 lead frame 210a die pad 211 gate lead 212 source lead 213 drain lead 220 resin 230 wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 switch element 320 diode 330 choke coil 340, 350 capacitor 360 Diode Bridge 370 AC Power Supply 400 Power Supply Device 410 Primary Side Circuit 420 Secondary Side Circuit 430 Transformer 440 Full Bridge Inverter Circuit 500 Amplifier 510 Digital Predistortion Circuit 520, 530 Mixer 540 Power Amplifier AR1 Outer Area AR2 Inner Area

Claims (10)

a semiconductor layer;
a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer;
a protective film provided in the peripheral region on the main surface of the semiconductor layer;
a via hole extending through the diamond layer and into the semiconductor layer;
and a via wiring provided in the via hole. 2. The semiconductor device according to claim 1, wherein a metal material is used for said protective film. 3. The semiconductor device according to claim 1, wherein the protective film is provided continuously from the outer peripheral region on the surface of the diamond layer excluding the via hole. 4. The semiconductor device according to claim 1, wherein said via wiring is provided so as to cover said protective film and said diamond layer, and a part of said via wiring is provided in said via hole. An electrode layer provided on the side of the semiconductor layer opposite to the diamond layer,
the via hole penetrates the semiconductor layer and reaches the electrode layer;
5. The semiconductor device according to claim 1, wherein said via wiring is connected to said electrode layer. forming a diamond layer on the main surface of the semiconductor layer;
the diamond layer in a first region corresponding to a dicing line for dividing the semiconductor layer into pieces; and the diamond layer in a second region corresponding to a first via hole formed in each piece of the semiconductor layer to be divided. to form a trench penetrating the diamond layer in the first region and forming a second via hole penetrating the diamond layer in the second region;
forming a protective film covering the main surface of the semiconductor layer in the trench;
etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole communicating with the second via hole and extending into the semiconductor layer;
forming a via wiring in the communicating first via hole and the second via hole;
a step of dicing the semiconductor layer and the protective film covering the main surface in the trench at the position of the first region where the trench is formed. The step of forming the protective film has a step of forming the protective film continuously provided from the main surface of the semiconductor layer in the trench on the surface of the diamond layer excluding the second via hole. 7. The method of manufacturing a semiconductor device according to claim 6, wherein: The step of forming the via wiring includes a step of forming the via wiring so as to cover the protective film and the diamond layer, and partially provided in the first via hole and the second via hole. 8. The method of manufacturing a semiconductor device according to claim 6 or 7. forming an electrode layer on a side of the semiconductor layer opposite to the diamond layer;
forming the first via hole includes forming the first via hole reaching the electrode layer;
9. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming said via wiring has a step of forming said via wiring connected to said electrode layer. a semiconductor layer;
a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer;
a protective film provided in the peripheral region on the main surface of the semiconductor layer;
a via hole extending through the diamond layer and into the semiconductor layer;
and a via wiring provided in the via hole. An electronic device comprising: a semiconductor device.

Images