JP2001137440A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of surely backing up and preserving required data in a RAM and surely utilizing the preserved data after power source restoration. SOLUTION: When power to this game machine is supplied, a CPU first confirms whether or not data set in a backup parity data area in the RAM capable of power backup for a prescribed period are '00'. When the data set in the backup parity data area are not '00', parity diagnosing (checksum confirmation) is performed. Then, when the result of the checksum confirmation is proper, a power failure restoration processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. It relates to a gaming machine in which a game is performed.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

[0006]

A game machine is equipped with various game machine control means including game control means. Generally, each gaming machine control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then
When a power failure occurs due to a power failure, etc.
The data inside will be lost. Therefore, at the time of recovery from a power failure or the like, the player must return to the initial state (for example, a state in which the power of the gaming machine is first turned on at the game store for the first time), which may cause disadvantage to the player. There is. For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a power supply backup RAM when an unexpected power failure such as a power failure occurs, and data stored when power is restored is restored. And then resume the game. However, if the way of saving and the way of restoring necessary data when the power is turned off are improper, the restored data may not match the data when the power is turned off. In such a case, unexpected disadvantages may still be given to the player.

[0008] Therefore, the present invention is required when a game is configured so that necessary data can be saved when an unexpected power failure such as a power failure occurs and a game can be resumed from a power-off state when the power is restored. It is an object of the present invention to provide a gaming machine capable of surely storing important data and reliably utilizing the stored data after the power is restored.

[0009]

A gaming machine according to the present invention comprises:
A game machine capable of giving a game result value to a player as a result of performing a predetermined game, and when power is turned on, stored data held in storage means capable of holding contents immediately before power-off is stored in a storage device. It is possible to perform a game state return control for returning the game state based on the game device control means for controlling the game device provided for the game, and the voltage of the predetermined potential power supply has decreased to a predetermined value. Power supply monitoring means for detecting that the power supply monitoring means detects the power supply monitoring means, the power supply monitoring means, the power supply monitoring means when the predetermined power off for holding the fluctuation data that fluctuates according to the progress of the game in the storage means When the power is restored from the power-off state while the data is being held by the storage means, the initialization processing is performed or the game state is changed to the state before the power-off, based on the data held in the storage means. And determining whether to return time process of returning. Note that the game result value is a concept indicating payout of a game ball or an increase in a score in the case of an image-type gaming machine.

[0010] The fluctuation data held in the storage means includes at least game state data indicating a game state, and the return processing includes a game state data read processing for restoring the game state. It may be.

The held data used to determine whether to perform the initialization processing or the recovery processing is, for example, a checksum.

The gaming machine control means calculates a checksum when the power is turned off and causes the storage means to store the checksum, and when the power is restored, checks the data held in the storage means by the checksum. It may be configured to perform processing.

Here, the gaming machine control means may be configured to perform an initialization process when the held data is not valid.

The power-off process includes a process of setting a flag indicating power-off, and the game-apparatus control means sets the state of the flag indicating power-off when the checksum is a predetermined value when the power is restored. And if the flag indicates that the power supply has been turned off, a recovery process may be performed.

The power-off processing may include processing for preventing access to the storage means.

The gaming machine is provided with second power supply monitoring means for detecting a power supply voltage drop after a predetermined period of time when the power supply monitoring means detects the voltage drop, and the game control microcomputer comprises:
The system may be configured to be reset in response to the input of the detection output from the second power supply monitoring unit.

A payout device for paying out at least a predetermined prize game medium is provided, and the gaming machine control means is a payout control means for performing payout control including prize payout control. Data retained even when the power of the gaming machine is turned off is: It may be configured to be data relating to the remaining amount of premium game media paid out from the payout device.

A payout device for renting out at least a predetermined game medium is provided, and the game device control means is a payout control means for performing payout control including game medium lending control. The data held even when the power of the gaming machine is turned off is a payout device. It may be configured to be data relating to the remaining amount of game media paid out from the device.

Further, the payout device for paying out a predetermined premium game medium can rent out the game medium, and the payout control means also executes the game medium lending control, so that the data held even when the power of the game machine is turned off can be obtained. May be configured to also include data relating to the remaining amount of the lending game media paid out from the payout device.

In other words, the payout device may be regarded as performing both the payout and lending of the prize of the game medium, and the payout device is divided into a payout device for paying out the prize game medium and a payout device for renting out a predetermined game medium. It may be considered as a thing. Note that, when viewed separately, they may be provided in the same housing (case) or may be installed as separate housings.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hitting ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and thereafter, enters the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary. In addition,
In this embodiment, a ball payout device 97 in which game balls are paid out by rotation of a stepping motor is illustrated as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure of sending out a ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game ball may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to control the winning ball payout.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a, 24a to the basic circuit 53, and a variable winning ball device. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the opening 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53; A lamp / LED circuit 60 for driving the lamp 10 and the decorative lamp 25 is mounted.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of volatile storage means used as a work memory, a CPU 56 for performing control operations in accordance with a control program, and an I / O controller 56.
/ O port section 57 is included. In this embodiment, the ROM
The RAM 55 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 therein, and the ROM 54 and the I / O port unit 57 may be external or internal. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 5, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full.

The detection signals from the cut-out detection switch 167 and the cut-out switch 187 (187a, 187b) are transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the out-of-ball detection switch 167 or the out-of-ball switch 187 indicates the out-of-ball state, or the detection signal from the full switch 48 indicates the full state. If it is, a prize ball control command for instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are also transmitted to the main board 3 via the relay boards 72 and 71.
1 is input to the I / O port 57. The prize ball count switch 301A and the ball lending count switch 30
1B is provided in the prize ball mechanism portion of the ball payout device 97, and detects the prize balls actually paid out.

When there is a prize, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

The prize ball control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer drive signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the detection signal of the winning ball count switch 301A is input to 72b via the relay board 72. The drive signal from the prize ball control board 37 to the payout motor 289 is
The output is transmitted to the payout motor 289 in the winning ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

The card unit 50 has a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, but those circuits are omitted in FIG.

In this embodiment, the case where the card unit 50 is provided is taken as an example. However, the present invention can be applied to a case where a game ball is lent according to the amount of money when a coin is inserted.

FIG. 6 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 6, a voltage drop signal from a first power supply monitoring circuit (first power supply monitoring means) mounted on a power supply board is input to an interrupt terminal (IRQ terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. Therefore, CPU5
No. 6 can confirm a power-off state by an interrupt (IRQ).

A second power supply monitoring circuit 90 is provided on the main board 31.
3 is installed. In this example, in the second power supply monitoring circuit 903, the power supply monitoring IC 904 has a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit.
A 30V power supply voltage is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. Then, for example, the detection voltage (voltage at which a voltage drop signal is output) of the first power supply monitoring circuit mounted on the power supply board is increased by +16.
V, and the detection voltage of the second power supply monitoring circuit 903 is +8 V
And In such a configuration, since the same voltage is monitored, the difference between the timing at which the first voltage monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal is desired. Can be reliably set in the predetermined period. The desired predetermined period is a period from the start of the power-down processing in response to the voltage drop signal from the first power supply monitoring circuit to the completion of the power-off processing.

The voltage drop signal from the second power supply monitoring circuit 903 is ORed with the initial reset signal from the initial reset circuit 65 and then input to the reset terminal of the CPU 56. Therefore, when the initial reset signal from the initial reset circuit 65 has a low level, or when the voltage drop signal from the second power supply monitoring circuit 903 has a low level, the CPU 56 sets the system reset state. (Non-operating state).

The reset I of the initial reset circuit 65
When the power of the gaming machine is turned on and the voltage of the + 5V power supply rises, the C651 sets the output signal to a high level when the + 5V power supply voltage exceeds a predetermined value. That is, the initial reset signal is turned off.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 7 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a display control board 80, a sound control board 70, and a lamp control board 35.
The game device control board such as the prize ball control board 37 is installed independently of the game machine control board, and generates a voltage used by each game machine control board and mechanical components in the gaming machine. In this example, AC24
V, DC + 30V, DC + 21V, DC + 12V and DC + 5V. Further, the capacitor 916 serving as a backup power supply is DC + 5V, that is, I
C is charged from a power supply line for driving C and the like.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each gaming machine control board and mechanical components is supplied.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 supplies power to the backup RAM (power-backed-up RAM, that is, a storage unit that can be in a storage content storage state) of the gaming machine control board when the power supply to the gaming machine is cut off, so that the storage state can be maintained. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing a +30 V power supply voltage and monitoring the +30 V power supply voltage. Specifically, when the + 30V power supply voltage becomes equal to or lower than a predetermined value (+ 16V in this example), a voltage drop signal is output assuming that power supply is cut off. In addition, +30
The V power supply voltage is a voltage immediately after conversion from AC to DC. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the prize ball control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU on each game device control board can operate for a while. Further, the power supply monitoring IC 902 is higher than the voltage for driving the CPU (+5 V in this example), and
Since the configuration is such that the voltage immediately after the conversion from AC to DC is monitored, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, the monitoring voltage is +30
When V is used, since the voltage supplied to various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, + 30V
By monitoring the voltage of the power supply, it is possible to detect a decrease in + 12V generated after the generation of + 30V before the voltage starts dropping. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the game machine control board, the first power supply monitoring circuit supplies a voltage drop signal to a plurality of game machine control boards. Can be. Regardless of the number of gaming machine control boards that require a voltage drop signal, it is sufficient that only one first power supply monitoring unit is provided, so that each gaming machine control unit in each gaming machine control board performs power supply return control described later. Does not significantly increase the cost of the gaming machine.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first checks whether or not the data set in the backup parity data area in the RAM 55 is "00" (step S1). The backup parity data area will be described later in detail. If the data set in the backup parity data area is not "00", parity diagnosis (checksum confirmation) is performed (step S2). If the result of the checksum check is valid (step S3), the CPU 56 executes a power failure recovery process described later (step S4). If the result of the checksum check is not valid, a normal initialization process is executed (step S6).

If the data set in the backup parity data area is "00",
The PU 56 checks the power-off flag (step S5),
If the power-off flag is set (step S5),
The power failure recovery processing is executed based on the game state data stored in the RAM 55 (step S4). If the power-off flag has not been set, a normal initialization process is performed (step S6).

Thereafter, in the main process, the process shifts to a loop process for checking the monitoring of the timer interrupt flag (step S8). In the loop, a display random number update process (step S7) is also executed.

In the normal initialization process, as shown in FIG. 9, the register and RAM are cleared (step S6).
a) and the initial setting (timeout is 2 ms) of the timer register provided in the CPU 56 so that the timer interrupt is periodically performed every 2 ms after the necessary initial value setting process (step S6b) is performed. And a setting to operate the repetition timer) is performed (step S6c). That is, in step S6c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 10, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag has been set in step S8, the CPU 56 resets the timer interrupt flag (step S8).
9), a game control process is executed (step S10). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

FIG. 11 is a flowchart showing a game control process. In the game control process, the CPU 56 first performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then executes the display control command. Output processing is performed (display control data output processing: step S22).

Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 further includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

Further, the CPU 56 performs signal processing with the award ball control board 37 (step S31). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control process, the game machine is forcibly returned to the initial state by an external interrupt that occurs periodically. Describing with reference to the example shown in FIG. 11, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good. Even in such a configuration, the flag is not determined until all of the game control processing is executed, so that execution of all the processing during the game control processing is guaranteed to be completed.

FIG. 12 is a flowchart showing an example of a power failure occurrence interrupting process executed in response to an interrupt based on a voltage drop signal from the first power supply monitoring circuit of the power supply board 910. In the power failure occurrence interruption process, the CPU 56 first sets the interruption prohibition (step S41). In the power failure occurrence interrupt process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during that process, the voltage may drop to a level at which the CPU cannot operate before the checksum generation process is completed. The setting is made so that no interrupt occurs.

Next, the CPU 56 turns off all the output ports (step S43). If necessary, the contents of each register are stored in the backup RAM area (step S44). In addition, backup RAM
An appropriate initial value is set in the backup check data area of the area (step S45), exclusive OR is sequentially performed on the initial value and the data in the backup RAM area (step S46), and the final operation value is converted to the backup parity data. The area is set (step S47). Thereafter, a power-off flag is set (step S48).
Further, the RAM access is prohibited (step S4).
9). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is disabled from the outside by the reset signal from the power supply monitoring IC 904 shown in FIG. 6, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM
The access prohibition control and the operation stop control can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

In this embodiment, the program is looped at the last part in the power failure occurrence interrupt processing. However, a HALT instruction may be issued.

Further, as described above, the power-off flag set before the RAM access is prohibited is set to indicate whether recovery from a power failure has occurred when the set value of the backup parity data area is “00” at the time of power-on. Used to determine whether or not. Further, the processing of steps S41 to S49 is completed before the second power supply monitoring unit generates the voltage drop signal. In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the detection is completed before the second power supply monitoring means generates the voltage drop signal.

FIG. 13 is a flowchart showing an example of the power outage restoration process (step S4) shown in FIG.
In the power failure recovery processing, the CPU 56 performs a game state recovery processing for returning the internal state to the state at the time of power failure (step S53), and clears the power failure flag (step S55).

FIG. 14 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 14A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity check is performed in the checksum confirmation process (step S2) of the main process. FIG. 14B is an explanatory diagram showing an example of the parity check. If all the data in the backup area is stored as it is, when the power is turned on again, FIG.
Data as shown in (A) is set in the backup area.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, in the parity check processing (checksum confirmation processing), the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the backup RAM for backing up the power for a predetermined period even if the power of the game machine is cut off. The program executed by the CPU 56) is configured to perform a game state restoration process (step S53) for restoring the game state based on the backup data if the backup RAM is in the backup state. Therefore, there is provided a gaming machine which can prevent a disadvantage from being brought to a player even if a power failure occurs.

When the power is turned on, the backup RAM
Data check of area (parity check in this example)
Is performed. If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the initialization processing (step S6) executed when the power is turned on without power recovery from the power failure is executed.

Further, in the main processing shown in FIG. 8, when the data set in the backup parity data area is not "00", a checksum confirmation processing is performed (steps S1, S2), and the backup parity data area is checked. Is "00", it is determined by the power-off flag whether or not to perform the power failure recovery process, that is, whether or not the gaming state can be recovered. Then, even when the checksum calculated when the power is turned off happens to be “00”, the game state restoring process is executed.

The checksum calculated when the power is turned off is "0".
In the case of “0”, in the checksum confirmation processing executed at power-on, exactly the same operation as the operation at the time of power-off is executed (in the example of FIG. 14, the initial data and the parity data correspond to each other). Because it matches). Therefore, the reliability of the parity check is lost. However, in this embodiment, the gaming state can be restored even if the checksum has such a predetermined value.

When determining whether or not to execute the power failure recovery processing, that is, when determining whether or not to recover the game state, the special process flag and the like in the stored RAM data and the number of start winning prizes are stored. According to the data, the gaming machine is in the game waiting state (the symbol is not changing, the jackpot is not playing, the probability is not changing, and there is no start winning memory)
When it is confirmed that the game state is restored, the initialization processing may be executed without performing the game state restoration processing.

Hereinafter, the game state restoring process will be described. First, in this embodiment, the CP of the main substrate 31
A display control command, a sound control command, and a lamp control command that the U56 sends to the display control board 80, the sound control board 70, and the lamp control board 35 will be described.
Each control command is determined to be sent according to the progress of the game in the special symbol process process (step S27) in the game control process shown in FIG. 11, and specific data is displayed in the display control data setting process (step S21). Is set, and is transmitted by being output from the output port in the display control data output process (step S22).

FIG. 15A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation on the variable display section 9. In this embodiment, the C
When starting the symbol change, the PU 56 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35. To the display control board 80, a symbol designating command indicating a fixed symbol of the middle left and right symbols is further transmitted.

When the symbol variation is determined, a variation stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35.
Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 15B is an explanatory diagram showing an example of the transmission timing of each control command related to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU of the main board 31
56 sends a big hit start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 at the start of the big hit game. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. When each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receives the big hit start command, it performs display control, sound generation control, and lamp lighting control at the start of the big hit. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the display control board 80
CPU performs the first round of display.

Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70, and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is transmitted. Upon receiving the normal screen display command, each game device control means changes the control state to a game waiting state.

FIG. 16 is a flowchart showing an example of the game state restoring process (step S53) performed in the power outage restoring process shown in FIG. In this example, the CPU 56
Restores the value stored in the backup RAM to the register if the contents of the register need to be restored (step S61). Then, the game state at the time of the power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

If the game state is a symbol change (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). If the gaming state is a jackpot game (step S64), the last transmitted control command before the power failure is displayed on the display control board 8.
0, control to send to the sound control board 70 and the lamp control board 35 is performed (step S65). When the game state is other than the above, for example, the normal screen display command is transmitted to the display control board 80 and the sound control board 7.
0 and control to send to the lamp control board 35 is performed (step S66). In addition, for example, the state of the variable prize ball device 15 when the big hit is in progress is automatically performed in a later game control process because the data in the RAM is stored.

FIG. 17 is an explanatory diagram showing an example of the control state when the power is restored after a power failure has occurred. 17, the state of the variable display is realized by the CPU (display control means) of the display control board 80, and the state of the sound is controlled by the sound control board 7.
0 is realized by the CPU (sound control means), and the state of the lamp is controlled by the CPU (lamp control means) of the lamp control board 35.
It is realized by.

FIG. 17A shows an example in which the power is restored after a power failure occurs during the change of the symbol. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 16). Since the change start command is a command sent at the start of the symbol change,
The states of the variable display control, the sound control, and the lamp control return to the states at the start of the change. In this embodiment, the fluctuation start command includes information for specifying the fluctuation time, and the main board 3
After transmitting the fluctuation start command, the first CPU 56 does not transmit anything (except for the symbol designation command) until the finalization command at the end of fluctuation (fluctuation stop command). Therefore, if a power failure occurs during the symbol change, the change cannot be restarted from the state in the middle of the change, but the display control, sound control, and lamp control are synchronized by resending the change start command. Return to

Note that, on the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display results (fixed symbols) and the like in the fluctuations after the restoration of the power supply are the same as the display results and the like that would have been made in the fluctuations interrupted by the power failure. Therefore, there is no disadvantage to the player.

FIG. 17 (B) shows an example in which the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 last before the power failure is sent again (step S65 in FIG. 15). Therefore, the sound control and the lamp control return to the control state during the big hit game. In addition, the display control also returns to the state performed at the time of the power failure.

On the main board 31, various parameters during the big hit game (number of times of opening the special winning opening, number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

In the above embodiment, the case where the game control means performs the data saving processing and the restoration processing has been described. However, the RAM in the prize ball control means, the voice control means, the lamp control means and the display control means has been described.
May be backed up by a power source, and the prize ball control means, the display control means, the sound control means, and the lamp control means may also perform the processing described above. However, the prize ball control means, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

Further, in this embodiment, two power supply monitoring circuits are provided. When the power supply voltage decreases, the second power supply monitoring means (the power supply monitoring IC 904 in this example) generates the voltage reduction signal at the first time.
The power supply monitoring means (power supply monitoring IC 902 in this example) is set to be later than the time when the voltage drop signal is generated. Further, a voltage drop signal from the second power supply monitoring means is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters a power-off wait state after executing a power-out occurrence processing (power-off processing) based on a voltage drop signal from the first power supply monitoring circuit (power supply monitoring IC 902). In the power-off wait state,
It will enter the reset state. That is, the CPU 56
Operation stops. In the power supply waiting state, the input / output state becomes unstable because the + 5V power supply voltage value gradually decreases.
Since U56 is in the reset state, abnormal operation based on undefined data is prevented.

As described above, in this embodiment, the CPU
56 executes the power-off processing in response to the input of the detection output from the first power monitoring means, and resets the system in response to the input of the detection output from the second power monitoring means (power monitoring IC 904). As a result, data can be reliably stored when the power is turned off, and it is possible to prevent the player from being disadvantaged.

Note that the first power supply monitoring means is a power supply board 91.
0, and the second power monitoring means is mounted on the main board 31. However, the second power monitoring means is mounted on the power board 910, and the first power monitoring means is mounted on the main board 31. Is also good.

Also, in the above embodiment, the detection signal from the first power supply monitoring means is the IR signal of the microcomputer.
Although the case where the power-off process is executed by an interrupt process by being input to the Q terminal is taken as an example, the detection signal from the first power monitoring unit is input to the non-maskable interrupt terminal (NMI terminal) and the NMI terminal is output. The power-off process may be executed by an NMI process based on an interrupt signal to the power supply. Further, the first voltage drop signal may be detected through the input port.
In that case, the monitoring of the input port is performed in the main processing executed by the CPU 56.

Next, the operation of the prize ball control means when a power failure occurs will be described. FIG. 18 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for monitoring and backing up the power supply. As shown in FIG. 18, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) mounted on the power supply board 910 is transmitted to the prize ball control CP.
It is input to the interrupt terminal (IRQ terminal) of U371.
Therefore, the prize ball control CPU 371 can confirm the occurrence of power interruption by the interrupt processing.

While power is not being supplied from the + 5V power supply which is the drive power supply for the prize ball control CPU 371 and the like, at least a part of the internal RAM of the prize ball control CPU 371 uses the backup power supplied from the power supply board 910 as a backup. Backed up by connecting to the terminal,
The contents are preserved even if the power to the gaming machine is turned off. When the + 5V power supply is restored, the initial reset circuit 935
Generates a reset signal from the CPU for controlling the prize ball.
371 returns to the normal operating state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In the configuration shown in FIG. 18, the prize ball control board 37
Is equipped with a second power supply monitoring circuit 933. In this example, in the second power supply monitoring circuit 933, the power supply monitoring IC 934 monitors the + 30V power supply voltage which is the same as the power supply voltage monitored by the first power supply monitoring circuit on the power supply board 910, and the voltage value is set to a predetermined value. When the value falls below the value, a low level voltage drop signal is generated. Second power supply monitoring circuit 933
Is provided, the second power supply monitoring circuit 933 is provided.
Detection voltage (voltage at which a voltage drop signal is output)
Is lower than the detection voltage of the first power supply monitoring circuit mounted on the power supply board 910.

The voltage drop signal from the second power supply monitoring circuit 933 is logically ORed with the initial reset signal from the initial reset circuit 935 and then input to the reset terminal of the prize ball control CPU 371. Therefore, the CPU for controlling the prize ball
371 indicates a reset state (non-operating state) when the initial reset signal from the initial reset circuit 935 is at a low level, or when the voltage drop signal from the second power supply monitoring circuit 933 is at a low level. State).

FIG. 19 shows the main board 31 to the prize ball control board 3.
7 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted to No. 7; FIG. As shown in FIG. 19, the upper 4 bits in one byte are used as a control designating unit, and the lower 4 bits are used as an area indicating the number of prize balls.

As shown in FIG. 20, when bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control designation section, it indicates that the command is a payout number designation command. ,
"0, 1" indicates a payout designation command.
The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

Bits 7, 6, 5, and 4 are "1, 0, 0,
The ball-out designation command of “0” is transmitted from the main board 31 when it is detected that there is no more supply ball. The firing stop designation command in which the bits 7, 6, 5, and 4 are "1, 0, 0, 1" indicates that the surplus ball tray 4 is full and the full switch 48 is turned on (the full tank state). (When the flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The winning ball control commands D7 to D0 are output in positive logic. When the award ball control commands D7 to D0 are output, a negative logic award ball control INT signal is output.

In this embodiment, as shown in FIG. 21, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal goes low for at least 5 μs. The prize ball control INT signal is transmitted to the prize ball control board 37.
Is connected to the interrupt terminal of the CPU 371 for controlling the prize ball. Therefore, when there is an interrupt, the award ball control CPU 371 transmits the award ball control commands D7 to D0 to the main board 31.
And recognizes that it has been sent from the CPU, and performs a prize ball control command receiving process in the interrupt process.

The command configuration shown in FIG. 19 is an example, and another configuration may be used. For example, the upper and lower bits in one byte may be reversed from the configuration shown in FIG.

FIG. 22 is a flowchart showing the main processing of the award ball control CPU 371. In the main processing,
The winning ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701).
If data is set in the RAM area (backup RAM area) of the built-in RAM where the power is backed up, those areas are not cleared. After that, in this embodiment, the CPU 371 for controlling the prize ball.
Shifts to a loop process for checking the monitoring of the timer interrupt flag (step S702).

In the initialization processing in step S701, if the value of the total number storage described later is not 0, the non-backup RAM area is cleared. Then, setting for restarting the prize ball is performed. For example, a flag during processing of a prize ball is set. Note that even in the backup RAM area,
If it is an area that is not related to the number of winning balls or the number of ball lending,
You may make it clear by designating those addresses. Furthermore, in addition to these processes, initial settings of a timer register provided in the CPU for controlling a prize ball 371 so that a timer interrupt is periodically performed every 2 ms (setting that the timeout is 2 ms and setting of the repetition timer operating) ) Is performed. That is, a process for activating a timer interrupt,
And a process of setting a timer interrupt interval.

Therefore, in the present embodiment, the internal timer of the award ball control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 23, when a timer interrupt occurs, the CPU 371 for controlling the prize ball.
Sets the timer interrupt flag (step S71)
1).

The CPU 371 for controlling the prize ball controls step S7.
In 02, when it is detected that the timer interrupt flag has been set, the timer interrupt flag is reset (step S703), and a prize ball control process and a ball lending control process are executed (steps S705 and S706). According to the above control, in this embodiment, the prize ball control process and the ball lending control process are started every 2 ms. In this embodiment, only the flag is set in the timer interruption processing, and the prize ball control processing and the like are executed in the main processing. However, the prize ball control processing and the like may be executed in the timer interruption processing.

FIG. 24 is an explanatory diagram showing an example of use of the RAM incorporated in the CPU 371 for controlling a prize ball. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are formed. The total number storage stores the total number of payouts instructed from the main board 31 side. The lending ball number storage stores the number of unpaid ball lending.

FIG. 25 is a flowchart showing a prize ball control command receiving process by the interrupt process. The award ball control INT signal from the main board 31 is input to the interrupt terminal of the award ball control CPU 371. Therefore, when the award ball control INT signal from the main board 31 is turned on, the award ball control CP
U371 is interrupted, and the reception processing of the award ball control command shown in FIG. 25 is started.

In the award ball control command receiving process, the award ball control CPU 371 first reads 1-byte data from the input port assigned to the input of the award ball control command data (step S852). If the read data is a payout number instruction command (step S8)
53), the number specified by the payout number instruction command is added to the total number storage (step S855). Otherwise, a communication end flag is set (step S85).
4). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

As described above, the CPU 371 for controlling the prize ball mounted on the prize ball control board 37 is the CPU 5 of the main board 31.
The number of award balls included in the payout number instruction command sent from 6 is stored in the backup RAM area (total number storage).

FIG. 26 shows a prize ball control process (step S70).
It is a flowchart which shows 5). In the prize ball control processing, the prize ball control CPU 371 checks whether or not the total number storage is not 0 (step S511). If the total number storage is not 0, the award ball control CPU 371 performs an award ball payout process (step S512). In the prize ball payout process, if the payout motor 289 is not turned on, it is turned on, and the detection output of the prize ball count switch 301A is used to confirm whether or not the game balls have been paid out. When it is confirmed that one payout has been made (step S513), the value of the total number storage is decremented by one (step S513).
514). When the value of the total number storage becomes 0 (step S515), the payout motor 289 is turned off (step S516).

The contents of the total number storage are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the award ball control CPU 371 can continue the award ball payout process based on the contents of the total number storage.

When the power is turned on, the CPU 371 for controlling the prize ball can determine whether to perform the normal initialization processing or restore the state during the prize ball simply by checking the data in the backup RAM area. That is, with a simple judgment,
The prize ball processing can be restarted for the unpaid prize balls.

The prize ball controlling CPU 371 manages the number of prize balls designated from the main board 31 as a total number in the total number storage, but the number of prize balls (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the payout of each prize ball is completed, the corresponding number counter is decremented by one. Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the content of each number counter.

FIG. 27 shows a ball lending control process (step S7).
It is a flowchart which shows 06). In the ball lending control processing, the prize ball control CPU 371 checks whether or not a prize ball is being paid out (step S531). If the prize balls are not being paid out, it is confirmed whether or not the stored number of lending balls is not 0 (step S532). If the lending ball number storage is not 0, the award ball control CPU 371 performs a ball lending process (step S533). In the ball lending process, the payout motor 2
If 89 has not been turned on, it is turned on, and it is checked whether or not a game ball has been paid out based on the detection output of the ball lending count switch 301B. Then, when it is confirmed that one payout has been made (step S534), the value of the stored number of lending balls is decremented by one (step S535). Further, when the value of the number of stored lending balls becomes 0 (step S5).
36), and turns off the payout motor 289 (step S53).
7). In this embodiment, the prize ball and the ball lending are performed by the same payout device.

Next, it is confirmed whether or not there is a ball lending request from the card unit 50 (step S538), and if there is a request, the number corresponding to the requested unit number is added to the value of the lending ball number storage (step S539). .

The contents of the number-lending-ball storage are stored by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the lending ball number storage.

Note that the prize ball control CPU 371 manages the number of lent balls requested by the card unit 50 in units (for example, in units of 100 yen) as a total number in the lent ball number storage. Good. For example, a ball lending counter is provided, and when a ball lending request is issued, the ball lending counter is incremented by one. When the payout of the number of units is completed, the ball lending counter is decremented by one. Also in that case, the ball lending counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball controlling CPU 371 can continue the ball lending process based on the content of the ball lending counter.

FIG. 28 shows that the CPU 371 for controlling the prize ball controls the first
7 is a flowchart showing a power failure occurrence interrupt process executed in response to an interrupt from a power monitoring unit. Power supply board 901
When the power supply monitoring IC 902 detects a drop in the power supply voltage, the voltage drop signal indicates a voltage drop, and the power failure occurrence interrupt processing is started. In the power failure occurrence interruption processing, the prize ball control CPU 371 sets interruption prohibition (step S
801), the RAM access is prohibited (step S802), and the process enters a loop process. That is, no processing is performed.

That is, the CPU itself is set to a state where it does not operate except for reset release or occurrence of an interrupt. Therefore,
Before the operation is disabled from the outside by the reset signal from the power supply monitoring IC 934 shown in FIG. 18, the operation is stopped internally. Thus, the operation of the award ball control CPU 371 is reliably stopped when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

In this embodiment, the program is looped at the last part in the power failure occurrence interrupt processing. However, a HALT instruction may be issued.

As in the case of the game control means, the power supply backup R
A checksum may be generated for the AM data, and the checksum may be stored.

FIG. 29 is a flowchart showing a part of the initialization processing (step S701) executed by the CPU 371 for controlling the prize ball when the power is turned on. When the power is turned on or the power is restored, the CPU 371 for controlling the prize ball
First, it is checked whether the value of the total number storage or the lending ball number storage formed in the backup RAM area is not 0 (step S901). If both are 0, it means that there were no unpaid game balls at the time of the previous power-off, so that normal initialization processing is performed. That is, the register and the entire RAM area are cleared (step S9).
03), the stack pointer is initialized (step S904).

If the value of the storage of the total number or the storage of the number of lending balls is not 0, an address is designated to clear the register and the non-backup RAM area (step S90).
5). Then, a setting for restarting the award ball or ball lending is performed. For example, a flag during processing of a prize ball is set (step S906). If the backup RAM area is an area irrespective of the number of payouts, those addresses may be designated and cleared.

As described above, the CPU 371 for controlling the prize ball
When the power is turned on, it is possible to determine whether to perform the normal initial setting process or to restore the state during the prize ball only by checking the data in the backup RAM area. That is, the payout process can be restarted for the unpaid prize balls and the unpaid lending balls by a simple judgment.

The CPU 371 for controlling the prize ball also sets the parity data and the power-off flag in the power-off processing, similarly to the CPU 56 of the main board 31, so that the power-on
Whether or not to perform the initialization process may be determined based on the parity data and the power-off flag.

In this embodiment, the CPU 3 for controlling the prize ball
71 detects a first voltage drop signal (voltage drop signal from the first power supply monitoring means) from a maskable external interrupt terminal (IRQ terminal) power supply board, but cannot mask the first voltage drop signal. It may be introduced to an interrupt terminal (NMI terminal). In that case, the power failure occurrence processing shown in FIG. 28 is executed by the NMI processing. Further, the first voltage drop signal may be detected through the input port. In that case, the input port is monitored in the main processing executed by the award ball control CPU 371.

Also, step S901 shown in FIG.
When the processing of (1) is executed, a parity check (check sum check) based on the stored parity data may be performed.

In the pachinko gaming machine 1 according to each of the above-described embodiments, when a special symbol is variably displayed on the variable display section 9 based on a start winning prize, a predetermined game value is obtained. Although it was a first-class pachinko gaming machine that can be given to a player, a predetermined game value that can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a start winning prize. Two types of pachinko machines,
A third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a start winning prize is a predetermined combination of symbols. Even so, the present invention can be applied.

[0150]

As described above, according to the present invention, when a power supply monitoring unit detects a voltage drop of a predetermined potential power supply, a predetermined power-off process is performed by the gaming machine control means. In addition, when the power is restored, it is configured to determine whether to perform the initialization process or the return process of returning the gaming state to the state before the power was cut off based on the data held in the storage means, In the event that the power is turned off, necessary data can be reliably stored, and the stored data can be reliably used after the power is restored.

The fluctuation data held in the storage means includes at least game state data indicating a game state, and the return processing includes a game state data readout processing for restoring the game state. In this case, the game state can be restored using the held data, so that the restored game state is accurate.

When the held data used to determine whether to perform the initialization processing or the recovery processing is a checksum, the initialization processing or the recovery processing is performed using a checksum that can be easily calculated. You can decide whether to do it.

When the power is turned off, a checksum is calculated and stored in the storage means, and when the power is restored, the data stored in the storage means is confirmed by the checksum, and when the stored data is valid, a recovery process is performed. In this case, it is possible to prevent the processing at the time of return from being executed based on the data changed during the power-off or during the power-off, and the gaming state is not restored incorrectly. .

If the gaming machine control means is configured to perform an initialization process when the held data is not valid, there is data that has changed during power-off or during power-off. In such a case, the initialization process is executed, so that the game state is not incorrectly restored.

When the power is restored, the gaming machine control means checks the state of a flag indicating power-off if the checksum is a predetermined value, and performs a recovery process if the flag indicates power-off. In such a configuration, even if the value of the checksum held when the power is turned off accidentally becomes a value that is not suitable for the check, the gaming state can be restored.

In the case where the processing at the time of power failure includes processing for preventing access to the storage means, it is possible to more reliably prevent data in the storage means from being destroyed at the time of power failure.

A second power supply monitoring means for detecting a power supply voltage drop after a predetermined period of time when the power supply monitoring means detects the voltage drop is provided, and the game control microcomputer inputs a detection output from the second power supply monitoring means to the input. If the system is configured to be reset accordingly, the operation of the gaming machine control means is also externally stopped by the system reset, so that more reliable data storage can be performed when the power is turned off.

[0158] The gaming machine control means is a payout control means for performing prize payout control, and the data held even when the power of the gaming machine is turned off is data relating to the remaining amount of the prize game medium to be paid out from the payout apparatus. If configured,
Upon recovery from a power failure or the like, the payout of unpaid premium game media can be automatically resumed.

The gaming machine control means is a payout control means for performing game medium lending control, and the data held even when the power of the gaming machine is turned off is data relating to the remaining amount of the game medium paid out from the payout apparatus. If configured,
Upon recovery from a power failure or the like, the payout of unrented game media can be automatically resumed.

It is also possible for a payout device that pays out a predetermined prize game medium to rent out the game media, and the data held even when the power of the gaming machine is turned off relates to the remaining amount of the rented game media paid out from the payout device. When configured to include data, the payout of unpaid premium game media and unrented game media is automatically performed at the time of recovery from a power failure, etc., using an integrated payout device. Can resume.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating components related to a prize ball, such as a prize ball control board and components of a ball payout device.

[Fig. 6] C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 7 is a block diagram illustrating a configuration example of a power supply board.

FIG. 8 is a flowchart showing main processing executed by a CPU on a main board.

FIG. 9 is a flowchart showing an initialization process.

FIG. 10 is a flowchart showing a 2 ms timer interrupt process.

FIG. 11 is a flowchart showing a game control process.

FIG. 12 is a flowchart showing a power failure occurrence process.

FIG. 13 is a flowchart illustrating a power failure recovery process.

FIG. 14 is an explanatory diagram for describing a backup parity data creation method.

FIG. 15 is an explanatory diagram showing an example of a transmission timing of each control command from the main board.

FIG. 16 is a flowchart illustrating an example of a game state restoration process.

FIG. 17 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure occurs.

FIG. 18 is a block diagram showing a configuration example around a CPU for controlling a prize ball for monitoring and backing up a power supply.

FIG. 19 is an explanatory diagram showing a configuration example of a winning ball control command.

FIG. 20 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 21 is a timing chart showing how a winning ball control command data is output.

FIG. 22 is a flowchart showing a main process executed by a winning ball control CPU.

FIG. 23 is a flowchart showing a timer interrupt process of a winning ball control CPU.

FIG. 24 is an explanatory diagram showing one configuration example of a RAM in the winning ball control means.

FIG. 25 is a flowchart showing a command receiving process of the winning ball control CPU.

FIG. 26 is a flowchart showing a prize ball control process.

FIG. 27 is a flowchart showing a ball lending control process.

FIG. 28 is a flowchart showing a power failure generation process executed by the winning ball control CPU.

FIG. 29 is a flowchart illustrating an example of initialization processing of a winning ball control CPU.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 371 Prize ball control CPU 902, 904, 934 Power supply monitoring IC 910 Power supply board

Claims (11)

[Claims] 1. A gaming machine capable of providing a game result value to a player as a result of playing a predetermined game, wherein the gaming machine is capable of retaining the contents immediately before the power is turned off when the power is turned on. It is possible to perform a game state return control for returning the game state based on the held data, a game device control means for controlling a game device provided for the game, and the voltage of the predetermined potential power supply decreases. Power supply monitoring means for detecting that a predetermined value has been reached, wherein the gaming device control means stores, in the storage means, fluctuation data that fluctuates in accordance with the progress of a game by detecting the power supply monitoring means. When the power is restored from the power-off state while the storage unit is holding data, the initialization process is performed based on the data held in the storage unit. UGA gaming machine and determines whether to perform processing upon return for returning the gaming state to a state before power-off. 2. The variation data held in the storage means includes at least game state data indicating a game state, and the return processing includes a game state data read processing for restoring the game state. Item 7. The gaming machine according to Item 1. 3. The gaming machine according to claim 1, wherein the held data used to determine whether to perform initialization processing or return processing is a checksum. 4. The gaming machine control means calculates a checksum when the power is turned off and causes the storage means to hold the checksum, and when the power is restored, checks the data held in the storage means by the checksum and determines whether the held data is valid. 4. The gaming machine according to claim 3, wherein a process at the time of return is performed. 5. The gaming machine according to claim 4, wherein the gaming machine control means performs an initialization process when the held data is not valid. 6. The power-off process includes a process of setting a flag indicating power-off, and the game-apparatus control means includes a flag indicating power-off when the checksum is a predetermined value when the power is restored. 6. The gaming machine according to claim 4, wherein the state of the game machine is checked, and if the flag indicates that the power is turned off, the process at the time of return is performed. 7. The gaming machine according to claim 1, wherein the power-off processing includes a processing for preventing access to the storage means. 8. A power supply monitoring means for detecting a power supply voltage drop after a predetermined period of time when the power supply monitoring means detects a voltage drop, wherein the gaming machine control means detects the power supply voltage drop from the second power supply monitoring means. 8. The gaming machine according to claim 1, wherein a system is reset in response to an input of an output. 9. A payout device for paying out at least a predetermined prize game medium, wherein the game device control means is a payout control means for performing payout control including a prize payout control, and data retained even when the power of the gaming machine is turned off. The gaming machine according to claim 1, wherein the data is data relating to a remaining amount of premium game media paid out from the payout device. 10. A payout device for renting out at least a predetermined game medium, wherein the game device control means is a payout control means for performing a payout control including a game medium lending control, and the data held even when the power of the game machine is turned off is 10. The gaming machine according to claim 1, wherein the data is data relating to a remaining amount of game media paid out from the payout device. 11. A payout device for paying out a predetermined premium game medium can also rent out a game medium, and the payout control means also executes a game medium lending control, and outputs data stored even when the power of the game machine is turned off. The gaming machine according to claim 9, further comprising data relating to the remaining amount of the rented game media paid out from the payout device.