JP2001127434A - Multilayer printed wiring board and method of production - Google Patents

Multilayer printed wiring board and method of production

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Publication number
JP2001127434A
JP2001127434A JP30330599A JP30330599A JP2001127434A JP 2001127434 A JP2001127434 A JP 2001127434A JP 30330599 A JP30330599 A JP 30330599A JP 30330599 A JP30330599 A JP 30330599A JP 2001127434 A JP2001127434 A JP 2001127434A
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JP
Japan
Prior art keywords
hole
interlayer resin
formed
resin
forming
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Granted
Application number
JP30330599A
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Japanese (ja)
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JP4832621B2 (en
Inventor
Yutaka Iwata
Yogo Kawasaki
Hiroaki Satake
博明 佐竹
豊 岩田
洋吾 川崎
Original Assignee
Ibiden Co Ltd
イビデン株式会社
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Application filed by Ibiden Co Ltd, イビデン株式会社 filed Critical Ibiden Co Ltd
Priority to JP30330599A priority Critical patent/JP4832621B2/en
Priority claimed from KR1020017008133A external-priority patent/KR100833723B1/en
Publication of JP2001127434A publication Critical patent/JP2001127434A/en
Application granted granted Critical
Publication of JP4832621B2 publication Critical patent/JP4832621B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

(57) [Problem] To provide a multilayer printed wiring board and a method of manufacturing a multilayer printed wiring board which can shorten the internal wiring length and have excellent connection reliability. SOLUTION: Core substrate 30 and lower interlayer resin insulation layer 5
The through hole 36 is formed so as to penetrate through the hole 0, and the via hole 66 is formed immediately above the through hole 36.
For this reason, the through hole 36 and the via hole 66 are linear, shortening the wiring length, and increasing the signal transmission speed. Further, since the through hole 36 and the via hole 66 connected to the solder bump 76 (conductive connection pin 78) are directly connected, the connection reliability is excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated structure in which interlayer resin insulating layers and conductive layers are alternately laminated, and build-up layers in which conductive layers are connected by via holes are formed on both surfaces of a core substrate. The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board that can be used as a package substrate on which an IC chip is mounted, and a method for manufacturing a multilayer printed wiring board.

[0002]

2. Description of the Related Art Conventionally, build-up multilayer printed wiring boards have been manufactured, for example, by the method disclosed in Japanese Patent Application Laid-Open No. Hei 9-130050. A roughened layer is formed on the surface of the conductor circuit of the printed wiring board by electroless plating or etching. Thereafter, an interlayer insulating resin is applied by a roll coater or printing, exposed, and developed to form a via hole opening for interlayer conduction, and after UV curing and main curing, an interlayer resin insulating layer is formed. Further, a catalyst such as palladium is applied to the roughened surface of the interlayer resin insulating layer which has been roughened with an acid or an oxidizing agent. Then, a thin electroless plating film is formed, a pattern is formed on the plating film with a dry film, and after thickening by electrolytic plating, the dry film is peeled off with an alkali and etched to create a conductor circuit. . By repeating this, a build-up multilayer printed wiring board is obtained.

[0003]

At present, with the increase in the frequency of IC chips, there is a demand for a multilayer printed wiring board to have a higher transmission speed. In order to respond to such a request, the present applicant has proposed Japanese Patent Application No. 10-334499. In this configuration, as shown in FIG.
A via hole 346 of the lower interlayer resin insulation layer 350 and a via hole 366 of the upper interlayer resin insulation layer 360 are disposed directly above the 36, and the length of the wiring is shortened by linearizing the wiring, thereby transmitting a signal. Speeding up.

However, it has been found that in the above-described structure, the via holes 346 of the lower interlayer resin insulating layer 350 and the via holes 366 of the upper interlayer resin insulating layer 360 are separated under heat cycle conditions. The present inventor has studied the cause, and found that the upper via hole 366 is affected by the surface shape of the lower via hole 346 and the connectivity is reduced. Furthermore, since the interlayer resin insulating layers 350 and 360 are not reinforced with a core material such as glass cloth, it is presumed that the interlayer resin insulating layers 350 and 360 are more easily peeled off in a heat cycle than a core substrate having a core material.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multi-layer printed wiring board and a multi-layer printed wiring which can shorten the internal wiring length and have excellent connection reliability. An object of the present invention is to provide a method for manufacturing a plate.

[0006]

In order to achieve the above object, in the multilayer printed wiring board according to the present invention, interlayer resin insulation layers and conductor layers are alternately laminated, and each conductor layer is connected by a via hole. The build-up layer is formed in a multilayer printed wiring board formed on both surfaces of a core substrate, forming a through hole so as to penetrate the core substrate and an interlayer resin insulating layer formed on both surfaces of the core substrate, A technical feature is that a via hole connected to an external connection terminal is formed directly above the through hole.

According to a second aspect of the present invention, in the first aspect, the through hole is filled with a filler, and a conductor layer is formed to cover an exposed surface of the filler from the through hole. A technical feature is that a via hole is formed on the conductor layer of the through hole.

[0008] Claim 3 is at least:
(D) a method of manufacturing a multilayer printed wiring board, comprising: (a) forming a lower interlayer resin insulation layer on both surfaces of a core substrate; (b) the core substrate and the lower interlayer resin insulation. Forming a through hole penetrating the layer, (c) forming an upper interlayer resin insulating layer on the lower interlayer resin insulating layer, and (d) forming a via hole in the upper interlayer resin insulating layer. Forming a via hole connected to an external connection terminal directly above a part of the through hole.

[0009] Claim 4 is at least the following (a):
(G) a method of manufacturing a multilayer printed wiring board, comprising: (a) a step of forming a lower interlayer resin insulation layer on both surfaces of a core substrate; (b) the core substrate and the lower interlayer resin insulation. Forming a through hole penetrating the layer, (c) filling the through hole with a filler, and (d) polishing the filler overflowing from the through hole to flatten it.
(E) forming a conductor layer covering the exposed surface of the filler from the through hole, (f) forming an upper interlayer resin insulation layer on the lower interlayer resin insulation layer, (g) forming the upper layer A step of forming a via hole in the interlayer resin insulating layer, the step of forming a via hole connected to an external connection terminal immediately above a part of the through hole.

In the method for manufacturing a multilayer printed wiring board according to the first aspect and the multilayer printed wiring board according to the third aspect, through holes are formed so as to penetrate the core substrate and the interlayer resin insulating layers formed on both surfaces of the core substrate. A via hole connected to an external connection terminal is formed immediately above the through hole. For this reason, the through-hole and the via-hole become linear, the wiring length is reduced, and the signal transmission speed can be increased. In addition, since the through hole and the via hole connected to the external connection terminal are directly connected, the connection reliability is excellent.

In the method for manufacturing a multilayer printed wiring board according to the present invention, a through hole is formed so as to penetrate a core substrate and an interlayer resin insulating layer formed on both surfaces of the core substrate. Then, a via hole is formed immediately above the through hole. For this reason, the through hole and the via hole become linear, shortening the wiring length,
It is possible to increase the signal transmission speed. Further, the via hole is directly connected to the via hole connected to the external connection terminal, and the via hole is formed on the conductor layer covering the filler in the through hole that has been planarized by polishing. Therefore, the connection reliability is excellent.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. In the multilayer printed wiring board 10, the build-up wiring layers 80 are formed on the front and back surfaces of the core substrate 30.
U and 80D are formed. The build-up wiring layer 8
Reference numerals 0U and 80D denote lower interlayer resin insulation layer 50 having via hole 46 formed therein, upper interlayer resin insulation layer 60 having upper via hole 66 formed therein, and upper interlayer resin insulation layer 6 having upper via hole 66 formed therein.
0 is formed of a solder resist layer 70. A solder bump (external connection terminal) 76 for connection to an IC chip (not shown) is formed in the upper via hole 66 via the opening 71 of the solder resist 70, and the lower via hole 66 is formed. Is connected to a conductive connection pin (external connection terminal) 78 for connection to a daughter board (not shown).

In this embodiment, the through holes 36 connecting the build-up wiring layers 80U and 80D are formed so as to penetrate the core substrate 30 and the lower interlayer resin insulation layer 50. The through hole 36 is filled with a resin filler 54, and a lid plating 58 is provided at the opening. Similarly, the via hole 46 formed in the lower interlayer resin insulation layer 50 is filled with a resin filler 54, and a lid plating 58 is provided in the opening.

In this embodiment, the through hole 36 is formed so as to penetrate the core substrate 30 and the lower interlayer resin insulating layer 50, and the via hole 66 is formed immediately above the through hole 36. For this reason, the through hole 36 and the via hole 66 are linear, shortening the wiring length, and increasing the signal transmission speed. Further, since the through hole 36 and the via hole 66 connected to the external connection terminal (solder bump 76, conductive connection pin 78) are directly connected, the connection reliability is excellent. In particular, in the present embodiment, after the filler 54 filled in the through hole 36 is flattened by polishing as described later, a lid plating (conductor layer) 58 that covers the filler 54 is provided, and Since the via hole 66 is formed, the smoothness of the surface of the through hole 36 is high, and the connection reliability between the through hole 36 and the via hole 66 is excellent.

Further, in the multilayer printed wiring board of the present embodiment, since the same filling resin 54 is filled in the through hole 36 and the lower via hole 46, the structure can be made inexpensive. Since the strength with the inside of the hole can be kept uniform, the reliability of the multilayer printed wiring board can be improved. Also, as described later, after the filler 54 filled in the via hole 46 is flattened by polishing, a lid plating (conductor layer) 58 covering the filler 54 is provided, and an upper via hole 66 is formed thereon. Since it is formed, the smoothness of the surface of the lower via hole 46 is high, and the connection reliability between the lower via hole 46 and the upper via hole 66 is excellent.

Further, as will be described later, in the multilayer printed wiring board of the present embodiment, in the manufacturing process, the desmearing treatment of the through hole 35 which becomes the through hole 36 and the roughening treatment of the lower interlayer resin insulating layer surface 40 are oxidized. Since it is performed simultaneously with the agent, the number of steps can be reduced and the production can be performed at low cost.

Next, a method of manufacturing the multilayer printed wiring board 10 will be described with reference to FIGS. (1) 0.8mm thick glass epoxy resin, FR4, FR
A starting material is a copper-clad laminate 30A in which 18 μm copper foils 32 are laminated on both sides of a substrate 30 made of 5, 5 or BT (bismaleimide triazine) resin (FIG. 1).
(A)). First, the copper-clad laminate is etched in a pattern to form inner layer copper patterns 34 on both sides of the substrate.
Is formed (FIG. 1B).

(2) After the substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water, an etching solution containing a cupric complex and an organic acid is allowed to act under oxygen-existing conditions such as spraying and bubbling. Then, a roughening layer 38 is provided on the surface of the inner layer copper pattern 34 by a process of forming a void by dissolving the copper conductor of the conductor circuit (FIG. 1C).
In addition, a roughening layer may be provided by an alloy of oxidation-reduction treatment or electroless plating. The formed roughened layer is
Those in the range of 0.1 to 5 μm are desirable. Within this range, peeling of the conductor circuit and the interlayer resin insulating layer hardly occurs.

The cupric complex is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole and tetrazole are preferable. Among them,
Imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2
-Phenylimidazole, 2-undecylimidazole and the like are preferred. The addition amount of the cupric complex of azoles is 1 to 15
% By weight is good. This is because they are excellent in solubility and stability.

In order to dissolve copper oxide, an organic acid is added to the cupric complex of azoles. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid,
At least one selected from the group consisting of succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid, and sulfamic acid is preferred. The content of organic acids is
0.1 to 30% by weight is preferred. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability.

The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation.

Further, in order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions, for example, fluorine ions, chlorine ions, bromine ions and the like may be added to the etching solution. In the present invention, halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because adhesion between the formed roughened surface and the interlayer resin insulating layer is excellent.

An etching solution is prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion if necessary) in water. The roughened surface according to the present invention can be formed by using a commercially available etching solution, for example, “Mech Etch Bond” manufactured by Mec Corporation.

(3) A resin film 50α to be a lower interlayer resin insulating layer is laminated on the surface of the substrate 30 by vacuum pressure lamination at a pressure of 5 kgf / cm 2 while the temperature is raised to 50 to 150 ° C. (FIG. 1). (D)). The resin film contains a hardly soluble resin, soluble resin particles, a curing agent, and other components. Each is described below.

In the resin film used in the production method of the present invention, particles soluble in an acid or an oxidizing agent (hereinafter, referred to as “soluble particles”) are contained in a resin that is hardly soluble in an acid or an oxidizing agent (hereinafter, referred to as a hardly soluble resin). It is dispersed. The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, and fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby,
Since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of a roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

(4) Subsequently, a through-hole 35 for a through hole having a diameter of 300 μm is formed in the core substrate 30 to which the resin film 50 is attached by a drill (FIG. 1E).

(5) Then, the resin film 50α has a diameter of 80 μm by carbonic acid, excimer, YAG, or UV laser.
(FIG. 2 (A)).
Thereafter, the resin film is thermally cured to form the lower interlayer resin insulation layer 50. The via hole may be formed by area processing using a laser, or by mounting a mask and performing area processing using a laser. Further, a mixed laser (which means a combination of a carbon dioxide laser and an excimer laser) may be used. Both the through hole and the via hole may be formed by laser.

(6) Chromic acid or permanganate (potassium permanganate, sodium permanganate)
At the same time, the desmear treatment of the through-holes 35 for the through holes formed in the core substrate 30 and the lower interlayer resin insulation layer 50 is performed by the oxidizing agent, and the surface of the lower interlayer resin insulation layer 50 is roughened (FIG. 2 ( B)).

In the multilayer printed wiring board of this embodiment, the core substrate 30 is made of any one of FR4, FR5 and BT resin, and the lower interlayer resin insulating layer 50 is made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin. Contains at least one of resin and fluororesin. For this reason, it becomes possible to simultaneously perform the desmear treatment of the through-hole 35 and the roughening treatment of the lower interlayer resin insulating layer 50 with an oxidizing agent composed of chromic acid and permanganate, thereby reducing the number of steps. A multilayer printed wiring board can be manufactured at low cost.

(7) A palladium catalyst is applied to the surface of the interlayer resin insulating layer 50 whose surface has been roughened, and an electroless copper plating film 42 is formed in an electroless plating aqueous solution (FIG. 2C).
Here, the electroless copper plating film is formed, but it is also possible to form a copper or nickel film by using sputtering. In addition, plasma, U
V. Corona treatment may be performed. This modifies the surface.

(8) After the substrate on which the electroless copper plating film 42 is formed is washed with water, a plating resist 43 having a predetermined pattern is formed (FIG. 2D). (9) Then, the substrate is immersed in the electrolytic plating solution, a current is passed through the electroless copper plating film 42, and the electrolytic copper plating film 44
Is formed (FIG. 2E).

(10) The plating resist 43 is peeled off with KOH, and the electroless copper plating film 42 under the plating resist is peeled off by light etching to form a via composed of the electroless copper plating film 42 and the electrolytic copper plating film 44. Hall 46
Then, a through hole 36 is formed (FIG. 3A).

(11) Via hole 46 and through hole 3
6, a roughened layer (alloy made of Cu-Ni-P) 47 is formed by electroless plating (FIG. 3B). Instead of this electroless copper plating, etching (eg, etching by spraying or immersing with a solution containing a cupric complex and an organic acid salt) or roughening layer by oxidation-reduction treatment It is also possible to form

(12) The resin filler 54 is filled in the through hole 36 and the via hole 46, and the temperature in the drying furnace is
Dry at 100 ° C. for 20 minutes (FIG. 3 (C)). In the present embodiment, since the same filler is simultaneously filled into the through hole 36 and the via hole 46, the number of manufacturing steps can be reduced. Here, the following raw material composition can be used as the resin filler. [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), SiO2 spherical particles having an average particle diameter of 1.6 μm and a surface coated with a silane coupling agent (manufactured by Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 3600-49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

(13) One surface of the substrate 30 after the processing of the above (12) is polished so as to smooth the surface of the resin filler 54 protruding from the openings of the via holes 46 and the through holes 36, Buffing is performed to remove scratches due to polishing. Such a series of polishing is similarly performed on the other surface of the substrate (FIG. 3D). Then at 100 ° C for 1
Heat treatment at 150 ° C for 1 hour for 5 hours
4 was cured. The resin that constitutes the resin filler is epoxy resin, phenol resin, fluororesin, triazine resin,
It means polyolefin resin, polyphenylene ether resin, etc., which may be thermosetting resin, thermoplastic resin, or a composite of each.The resin contains inorganic fillers such as silica and alumina to adjust the coefficient of thermal expansion. May be used. Alternatively, a paste mainly containing a conductive metal filler such as a conductive resin, gold, silver, or copper may be used. Further, each of the above complexes may be used.

(14) A palladium catalyst is applied to the surface of the interlayer resin insulating layer 50 to form an electroless copper plating film 56 in an electroless plating aqueous solution (FIG. 4A). Here, the electroless copper plating film is formed, but it is also possible to form a copper or nickel film by using sputtering.

(15) After a plating resist (not shown) having a predetermined pattern is formed, an electrolytic copper plating film 57 is formed, the plating resist is peeled off, and the electroless copper plating film 56 under the plating resist is removed. By peeling off by light etching, the electroless copper plating film 56 and the electrolytic copper plating film 5 are removed.
7 is formed at the openings of the via hole 46 and the through hole 36 (FIG. 4B).

(16) A roughening layer (Cu—Ni—) is formed on the cover plating 58 of the opening of the via hole 46 and the through hole 36.
P) 59 is formed by electroless plating (FIG. 4)
(C)). Instead of the electroless copper plating, a roughened layer can be formed by etching or oxidation-reduction treatment. (17) By repeating the above steps (3) to (11), the upper interlayer resin insulation layer 60 is formed, and the electroless copper plating film 62 and the electrolytic copper plating film are formed on the upper interlayer resin insulation layer 60. 64 are formed (FIG. 4)
(D)). (18) Subsequently, a solder resist and a solder bump are formed. The raw material composition for the solder resist is as follows.
A photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of an epoxy group of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was used.
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s is obtained. As the solder resist layer, various resins can be used. For example, bisphenol A type epoxy resin, acrylate of bisphenol A type epoxy resin, novolak type epoxy resin, acrylate of novolak type epoxy resin may be used as an amine curing agent or an imidazole curing agent. Can be used. In particular, in the case where an opening is provided in the solder resist layer to form a solder bump, a solder bump made of "novolak epoxy resin or acrylate of novolak epoxy resin" and containing "imidazole curing agent" as a curing agent is preferable. On both sides of the multilayer printed wiring board obtained in the above (17), the solder resist composition 70α
Is applied in a thickness of 20 μm (FIG. 5A).

(19) Next, after performing a drying process at 70 ° C. for 20 minutes and at 80 ° C. for 30 minutes, a circular pattern (mask pattern)
A 5 mm-thick photomask film on which is drawn is placed in close contact with the substrate, exposed to ultraviolet light at 1000 mJ / cm 2 , and subjected to DMTG development processing. And then at 80 ° C for 1 hour, at 100 ° C for 1 hour
Heat treatment is performed at 120 ° C. for 1 hour and at 150 ° C. for 3 hours to form a solder resist layer 70 (opening diameter: 200 μm) having an opening 71 (opening diameter: 200 μm) (FIG. 5).
(B)).

(20) Thereafter, the multilayer printed wiring board opening 7
The plating post 242 exposed from 1 was replaced with nickel chloride 2.3
× 10 -1 mol / l, sodium hypophosphite 2.8 × 10
-1 mol / l, sodium citrate 1.6 × 10 -1 mo
1 / l, is immersed in an electroless nickel plating solution having a pH of 4.5 and having a pH of 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, potassium potassium cyanide 7.6 × 10 −3 mol / l, ammonium chloride 1.9 × 10 3
-1 mol / l, sodium citrate 1.2 × 10 -1 mo
l / l, sodium hypophosphite 1.7 × 10 -1 mol / l
Is immersed in an electroless gold plating solution consisting of at 7.5 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (FIG. 5C). In the above-described example, the intermediate layer is made of nickel and the noble metal layer is made of gold. In addition to nickel, the intermediate layer may be made of palladium, titanium, or the like. Further, two or more noble metal layers may be formed. Dry treatment, plasma, UV, or corona treatment may be performed as the surface treatment. Thereby, the filling property of the underfill is improved.

(23) The solder resist layer 70
Solder paste is printed on the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump (solder body) 76 in the via hole 66 on the upper surface, and a solder 77 is inserted in the via hole 66 on the lower surface. Then, the conductive connection pins 78 are attached (see FIG. 6). Note that a BGA can be formed instead of the conductive connection pin.

Comparative Example As a comparative example, a multilayer printed wiring board having the same structure as the multilayer printed wiring board of the present embodiment shown in FIG. . FIG. 8 shows the evaluation results of the multilayer printed wiring board of the present embodiment and the multilayer printed wiring board of the comparative example.
Shown in

The electrical tangency was checked for continuity by a checker. If there is a short circuit or disconnection, it is NG, and if there is no, OK.
And After the heat cycle test (-65 ° C / 3 minutes + 130 ° C / 3 minutes as one cycle, the cycle was repeated 1000 times), the cross section was cut, and the peeling and swelling were observed with a microscope (× 100 to 400). Peeling and swelling of the resin insulating layer and the via hole were visually inspected.

In the comparative example, a dent not completely filled by plating was formed on the surface of the lower via hole, and the connectivity with the upper via hole was reduced. As a result, a portion that is not electrically connected between the via holes may occur. After the heat cycle test, it was confirmed that peeling and swelling occurred in the interlayer resin insulating layer due to peeling between via holes. In the multilayer printed wiring board of the present embodiment, there was no problem in the connectivity described above, and neither peeling nor swelling was confirmed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a multilayer printed wiring board according to the prior art.

FIG. 8 is a table showing evaluation results of the first embodiment and a comparative example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 30 core substrate 32 copper foil 34 conductive circuit 35 through hole 36 through hole 38 roughened layer 42 electroless copper plated film 43 resist 44 electrolytic copper plated film 46 via hole 47 roughened layer 48 conductive circuit 50 lower interlayer resin insulation layer 52 opening 54 Filled resin 56 Electroless copper plating film 57 Electroless copper plating film 58 Lid plating 59 Roughened layer 60 Upper interlayer resin insulation layer 62 Electroless copper plating film 64 Electrolytic copper plating film 66 Via hole 70 Solder resist 71 Opening 72 Nickel Plating layer 74 Gold plating layer 76 Solder bump 77 Solder 78 Conductive connection pin 80U, 80D Build-up wiring layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yutaka Iwata 300 Aoyagi-cho, Ogaki-shi, Gifu IBIDEN Corporation Aoyagi Plant F-term (reference) 5E317 AA04 AA24 BB02 BB12 CC32 CC33 CD01 CD05 CD12 CD15 CD18 CD23 CD25 CD27 CD32 CD40 GG03 GG11 GG17 5E346 AA42 AA43 DD23 DD24 EE18 EE19 EE38 EE39 FF07 FF15 FF18 FF19 FF23 FF33 FF34 GG15 GG17 GG27 GG28

Claims (4)

[Claims]
1. A multilayer printed wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated, and build-up layers in which respective conductor layers are connected by via holes are formed on both surfaces of a core substrate. A through hole is formed so as to penetrate the core substrate and an interlayer resin insulating layer formed on both surfaces of the core substrate, and a via hole connected to an external connection terminal is formed immediately above the through hole. Multi-layer printed wiring board.
2. A filler is filled in the through hole, a conductor layer is formed to cover an exposed surface of the filler from the through hole, and a via hole immediately above the through hole is formed in the through hole of the through hole. 2. The multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board is formed on the conductor layer.
3. A method for manufacturing a multilayer printed wiring board, comprising at least the following steps (a) to (d): (a) forming a lower interlayer resin insulating layer on both surfaces of a core substrate; b) forming a through hole penetrating the core substrate and the lower interlayer resin insulating layer; (c) forming an upper interlayer resin insulating layer on the lower interlayer resin insulating layer; and (d) forming the upper interlayer resin insulating layer. A step of forming a via hole in the resin insulating layer, the step of forming a via hole connected to an external connection terminal immediately above a part of the through hole.
4. A method for manufacturing a multilayer printed wiring board, comprising at least the following steps (a) to (g): (a) forming a lower interlayer resin insulating layer on both surfaces of a core substrate; b) a step of forming a through hole penetrating the core substrate and the lower interlayer resin insulation layer; (c) a step of filling the through hole with a filler; and (d) polishing the filler overflowing from the through hole. Flattening process,
(E) forming a conductor layer covering the exposed surface of the filler from the through hole, (f) forming an upper interlayer resin insulation layer on the lower interlayer resin insulation layer, (g) forming the upper layer A step of forming a via hole in the interlayer resin insulating layer, the step of forming a via hole connected to an external connection terminal immediately above a part of the through hole.
JP30330599A 1999-10-26 1999-10-26 Multilayer printed wiring board Expired - Lifetime JP4832621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30330599A JP4832621B2 (en) 1999-10-26 1999-10-26 Multilayer printed wiring board

Applications Claiming Priority (20)

Application Number Priority Date Filing Date Title
JP30330599A JP4832621B2 (en) 1999-10-26 1999-10-26 Multilayer printed wiring board
KR1020017008133A KR100833723B1 (en) 1999-10-26 2000-10-10 Multi-layer printed circuit board and metheod of manufacturing multi-layer printed circuit board
EP00964763A EP1162867B1 (en) 1999-10-26 2000-10-10 Multilayer printed wiring board and method of producing multilayer printed wiring board
CN2006101001609A CN1909763B (en) 1999-10-26 2000-10-10 Multi-layer printed circuit board
CNB008023913A CN1199536C (en) 1999-10-26 2000-10-10 Multilayer printed wiring board and method of producing multilayer printed wiring board
CNB2005100526249A CN100521868C (en) 1999-10-26 2000-10-10 Multilayer printed wiring board and method of producing multilayer printed wiring board
CN2006101001596A CN1909762B (en) 1999-10-26 2000-10-10 Multi-layer printed circuit board
PCT/JP2000/007037 WO2001031984A1 (en) 1999-10-26 2000-10-10 Multilayer printed wiring board and method of producing multilayer printed wiring board
DE60027141T DE60027141T2 (en) 1999-10-26 2000-10-10 Printed multilayer plate and manufacturing method for printed multilayer plate
CN2006101001717A CN1909764B (en) 1999-10-26 2000-10-10 Multi-layer printed circuit board
EP06003111A EP1672970B1 (en) 1999-10-26 2000-10-10 Multi-layer printed circuit board and method of manufacturing multi-layered printed circuit board
US09/830,963 US6930258B1 (en) 1999-10-26 2000-10-20 Multilayer printed wiring board and method of producing multilayer printed wiring board
TW089122342A TWI252723B (en) 1999-10-26 2000-10-24 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
MYPI20005015A MY129285A (en) 1999-10-26 2000-10-25 "multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board"
MYPI20051618A MY148600A (en) 1999-10-26 2000-10-25 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US11/106,642 US7178234B2 (en) 1999-10-26 2005-04-15 Method of manufacturing multi-layer printed circuit board
US11/333,228 US7795542B2 (en) 1999-10-26 2006-01-18 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US12/179,201 US7999194B2 (en) 1999-10-26 2008-07-24 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US12/560,208 US8106310B2 (en) 1999-10-26 2009-09-15 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US13/307,213 US8822839B2 (en) 1999-10-26 2011-11-30 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board

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CN106898594A (en) * 2017-02-28 2017-06-27 美的智慧家居科技有限公司 Substrate for wireless fidelity systems level encapsulation chip and forming method thereof

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Publication number Publication date
CN1909764A (en) 2007-02-07
CN1909762A (en) 2007-02-07
CN1909764B (en) 2010-11-10
CN1909763A (en) 2007-02-07
JP4832621B2 (en) 2011-12-07
CN1909762B (en) 2012-05-30
CN1909763B (en) 2010-11-10

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