JP2001102926A - アナログ・デジタル変換器の動的要素不整合ノイズ・シェイピング法 - Google Patents
アナログ・デジタル変換器の動的要素不整合ノイズ・シェイピング法Info
- Publication number
- JP2001102926A JP2001102926A JP2000271419A JP2000271419A JP2001102926A JP 2001102926 A JP2001102926 A JP 2001102926A JP 2000271419 A JP2000271419 A JP 2000271419A JP 2000271419 A JP2000271419 A JP 2000271419A JP 2001102926 A JP2001102926 A JP 2001102926A
- Authority
- JP
- Japan
- Prior art keywords
- capacitors
- capacitor
- digital
- analog
- voltage level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 100
- 238000007493 shaping process Methods 0.000 title description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 332
- 238000005070 sampling Methods 0.000 claims abstract description 112
- SEIGJEJVIMIXIU-UHFFFAOYSA-J aluminum;sodium;carbonate;dihydroxide Chemical compound [Na+].O[Al+]O.[O-]C([O-])=O SEIGJEJVIMIXIU-UHFFFAOYSA-J 0.000 claims abstract 2
- 230000003595 spectral effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 21
- 230000003321 amplification Effects 0.000 description 12
- 238000003199 nucleic acid amplification method Methods 0.000 description 12
- 238000012546 transfer Methods 0.000 description 12
- 238000012935 Averaging Methods 0.000 description 5
- 230000001351 cycling effect Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 2
- 102100029203 F-box only protein 8 Human genes 0.000 description 1
- 101100334493 Homo sapiens FBXO8 gene Proteins 0.000 description 1
- 101100194362 Schizosaccharomyces pombe (strain 972 / ATCC 24843) res1 gene Proteins 0.000 description 1
- 101100194363 Schizosaccharomyces pombe (strain 972 / ATCC 24843) res2 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
- H03M1/0668—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging the selection being based on the output of noise shaping circuits for each element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
- H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/392,138 US6211805B1 (en) | 1999-09-08 | 1999-09-08 | Noise shaping dynamic element mismatch in analog to digital converters |
| US392138 | 1999-09-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001102926A true JP2001102926A (ja) | 2001-04-13 |
| JP2001102926A5 JP2001102926A5 (enExample) | 2007-10-25 |
Family
ID=23549396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000271419A Abandoned JP2001102926A (ja) | 1999-09-08 | 2000-09-07 | アナログ・デジタル変換器の動的要素不整合ノイズ・シェイピング法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6211805B1 (enExample) |
| EP (1) | EP1083661A3 (enExample) |
| JP (1) | JP2001102926A (enExample) |
| KR (1) | KR100730277B1 (enExample) |
| TW (1) | TW494641B (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6885326B2 (en) * | 1999-02-04 | 2005-04-26 | Med-El Elektromedizinische Geraeta Gmbh | Accumulator for adaptive Σ-Δ modulation |
| WO2001031793A1 (en) * | 1999-10-27 | 2001-05-03 | Koninklijke Philips Electronics N.V. | A digital to analog converter |
| US6734818B2 (en) * | 2000-02-22 | 2004-05-11 | The Regents Of The University Of California | Digital cancellation of D/A converter noise in pipelined A/D converters |
| US6346898B1 (en) * | 2000-08-07 | 2002-02-12 | Audio Logic, Inc. | Multilevel analog to digital data converter having dynamic element matching in a reference data path |
| IT1320694B1 (it) * | 2000-10-06 | 2003-12-10 | St Microelectronics Srl | Metodo di equalizzazione dinamica degli elementi di un convertitoredigitale/analogico multibit integrato con uscita bilanciata per |
| US6617992B2 (en) | 2001-08-15 | 2003-09-09 | National Semiconductor Corporation | Capacitor mismatch independent gain stage for differential pipeline analog to digital converters |
| US6600440B1 (en) | 2001-08-15 | 2003-07-29 | National Semiconductor Corporation | Capacitor mismatch independent gain stage for pipeline analog to digital converters |
| KR100500440B1 (ko) * | 2002-10-15 | 2005-07-12 | 삼성전자주식회사 | 파이프라인 구조를 갖는 다단 ａ/ｄ 컨버터 및 그것을설계하기 위한 코딩 방법 |
| US7193548B2 (en) * | 2004-01-30 | 2007-03-20 | Hrl Laboratories, Llc | Switching arrangement and DAC mismatch shaper using the same |
| US7187310B2 (en) * | 2005-03-04 | 2007-03-06 | Kamal El-Sankary | Circuit calibration using voltage injection |
| TWI304686B (en) * | 2006-01-06 | 2008-12-21 | Realtek Semiconductor Corp | Pipeline analog-to-digital converter capable of sharing comparators |
| US10003348B2 (en) * | 2016-09-08 | 2018-06-19 | Mediatek Inc. | Analog-to-digital converter with noise shaping |
| CN114050828B (zh) * | 2022-01-07 | 2022-04-12 | 武汉杰开科技有限公司 | 一种数模转换器、数模转换器的失配校准方法及芯片 |
| US12451895B2 (en) | 2022-10-28 | 2025-10-21 | Kepler Computing Inc. | Mismatch shaping apparatus and method for binary coded digital-to-analog converters |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9224238D0 (en) | 1992-11-19 | 1993-01-06 | Vlsi Technology Inc | Pipelined analog to digital converters and interstage amplifiers for such converters |
| US5412387A (en) | 1993-04-06 | 1995-05-02 | Analog Devices, Inc. | Error reduction in switched capacitor digital-to-analog converter systems by balanced sampling |
| US5404142A (en) | 1993-08-05 | 1995-04-04 | Analog Devices, Incorporated | Data-directed scrambler for multi-bit noise shaping D/A converters |
| US5416485A (en) | 1993-12-20 | 1995-05-16 | Lee; Hae-Seung | Analog-to-digital conversion circuit with improved differential linearity |
| US6031480A (en) * | 1997-11-04 | 2000-02-29 | Texas Instruments Incorporated | Method and apparatus for implementing a pipelined A/D converter with inter-stage amplifiers having no common mode feedback circuitry |
-
1999
- 1999-09-08 US US09/392,138 patent/US6211805B1/en not_active Expired - Lifetime
-
2000
- 2000-09-06 EP EP00119317A patent/EP1083661A3/en not_active Withdrawn
- 2000-09-07 JP JP2000271419A patent/JP2001102926A/ja not_active Abandoned
- 2000-09-08 KR KR1020000053292A patent/KR100730277B1/ko not_active Expired - Fee Related
- 2000-09-26 TW TW089118385A patent/TW494641B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100730277B1 (ko) | 2007-06-19 |
| EP1083661A2 (en) | 2001-03-14 |
| US6211805B1 (en) | 2001-04-03 |
| KR20010030325A (ko) | 2001-04-16 |
| EP1083661A3 (en) | 2003-09-03 |
| TW494641B (en) | 2002-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070907 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070907 |
|
| A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20081209 |