JP2001092869A - Device and method for synthesizing and verifying logic and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the man-hour required for synthesizing and verifying a plurality of net lists from logical descriptions. SOLUTION: A means 1 generates a net list B from a logical description A and a means 2 verifies the consistency between the description A and list B. Means 3 and 4 generate net lists DI, etc., corresponding to different signal names, and logical descriptions F1, etc., by converting the signal names in the list B and description A in accordance with a signal name corresponding card file C in which different signal names are arranged correspondingly to the signal names in the list B. A means 5 detects the difference in signal name between the net list B and net lists DI, etc., and outputs a net list signal name difference file E in which the signal names are arranged. A means 6 detects the difference in signal name between the logical description A and logical descriptions F1, etc., and outputs a logical description signal name difference file G in which the signal names are arranged. A means 7 verifies the consistency between the files E and G.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis / verification system in an LSI design using a plurality of general-purpose logic macros (netlists), and more particularly, to creating a plurality of netlists from one type of logic description. The present invention relates to a logic verification system for verifying consistency between a logic description and each netlist.

[0002]

2. Description of the Related Art In the design of an integrated circuit, as is well known, a text description in which logic circuit information is described in a hardware description language (HDL) (hereinafter referred to as "logic description").
Then, a netlist expressing the connection relation of the circuits in units of gate-level circuit elements is generated by logic synthesis. In particular, in an LSI, there are often a plurality of logic circuits having different signals but performing the same logical operation. In this case, a plurality of netlists having different signal names are generated from one type of logic description. Therefore, logic verification for verifying the consistency between the logic description and each netlist is an important task.

FIG. 14 shows an example of a conventional logic synthesis / verification system for performing such logic synthesis / verification. In FIG. 14, first, a plurality of base logical descriptions a are copied to obtain a plurality of logical descriptions a1, a2,. Next, each of the logical descriptions a1, a2,... Is converted into a different signal name by the signal name conversion means 30. Thus, a plurality of logic descriptions a11, a21,... Having the same logic as the base logic description a but different signal names can be created. Next, for each of the base logical description a and the logical descriptions a11, a21,.
Logic synthesis is performed by the logic synthesis means 10 to create netlists b, b1, b2,. Finally, the logic verifying means 20 assigns each of the logic descriptions a, a11, a21. Verification of consistency with b1, b2,.

That is, this logic synthesis / verification system creates a plurality of logic descriptions and a plurality of netlists from one type of logic description, and verifies the consistency between the corresponding logic description and the netlist a plurality of times. Is what you do.

[0005]

However, in the above-described conventional logic synthesis / verification system, a plurality of logic descriptions composed of the same logic and having different signal names are created, and a netlist is created for each logic description. Since it is necessary to perform the logic synthesis work a plurality of times for the creation, there is a first problem that the number of steps of the logic synthesis work increases.

In addition, since the logic verification between the plurality of logic descriptions and the netlists corresponding to the respective logic descriptions must be performed a plurality of times, the number of steps of the logic verification work increases. There is a second problem.

Further, since there are a plurality of logic descriptions having the same logic but different signal names, if the logic is changed, it is necessary to correct a plurality of logic description languages. There is a third problem that the possibility of a correction error due to manual intervention increases.

An object of the present invention is to provide a logic synthesis system in which the number of steps of a logic synthesis operation for creating a plurality of netlists from one type of logic description is reduced.

It is another object of the present invention to provide a logic verification system in which the number of steps of a logic verification operation for verifying the consistency between one type of logic description and a plurality of netlists is reduced.

[0010]

According to a first aspect of the present invention, there is provided a logic synthesizing apparatus for creating a plurality of netlists having different signal names from one kind of logical description, wherein the netlist is created from the logical description. Logic synthesizing means, and converting the signal names in the netlist in accordance with a signal name correspondence card file listing the different signal names in correspondence with the signal names in the netlist, thereby obtaining the nets corresponding to the different signal names. A netlist signal name conversion processing means for creating a list is provided.

According to a second aspect of the present invention, there is provided a logic verifying apparatus for creating a plurality of netlists having different signal names from one kind of logical description and performing logic verification of the created netlist. Logic synthesizing means for creating a net list from the logic list, logic verifying means for verifying consistency between the logic description and the net list, and signal names listing the different signal names corresponding to the signal names in the net list Netlist signal name conversion processing means for creating a netlist corresponding to the different signal names by converting signal names in the netlist according to the corresponding card file; and By converting the signal names in the logical description according to the signal name correspondence card file listing the signal names, it is possible to handle the different signal names. Logic description signal name conversion processing means for creating a logic description, detecting a difference in signal name between the netlist created from the logic description and the netlist after the signal name conversion, and listing the signal names Netlist signal name verification means for outputting a netlist signal name difference file, and a logic which detects a difference in signal name between the logical description and the logical description after the signal name conversion, and lists the signal names. Logic description signal name verification means for outputting a description signal name difference file; and signal name difference file verification means for verifying consistency between the netlist signal name difference file and the logic description signal name difference file. It is characterized by the following.

According to a first aspect of the present invention, there is provided a logic synthesis method for creating a plurality of netlists having different signal names from one type of logic description, wherein the logic synthesis procedure creates a netlist from the logic description. A netlist for creating the netlist corresponding to the different signal names by converting the signal names in the netlist according to a signal name correspondence card file listing the different signal names corresponding to the signal names in the netlist. And a signal name conversion processing procedure.

According to a second aspect of the present invention, in the logic verifying method for creating a plurality of netlists having different signal names from one kind of logical description and performing logic verification of the created netlist, A logic synthesis procedure for creating a netlist from the above, a logic verification procedure for verifying consistency between the logic description and the netlist, and a signal name listing the different signal names corresponding to the signal name in the netlist. A netlist signal name conversion processing procedure for creating a netlist corresponding to the different signal names by converting the signal names in the netlist according to the corresponding card file; and By converting the signal names in the logical description according to the signal name correspondence card file listing the signal names, it is possible to handle the different signal names. A logic description signal name conversion procedure for creating a logic description, and detecting a difference in signal name between the netlist created from the logic description and the netlist after the signal name conversion, and listing the signal names. A netlist signal name verifying procedure for outputting the netlist signal name difference file, and detecting a difference in signal names between the logical description and the converted logical description, and listing the signal names. A logic description signal name verification procedure for outputting a description signal name difference file; and a signal name difference file verification procedure for verifying consistency between the netlist signal name difference file and the logic description signal name difference file. It is characterized by.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a logic synthesis / verification system according to an embodiment of the present invention. In the present embodiment, the logic synthesizing unit 1 performs the logic synthesizing operation only once for one type of the logical description A,
.. Are generated, and the netlist signal name conversion processing means 3 converts the signal names of the netlist B to generate a plurality of netlists D1, D2,. Also,
The logical description signal name conversion processing means 4 converts the signal name of the logical description A to create a plurality of logical descriptions F1, F2,.

The logic verification means 2 performs the logic verification only once between the logic description A and the netlist B. And after that,
The netlist signal name verification processing means 5 detects a netlist signal name difference between the netlist B and the netlists D1, D2,. .., And finally, the signal name difference file verification processing means 7 checks the consistency between the netlist signal name difference and the logical description signal name difference. Verify.

First, each input / output file will be described. The logic description A is a text description in which logic circuit information is described in HDL, and is an input file to be input to the logic synthesis unit 1. The netlist B is a file created by the logic synthesizing unit 1, and is a list expressing the connection relation of the logic circuits in units of gate-level circuit elements. The signal name correspondence card file C is a file listing correspondences between signal names described in the logical description A input to the logical synthesizing means 1 and converted signal names. The netlists D1, D2,... Are files created by the netlist signal name conversion processing means 5 by converting the signals of the netlist B using the signal name correspondence card file C. The logical descriptions F1, F2,... Are files created by the signal name corresponding card file C by the logical description signal name conversion processing means 4. The netlist signal name difference file E is
This is a file created by the netlist signal name verification processing means 5 and listing the differences in signal names between the netlist B and the netlists D1, D2,. The logic description signal name difference file G is stored in the logic description signal name verification processing unit 6.
Is a file listing differences in signal names between the logical description A and the logical descriptions F1, F2,...

Next, an outline of the function of each means will be described. The logic synthesis means 1 inputs a logic description A and outputs a netlist B. The logic verification means inputs the netlist B and the logic description A, and performs logic verification on the consistency between the two. The logic synthesizing means 1 and the logic verifying means 2 are the same as those in the prior art.

The netlist signal name conversion processing means 3 inputs a signal name corresponding card file C and a netlist B, and converts a plurality of netlists D1, D2,.
・ ・ Is output. Logic synthesis processing signal name conversion processing means 4
Are a plurality of logical descriptions F1, F2,... Obtained by inputting a signal name corresponding card file C and a logical description A and converting the signal names.
Is output. The netlist signal name verification processing means 5 inputs the netlist B after the logic synthesis and the plurality of netlists D1, D2,... After the netlist signal name conversion processing, and lists different signal names between the two. Then, the output netlist signal name difference file E is output. The logical description signal name verification processing means 6 receives the logical description A and a plurality of logical descriptions F1, F2,... After the logical description signal name conversion processing, and lists the logical description signals having different signal names between the two. Output the misnamed file G. The signal name difference file verification processing means 7
A netlist signal name difference file E and a logic description language signal name difference file G are input, and a difference in signal names listed between the two is detected to verify the signal name difference file.

Next, the netlist signal name conversion processing means 3
Will be described in detail with reference to the flowchart of FIG.

The netlist in FIG. 2 is the netlist B output from the logic synthesizing means 1, and the card file indicates the signal corresponding card file C. The netlist signal name conversion process is a process of reading the first row of the netlist output by the logic synthesis means 1 (step S in FIG. 2).
1) Processing for reading the first line of the card file (step S2), and checking whether the signal name described in the line of the read netlist and the signal name defined in the line of the read card file are the same. Determining process (step S3),
Processing for determining whether the line read from the card file is the last line of the card file (step S4), processing for converting the signal name of the read netlist line into the card file signal name and outputting it to a new netlist (Step S5), the process of reading the next line of the card file (Step S6), the process of outputting the read netlist line to a new netlist (Step S7), and the line read from the netlist is the last line of the netlist. (Step S8) and a process of reading the next line of the netlist (step S9).

Next, the processing procedure will be described. First, the process of reading the first line of the netlist (step S1)
I do. In the process of reading the first line of the netlist (step S1), the first line (first line) of the netlist B to be input to the netlist signal name conversion processing means 3 is read.
Then, the process proceeds to a process of reading the first line of the card file (step S2). In the process of reading the first line of the card file (step S2), the first line (first line) of the card file C to be input to the netlist signal name conversion processing means 3 is read. Then, the process proceeds to a process of determining whether the signal name described in the line of the read netlist and the signal name defined in the line of the read card file are the same (step S3).

Processing for determining whether the signal name described in the line of the read netlist is the same as the signal name defined in the line of the read card file (step S)
In 3), if the signal name described in the line of the read netlist B is the same as the signal name defined in the line of the read card file C, the read netlist B
The process proceeds to the process of converting the signal names in the row of (2) into the signal names of the card file C and outputting the signal names to the new netlist (step S5). If the signal names defined in the lines of the file C are not the same, the process proceeds to a process of determining whether the line read from the card file is the last line of the card file (step S4).

Processing for determining whether the line read from the card file is the last line of the card file (step S
In 4), if the line read from the card file C is the last line of the card file C, the process proceeds to a process of outputting the read netlist line to a new netlist (step S7). If the read line is not the last line of the card file C, the process proceeds to a process of reading the next line of the card file (step S6).

In the process of converting the read signal name of the line of the netlist into the signal name of the card file and outputting it to a new netlist (step S5), the signal name description portion of the read line of the netlist B is converted into a card file. Are converted into signal names corresponding to the signal names defined in the line read by C and output to new netlists D1, D2,... Then, a process of determining whether the line read from the netlist is the last line of the netlist (step S
Go to 8).

In the process of reading the next line of the card file (step S6), the next line of the currently read card file C is read. Then, the process proceeds to a process of determining whether the signal name described in the line of the read netlist and the signal name defined in the line of the read card file are the same (step S3).

In the process of outputting the read netlist rows to the new netlist (step S7), the signal names of the read netlist C rows are not converted, but are output to the new netlists D1, D2,. I do.
Then, the process proceeds to a process of determining whether the line read from the netlist is the last line of the netlist (step S8).

Processing for determining whether the line read from the netlist is the last line of the netlist (step S8)
Then, if the line read from the netlist B is the last line of the netlist B, the process is terminated. On the other hand, if the line read from the netlist B is not the last line of the netlist B, The process proceeds to the process of reading the row (step S9).

In the process of reading the next line of the netlist (step S9), the next line of the currently read netlist B is read. Then, the process proceeds to a process of reading the first line of the card file (step S2).

As a result, new netlists D1, D2,... Obtained by converting the signal names of the netlist B by the card file C corresponding to the signal names are obtained. The number of the new netlists D1, D2,... Depends on the number of signal names associated with the signal names of the netlist B in the signal name correspondence card file C.

Next, the operation of the logic description signal name conversion means 4 will be described in detail with reference to the flowchart of FIG. FIG.
In FIG. 2, "Netlist" means "Logical Description".
And the flow itself is the same.

In FIG. 3, the logical description is a logical description A which is an input to the logical synthesizing means 1, and the card file indicates a signal corresponding card file C. The logic description signal name conversion process is a process of reading the first line of the logic description to be input to the logic synthesis means 1 (step S10 in FIG. 3), a process of reading the first line of the card file (step S11), and Processing to determine whether the signal name described in the logical description line is the same as the signal name defined in the read card file line (step S12), and the line read from the card file is the last of the card file (Step S13), the signal names of the read lines of the logical description language are converted into the signal names of the card file and output to new logical descriptions F1, F2,... (Step S14). , The process of reading the next line of the card file (step S15), the process of outputting the line of the read logical description to new logical descriptions F1, F2,.
6), a process of determining whether the line read from the logical description is the last line of the logical description (step S17), and a process of reading the next line of the logical description (step S18).

Next, the processing procedure will be described. First, a process of reading the first line of the logical description (step S10) is performed. Processing for reading the first line of the logical description (step S1
In 0), the first line (first line) of the logical description A to be input to the logical description signal name conversion means 4 is read. Then, the process proceeds to a process of reading the first line of the card file (step S11). Processing to read the first line of the card file (step S
In 11), the first line (first line) of the card file C to be input to the logical description name conversion processing means 4 is read. Then, the process proceeds to a process of determining whether the signal name described in the read line of the logic description language is the same as the signal name defined in the read line of the card file (step S12).

Processing to determine whether the signal name described in the read logical description line is the same as the signal name defined in the read card file line (step S12)
In the case where the signal name described in the line of the read logical description A is the same as the signal name defined in the line of the read card file C, the signal name in the line of the read logical description A The process proceeds to a process of converting the signal name into a signal name of C and outputting it to a new logic description language (step S14).
If the signal name described in the line of the read logical description A is not the same as the signal name defined in the line of the read card file, it is determined whether the line read from the card file is the last line of the card file. The process proceeds to the determining process (step S13).

Processing for determining whether the line read from the card file is the last line of the card file (step S
In 13), when the line read from the card file C is the last line of the card file C, the process of outputting the read line of the logical description to a new logical description (step S1)
6). On the other hand, if the line read from the card file C is not the last line of the card file C, the process proceeds to a process of reading the next line of the card file (step S15).

In the process of converting the read signal name of the logical description into a signal name of the card file and outputting it as a new logical description (step S14), the signal name description portion of the read logical description A is converted to the card file. Are converted into signal names corresponding to the signal names defined in the line read by C and output to new logical descriptions F1, F2,. Then, the process proceeds to a process of determining whether the line read from the logical description is the last line of the logical description (step S17).

In the process of reading the next line of the card file (step S15), the currently read card file C is read.
Read the next line of Then, the process proceeds to a process of determining whether the signal name described in the read logical description line and the signal name defined in the read card file line are the same (step S12).

In the process of outputting the read logical description line to the new logical description (step S16), the signal names of the read logical description A line are not converted, but are output to new logical descriptions F1, F2,. I do. Then, the process proceeds to a process of determining whether the line read from the logical description is the last line of the logical description (step S17).

In the process of determining whether the line read from the logical description is the last line of the logical description (step S17),
If the line read from the logical description A is the last line of the logical description A, the process ends. On the other hand, if the line read from the logical description A is not the last line of the logical description A, The process proceeds to a process of reading a row (step S18).

Processing for reading the next line of the logical description (step S
In step 18), the next line of the logical description A being read is read. Then, the process proceeds to a process of reading the first line of the card file (step S11).

As a result, new logical descriptions F1, F2,... Obtained by converting the signal names of the logical description A by the card file C corresponding to the signal names are obtained. Note that a new logical description F
The number of 1, F2... Depends on the number of signal names associated with the signal of the logical description A in the signal name corresponding card file C.

Next, the netlist signal name verification processing means 5
Will be described in detail with reference to the flowchart of FIG.

4 are the netlist B output from the logic synthesis means 1 and the netlists D1 and D output from the net signal name conversion processing means 3.
2 and so on. This netlist signal name verification process
Processing for reading the first line of all netlists (step S1
9), a process of determining whether the signal names of all netlists are the same (step S20), a process of listing and outputting the signal names (step S21), and determining whether the line read from the netlist is the last line (Step S22) and the process of reading the next line of the all list (step S2)
3).

Next, the processing procedure will be described. First, the process of reading the first line of all netlists (step S
19) is performed. In the process of reading the first line of the entire netlist (step S19), the first line (first line) is read from the entire netlist. Then, the process proceeds to a process of determining whether the signal names described in the lines read from all netlists are the same (step S20). In the process of determining whether the signal names described in the lines read from the all netlists are the same (step S20), it is determined whether the signal names described in the lines read from the all netlists are the same. I do. If the signal names are the same, the process proceeds to a step of determining whether the line read from all netlists is the last line (step S22). If the signal names are not the same, the signal names are listed. Output (step S
Move on to 21).

In the process of enumerating and outputting signal names (step S21), signal name description portions of rows read from all netlists are enumerated and output. Then, the process proceeds to a process of determining whether the line read from the entire netlist is the last line of the netlist (step S22).

In the process of determining whether the line read from the all netlist is the last line (step S22), it is determined whether the line read from the all netlist is the last line. If it is the last line, the process ends. On the other hand, if it is not the last line, the process proceeds to a process of reading the next line of the entire netlist (step S23).

In the process of reading the next line of the all netlist (step S23), the next line of the currently read all netlist is read. Then, the process proceeds to a process of determining whether the signal names described in the lines read from all netlists are the same (step S20).

Next, the operation of the logic description signal name verification processing means 6 will be described in detail with reference to the flowchart of FIG. FIG.
In FIG. 4, "all netlists" is replaced with "all logical descriptions", and the flow itself is the same.

All the logical descriptions in FIG. 5 are a logical description A input to the logical synthesizing means 1 and logical descriptions F1, F2... Output from the logical description signal name conversion processing means 6. The logic description signal name verification process reads the first line of all logic descriptions (step S24), determines whether the signal names of all logic descriptions are the same (step S25), lists and outputs the signal names (Step S26), a process of determining whether the line read from the entire logical description is the last line (step S27), and a process of reading the next line of the entire logical description (step S28).

Next, processing means will be described. First, a process of reading the first line of the entire logical description (step S2)
Perform 4). In the process of reading the first line of the entire logical description (step S24), the first line (first line) is read from the entire logical description. Then, it is determined whether or not the signal names described in the lines read from all the logical descriptions are the same (Step S).
Move to 25). Processing to determine whether the signal names described in the lines read from all logical descriptions are the same (step S
In 25), it is determined whether or not the signal names described in the lines read from all the logical descriptions are the same. If the signal names are the same, the process proceeds to a step of determining whether the line read from all the logical descriptions is the last line (step S27). If the signal names are not the same, the signal names are listed and output. Then, the process proceeds to step S26.

In the process of listing and outputting signal names (step S26), signal name description portions are listed and output from all logical descriptions. Then, the process proceeds to a process of determining whether the line read from the entire logical description is the last line (step S28).

In the process of determining whether the line read from all logical descriptions is the last line (step S27), it is determined whether the line read from all logical descriptions is the last line. If it is the last line, this process ends. On the other hand, if it is not the last line, the process reads the next line of the entire logical description (step S28).
Move on to

In the process of reading the next line of the entire logical description (step S28), the next line of the currently read logical description is read. Then, the process proceeds to a process of determining whether the signal names described in the lines read from all the logical descriptions are the same (step S25).

Next, the operation of the netlist signal name difference file verification processing means 7 will be described in detail with reference to the flowchart of FIG.

In the signal name difference file verification process, the first line of the netlist signal name difference file is read (step S29), and the first line of the logical description signal name difference file is read (step S30). Processing to determine whether the lines have the same content (step S31), processing to determine whether the line read from the file with the different logical description signal name is the last line (step S32), processing to output an error message (step S33), difference in the logical description signal name The process of reading the next line of the file (Step S34), the process of determining whether the line read from the netlist signal name difference file is the last line (Step S35), and the process of reading the next line of the netlist signal name difference file (Step S36) ).

Next, the processing procedure will be described. First, a process of reading the first line of the netlist signal name difference file (step S29) is performed. In the process of reading the first line of the netlist signal name file (step S29), the first line (1
Line). Then, the process proceeds to the process of reading the first line of the logical description signal name file (step S30). In the process of reading the first line of the logical description signal difference file (step S30), the first line (first line) of the logical description signal difference file G is read, and it is determined whether the read lines have the same contents. Move to (Step S31).

In the process of determining whether the read lines have the same contents (step S31), it is determined whether the read lines have the same contents. If the read lines are the same, the process proceeds to a step of determining whether the line read from the netlist signal name difference file E is the last line (step S35). If the read lines are not the same, the logical description signal name difference file G is used. Processing to judge whether the read line is the last line (step S32)
Move on to

In the process of determining whether the line read from the logical description signal name difference file is the last line (step S32),
If the line read from the logical description signal name difference file G is the last line, the process proceeds to the process of outputting an error message (step S33). If not, the process reads the next line of the logical description language signal name file (step S33). Move to S34).

In the process of outputting an error message (step S33), an error is output, and the process proceeds to a process of determining whether the line read from the netlist signal name file is the last line (step S35). In the process of reading the next line of the logical description signal name difference file (step S34), the process proceeds to the process of reading the next line from the logical description signal name file difference and determining whether the read lines have the same content (step S31).

In the process of judging whether the line read from the netlist signal name difference file is the last line (step S35), if the line read from the netlist signal name difference file E is the last line, the process is terminated. If not, the process proceeds to the process of reading the next line of the netlist signal name difference file (step S36).

In the process of reading the next line of the netlist signal name difference file (step S36), the next line is read from the netlist signal name difference and the first line of the logical description signal name file is read (step S30). Move to).

Next, the logic synthesis and verification according to the present invention will be described with reference to specific examples. FIG. 7 shows a specific example of a logical description A for a signal name A describing logical circuit information, in which a logical AND operation of the signals AA1 and AA2 is performed to obtain a signal AA3. FIG. 8 shows a netlist B after logic synthesis by the logic synthesis means 1 with respect to the logic description A. The logic is AND, and the input terminal 1 has a signal AA.
1, input terminal 2 has signal A2, and output terminal has signal AA3.
Are connected, which represents a circuit connection relationship. FIG. 9 shows a specific example of the signal name corresponding card file C used in this example. In FIG. 9, three signal names BBB, CCC and DDD are listed as signal names corresponding to the signal name AAA. Therefore, the signals AA1, AA
2 and AA3, the signals BB1 and B
B2, BB3, and the signal name CCC, the signals CC1, CC2,
CC3, signal name DDD, signals DD1, DD2, DD3
Correspond to each other.

As shown in FIG. 2, the netlist signal conversion processing means 3 first reads the first line "DID AAA" of the netlist B (FIG. 8) (step S2).
1) Read the first line "AAA;BBB;CCC;DDD;" of the signal name corresponding card file C (FIG. 9) (step S2). The signal name of the netlist B is compared with the signal name of the card file C corresponding to the signal name (step S3). As a result, since the signal name AAA is defined and coincides with both, the signal name AAA is changed to the signal name BBB. The converted netlist D1 (FIG. 10 (1)) and the signal name AAA are replaced with the signal name C
The netlist D2 (FIG. 10 (2)) converted to CC and the netlist D3 (FIG. 10 (3)) converted from the signal name AAA to the signal name DDD are output (step S5). Then, since the net list B is not over yet (step S8), the next line of the net list B “RONRI
And "is read (step S9).

Again, the first line "AAA;BBB;CCC;DDD;" of the signal name corresponding card file C is read (step S2) and compared with the signal name of the netlist B (step S3). No, and it is not the end of the signal name corresponding card file C (step S4),
The next line "AA1;BB" of the card file C corresponding to the signal name
1; CC1; DD1; "is read (step S6) and compared with the signal names of the netlist B (step S3). However, the last line “AA3;
BB3; CC; DD3; "
The signal names in the second row "RONRI AND" of the netlist B are output to the netlists D1, D2, and D3 as they are (step S7).

Next, the third line of the netlist B (“INP
UT1; AA1;) is read (step S9), and the first line "AAA;BBB;CC" of the signal name corresponding card file C is read.
C; DDD; "(step S2). Since the signal name “AA1” defined in the netlist B is not defined in the line of the signal name corresponding card file C currently being read (step S3), there is a definition in the signal name corresponding card file C, or The signal name corresponding card file C is read in order up to the last line of the signal name corresponding card file C (step S).
3, S4). The signal name “A” defined in the netlist B
“A1” is the second line “AA” of the signal name corresponding card file C.
1; BB1; CC1; DD1; "
The signal name “AA1” of the netlist B is changed to “BB1, CC
1, DD1 ”, and the netlist D1,
"INPUT;BB1;" and "INPU" in D2 and D3.
T; CC1 "and"INPUT; DD1 "are output (step S5).

For the fourth and subsequent rows of the netlist B, the above processing is performed according to the flowchart of FIG. 2 until the last row of the netlist B is reached (step S).
8), the netlists D1, D2, D3 are as shown in FIG. When FIG. 10 is compared with FIG. 8, the signal names AAA,
It can be seen that the difference is only BBB, CCC and DDD.

The logical description signal name conversion processing means 4 performs the signal name conversion processing for the logical description A by the above-described netlist signal name conversion processing means 3 as shown in FIG. 3 (FIG. 2).
The same conversion processing as described above is performed. As a result, a logical description F1 (FIG. 1) obtained by converting the signal name AAA of the logical description A into the signal name BBB.
1 (1)), the signal name AAA of the logical description A is changed to the signal name CCC
A logical description F2 (FIG. 11 (2)) converted into a logical description F3 (FIG. 11 (3)) obtained by converting the signal name AAA of the logical description A into a signal name DDD can be obtained.

Next, the netlist signal name verification means 5
All netlists, ie, netlists B, D1, D
2 and D3, as shown in FIG. 4, a netlist signal name difference file E (FIG.
Output 2). In FIG. 4, the first line of all netlists, that is, the first line of netlist B “DID AA
A ", the first line" DID BBB "of the netlist D1,
The first line "DID CCC" of the netlist D2 and the first line "DID DDD" of the netlist D3 are read (step S19). As a result, the signal names are not the same (step S20). The signal names are listed in E as "AAA;BBB;CCC;DDD;" (step S21).

Since the netlist is not the end (step S22), when the next line of the entire netlist is read (step S23), "RONRI;AND;" is defined in all the netlists B, D1, D2 and D3. Therefore, the process goes to the next step without doing anything (step S20).

For the third and subsequent lines of the netlist,
By performing the same processing as described above along the flowchart of FIG. 4, a netlist signal name difference file E as shown in FIG. 12 can be obtained.

The logical description signal name verification means 6 performs all logical descriptions, that is, a logical description A, a logical description F1, and a logical description F.
2 and the logical description F3, as shown in FIG.
The same processing as the signal name verification processing (FIG. 4) by the netlist signal name verification means 5 is performed. As a result, the logic description signal difference file G (FIG. 1) in which different signal names are listed.
3) is output. As is clear from comparison of FIG. 13 with FIG. 12, the results are the same, but this is the case where the verification result is normal.

As shown in FIG. 6, the signal name difference file verification processing means 7 outputs the netlist signal name difference file E
(FIG. 12) and file G (FIG. 13) with a difference in logic description signal name
The logic verification process is completed by comparing the contents of That is, both files are read line by line (steps S29 and S30). If the read contents are different (step S31), the files are read up to the last line of the logical description signal difference file G (steps S32 and S34). If the read contents still do not match, an error message is output (step S33). This is because the signal names of the netlist and the logical description are converted by the same signal name-compatible card file as described above.
As shown in FIG. 3, it is based on the fact that both should agree.

A program for executing the above-described logic synthesis method and logic verification method on a computer may be stored in a computer-readable recording medium such as a semiconductor memory or a magnetic disk and read and executed by the computer. Good. Such a program includes the logic synthesis means 1, the logic verification means 2, the netlist signal name conversion processing means 3, the logic description signal name conversion means 4, the netlist signal name verification processing means 5, and the logic description signal shown in FIG. It operates so that the computer performs the same function as the name verification processing means 6 and the signal name difference file verification processing means 7.

[0074]

A first effect of the present invention is that the number of steps of a logic synthesis operation for creating a plurality of netlists from one type of logical description can be reduced. The reason is that it is possible to create one logic description language, perform a logic synthesis operation once, and then create a plurality of netlists by signal name conversion processing using a signal name corresponding card file as an input. .

A second effect of the present invention is that the number of steps of a logic verification operation for verifying consistency between one type of logic description and a plurality of netlists can be reduced. The reason is that logic verification for verifying consistency between a basic netlist created from one type of basic logical description and a basic logical description is performed only once, and the rest is basic. This is because a difference between the signal name of the logical description and the signal name of the netlist which is obtained by converting the signal name of each of the basic netlists is detected, and the consistency between the two is verified.

Further, the above two effects have a ripple effect that, when a logic change occurs, the number of man-hours for creating a netlist and verifying the logic can be reduced, and correction errors due to manual intervention can be reduced. Bring.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of a netlist signal name conversion processing means 3 in the embodiment shown in FIG. 1;

FIG. 3 is a flowchart of a logical description signal name conversion processing means 4 in the embodiment shown in FIG. 1;

FIG. 4 is a flowchart of a netlist signal name verification processing means 5 in the embodiment shown in FIG. 1;

FIG. 5 is a flowchart of a logic description signal name verification unit 6 in the embodiment shown in FIG. 1;

FIG. 6 is a flowchart of a signal name difference file verifying means 7 in the embodiment shown in FIG. 1;

FIG. 7 is a diagram showing a specific example of a logical description A;

FIG. 8 is a diagram showing a specific example of a netlist B;

FIG. 9 is a diagram showing a specific example of a card file C corresponding to a signal name;

FIG. 10 is a diagram showing a specific example of a netlist D after signal name conversion;

FIG. 11 is a diagram showing a specific example of a logical description F after signal name conversion;

FIG. 12 is a diagram showing a specific example of a netlist signal name difference file E;

FIG. 13 is a diagram showing a specific example of a logical description signal name difference file G;

FIG. 14 is a block diagram showing an example of a conventional logic synthesis / verification system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic synthesis means 2 Logic verification means 3 Netlist signal name conversion processing means 4 Logic description signal name conversion processing means 5 Netlist signal name verification means 6 Logic description signal name verification means 7 Verification means of signal name difference file A Logic description B Netlist C Signal name corresponding card file D1 Netlist D2 Netlist E Netlist signal name difference file F1 Logic description F2 Logic description G Logic description signal name difference file

Claims (8)

[Claims] 1. A logic synthesis device for creating a plurality of netlists having different signal names from one type of logic description, comprising: logic synthesis means for creating a netlist from the logic description; Netlist signal name conversion processing means for creating a netlist corresponding to the different signal names by converting signal names in the netlist in accordance with a signal name corresponding card file listing the different signal names. A logic synthesis device characterized by the above. 2. A logic verification device for creating a plurality of netlists having different signal names from one type of logic description and performing logic verification of the created netlist, wherein a logic synthesis unit creates a netlist from the logic description. Logic verification means for verifying consistency between the logical description and the netlist; and the netlist according to a signal name correspondence card file listing the different signal names corresponding to signal names in the netlist. Netlist signal name conversion processing means for creating a netlist corresponding to the different signal names by converting the signal names in the signal names, and a signal name correspondence card listing the different signal names in correspondence with the signal names in the netlist A logical description for creating a logical description corresponding to the different signal names by converting the signal names in the logical description according to a file. Signal name conversion processing means, a netlist signal name difference file in which a signal name difference between a netlist created from the logical description and a netlist after the signal name conversion is detected and the signal names are listed And a netlist signal name verification unit that outputs a logical description signal name difference file in which the signal names are detected between the logical description and the logical description after the signal name conversion. Logic verification signal verification means for verifying the consistency between the netlist signal name difference file and the logic description signal name difference file. apparatus. 3. The signal name difference file verification means outputs an error message when a signal name in the netlist signal name difference file does not exist in the logical description signal name difference file. The logic verification device according to claim 2, wherein 4. A logic synthesis method for creating a plurality of netlists having different signal names from one type of logic description, comprising: a logic synthesis procedure for creating a netlist from the logic description; and a correspondence between signal names in the netlist. A netlist signal name conversion process for creating the netlist corresponding to the different signal names by converting the signal names in the netlist according to the signal name corresponding card file listing the different signal names. A logic synthesis method characterized by the following. 5. A logic verification method for creating a plurality of netlists having different signal names from one type of logic description and performing logic verification of the created netlist, wherein a logic synthesis procedure for creating a netlist from the logic description A logic verification procedure for verifying consistency between the logic description and the netlist; and the netlist according to a signal name correspondence card file listing the different signal names corresponding to signal names in the netlist. A netlist signal name conversion processing procedure for creating a netlist corresponding to the different signal names by converting signal names in the inside, and a signal name correspondence card listing the different signal names corresponding to the signal names in the netlist A logical description that creates a logical description corresponding to the different signal names by converting signal names in the logical description according to a file. A signal name conversion processing procedure, a netlist signal name difference file in which a signal name difference between a netlist created from the logical description and the netlist after the signal name conversion is detected and the signal names are listed A netlist signal name verifying procedure for outputting a signal name difference between the logic description and the logic description after the signal name conversion, and outputting a logic description signal name difference file listing the signal names A logic description signal name verification procedure, and a signal name difference file verification procedure for verifying consistency between the netlist signal name difference file and the logic description signal name difference file. . 6. In the signal name difference file verification procedure, an error message is output when a signal name in the netlist signal name difference file does not exist in the logical description signal name difference file. The logic verification method according to claim 5, wherein 7. A logic synthesis method for creating a plurality of netlists having different signal names from one type of logic description, comprising: a logic synthesis procedure for creating a netlist from the logic description; and a signal name in the netlist. A netlist signal name conversion process for creating a netlist corresponding to the different signal names by converting the signal names in the netlist according to the signal name corresponding card file listing the different signal names in a corresponding manner. A computer-readable recording medium storing a program for causing a computer to execute the logic synthesis method characterized by having the above. 8. A logic verification method for creating a plurality of netlists having different signal names from one type of logic description and performing logic verification of the created netlist, wherein a logic for creating a netlist from the logic description is provided. A synthesis procedure, a logic verification procedure for verifying the consistency between the logic description and the netlist, and a signal name correspondence card file listing the different signal names corresponding to the signal names in the netlist. A netlist signal name conversion processing procedure for creating a netlist corresponding to the different signal names by converting signal names in the netlist; and a signal name listing the different signal names corresponding to the signal names in the netlist. A logical description for creating a logical description corresponding to the different signal names by converting signal names in the logical description according to a corresponding card file. A signal name conversion processing procedure, a netlist signal name difference file in which a signal name difference between a netlist created from the logical description and a netlist after the signal name conversion is detected and the signal names are listed A netlist signal name verifying procedure for outputting a signal name difference between the logic description and the logic description after the signal name conversion, and outputting a logic description signal name difference file listing the signal names A logic description signal name verification procedure, and a signal name difference file verification procedure for verifying consistency between the netlist signal name difference file and the logic description signal name difference file. Computer-readable recording medium storing a program for causing a computer to execute the program.