JP3196950B2 - Circuit information verification system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program for writing in a so-called FPGA (Field Programmable Gate Array), in which a user determines the operation of a circuit by writing circuit information inside the device by a program, and is rewritable by the user. It relates to a system for performing verification.

[0002]

2. Description of the Related Art FIG. 5 shows a general procedure of an FPGA design system for designing a circuit on an FPGA. According to FIG.
First, connection information of a general logic circuit designed by a user, that is, a netlist 101 is input to the design system. The netlist 101 may be described by the user in some cases, or may be logically synthesized from a language (hardware description language) describing circuit functions by a CAD (Computer Aided Design) system using a higher-level design system. May be a result automatically generated through the above procedure. Next, a procedure for mapping this netlist 101 to a programmable logic cell specific to the target FPGA, that is, a technology mapping 102
Perform With respect to the netlist 103 after the mapping is completed, an arrangement procedure 104 for arranging each logic cell at an appropriate position of the device is performed in consideration of a circuit delay, a state of a programmable wiring element, and the like. Further, in the netlist 105 after placement, a wiring procedure 106 for allocating input / output wiring to the placed logic cell to an appropriate programmable wiring area of the device is performed. The structure of the netlist 107 after the wiring performed through the steps up to this point is usually composed of program contents of the logic cell, and enumeration of the logic cell and the input / output terminals of the device and the programmable wiring used. F
In order to actually download the circuit information to the PGA, the netlist is further stored in a look-up table memory for realizing the logic of the FPGA, a bit string of a memory for controlling a selector for realizing the logic, a connection or disconnection of the programmable wiring. Or a procedure for converting the data into a program binary signal such as a bit string of a memory for controlling the direction of a buffer, that is, a bit image conversion 108 is required. The converted program binary signal 109 is transmitted from the design system to the actual FPGA device 1.
11 is downloaded 110.

FIG. 6 shows a specific example of a part of a hardware configuration inside an FPGA. Program binary signal 1
09 is stored in the storage element 122-1, 122-2 at a predetermined position on the FPGA device 111, and the wiring connection switches 124-1, 124 for connecting the programmable wiring elements 123-1, 123-2, 123-3 to each other. -2 controls connection / disconnection, and the storage element itself functions as a rewritable logic cell as the look-up table memories 125-1 and 125-2. Desired processing is performed by inputting the input data 126 one after another while holding the values of these memories.

FIG. 7 shows a netlist after wiring shown in FIG.
6 shows a correspondence between the program binary signal of FIG. 5 and a specific example of the FPGA internal structure of FIG. The netlist 107 after the wiring is stored in the programmable wiring element 1 inside the FPGA.
It consists of 23 enumerations. Here, the wiring connection switch 1
24 is not described in the netlist 107 after wiring. With regard to the description of the series of programmable wiring elements 123 on the netlist, by setting the bits of the program binary signal 109 corresponding to the wiring connection switch 124 between the adjacent programmable wiring elements 123 to a connected state, Wiring is performed.

[0005]

Here, what should be noted in downloading the program binary signal of the FPGA is that the device may be destroyed depending on the contents of the storage element of the wiring connection control. For example, in FIG. 7, in the netlist 107 after wiring, C: OU
T wiring element 123-1 and NET1 wiring element 123-
3 is connected, so that the storage element 1 of B is correctly connected to the wiring connection switch 124-2 of SW: B.
Data "1" is stored in 22-2, and "0" is stored in the storage element 122-1 of A so that the wiring connection switch 124-1 of SW: A is disconnected. However, at this time, the program binary signal 109
When both the bits corresponding to the storage elements 122-1 and 122-2 of A and B become “1”, the wiring connection switch 124-1 of SW: A and the wiring connection switch 124-2 of SW: B Are connected together, and the output signal of the lookup table 125-1 of C and the output signal of the lookup table 125-2 of D are the wiring elements 123 of the NET1.
-3, which may destroy the device. In order to prevent such a signal conflict, it is necessary to verify in advance that the program binary signal 109 is valid. Further, it is conceivable that a signal error may occur on a transmission path when downloading to a device. For this reason, conventionally, measures against transmission path errors have been taken by, for example, reading back a program binary signal downloaded from a device and adding error correction bits to the program binary signal. However, if there is an error in the program binary signal before downloading, the validity cannot be verified by this method. It is very difficult to verify the validity of the program binary signal itself before the download because the conflicting portion of the signal is complicatedly related to the entire device. On the other hand, it is possible to verify the validity of the netlist after wiring by confirming that there is only one signal input point for a series of connected programmable wiring elements using graph theory or the like. Yes, not difficult. However, even if the netlist after wiring is valid, the bit image conversion mechanism is complicated, and there is an error in the bit image conversion mechanism or an error in the signal on the transmission line when downloading to the device. Considering the possibility of occurrence, it is not sufficient to verify the validity of the netlist after routing.

An object of the present invention is to provide a verification system capable of easily verifying the correctness of a program binary signal for determining information of an FPGA circuit.

[0007]

According to the present invention, in order to solve the above-mentioned problems, in claim 1, the operation of a circuit inside the device is determined by downloading a bit string of circuit information from outside the device. In a system in which a bit string of circuit information is converted from a connection description of a circuit element and downloaded to a device, circuit information for verifying the validity of the connection description of the circuit element and the validity of the conversion of the circuit information into a bit string A verification unit that verifies the validity of the connection description of the circuit element, a conversion unit that converts the connection description of the circuit element into a bit string of the circuit information, and converts the bit string of the circuit information into An inverse transformation unit for converting the connection description of the circuit element into a connection description of the circuit element, and the connection unit of the circuit element inversely transformed by the inverse transformation unit is verified by the verification unit According to a second aspect of the present invention, in the circuit information verification system according to the first aspect, a connection description of the circuit element inversely transformed by the inverse transformation unit and a connection description of the circuit element before the circuit information is converted into a bit string. And a comparison unit for comparing with. According to the third aspect, the operation of the circuit inside the device is determined by downloading a bit string of circuit information from outside the device, and the bit string of the circuit information is converted from the connection description of the circuit element and downloaded to the device. Circuit information verification system for verifying the validity of the connection description of the circuit element, the validity of converting the circuit information into a bit string, and the validity of downloading the circuit information bit string to a device in a simple system. A verification unit that verifies the validity of the connection description of the circuit element, a conversion unit that converts the connection description of the circuit element into a bit string of the circuit information, and a download unit that downloads the bit string of the circuit information into the device And the bit string of the circuit information downloaded inside the device from the inside of the device to the outside. A readback unit for reading, a comparison unit for comparing a bit string of the circuit information read back with the bit string of the circuit information before downloading to a device, and an inverse conversion for converting the bit string of the circuit information into a connection description of the circuit element A connection description of the circuit element inversely transformed by the inverse transformation unit is verified by the verification unit. According to a fourth aspect of the present invention, in the circuit information verification system according to the third aspect, the connection description of the circuit element inversely transformed by the inverse transformation unit and the connection description of the circuit element before the circuit information is converted into a bit string. And a comparison unit for comparing with.

[0008]

According to the first aspect, the inverse conversion unit performs an inverse conversion from the program binary signal to the netlist after wiring, and once returns the program binary signal to the netlist, which is verified by the verification unit. Thus, the verification of the program binary signal can be simultaneously performed by the verification of the netlist after the wiring. According to the second aspect, the netlist after the direct routing of the original and the inversely converted netlist are compared by a file by the comparing unit, thereby directly indicating to the designer where and how the two netlists are different. be able to. According to the third aspect, the program binary signal downloaded to the device is read back by the read back unit, and the two program binary signals before and after the download are compared by the comparison unit, whereby the transmission path error of the download is obtained. Therefore, it is possible to prevent the destruction of the inside of the chip caused by the above. Further, according to the fourth aspect, the comparison unit directly compares the netlist after the original wiring and the inversely converted netlist with a file, thereby directly asking the designer about where and how the two netlists differ. Can be shown.

[0009]

FIG. 1 shows a circuit information verification system according to a first embodiment of the present invention. The circuit information verification system according to the present embodiment includes a netlist verification unit 20 that verifies the validity of the netlist 107 after wiring and the inverted netlist 205.
1. A bit image conversion unit 202 that converts the netlist verified by the verification unit 201 into a program binary signal 109, and converts the program binary signal 109 into an inverse conversion netlist 205 having the same file format as the netlist 107. Netlist reverse conversion unit 20 for conversion
3, and a memory address map 204 that represents an adjacent relationship between the programmable wiring elements on the FPGA and addresses of storage elements that control wiring connection switches existing between the adjacent programmable wiring elements.

Next, the operation of this embodiment will be described. The initial input in the circuit information verification system of the present embodiment is:
9 is a netlist 107 after wiring described using a higher-level design system or the like. Netlist 10 after this wiring
7 describes the contents of the operation in each programmable logic cell of the FPGA device as a target having the structure shown in FIG. 6, the input / output terminals of each programmable logic cell, the input / output terminals of the device, and the programmable wiring elements connecting these. In other words, it is assumed that there is no description about the wiring connection switch. The unit of description of the wiring here is called a net, and one net is configured by terminals having the same potential on an implemented circuit and programmable wiring elements having the same potential connecting these terminals. That is, the netlist 107 after one wiring
Consists of a plurality of programmable logic cell descriptions and a plurality of net descriptions.

Next, the netlist 107 after wiring is verified by a netlist verification unit 201 for the validity of the description. The verification items here are that adjacent programmable wiring elements in the description of one net are adjacent, that there is only one signal output terminal in one net, and so on. It is. This verification can be performed by referring to the memory address map 204. As a result of this verification, an error message is shown for a corresponding portion of the netlist determined to be invalid. The netlist 107 after the wiring determined to be valid by the netlist verification unit 201 is input to the bit image conversion unit 202, and according to the content of the memory address map 204, the program binary corresponding to the content of the memory of the FPGA device. It is converted to a signal 109.

In order to verify whether or not the program binary signal 109 is valid, the netlist reverse conversion unit 203 converts the program binary signal 109 again into an inverse conversion netlist 205 having the same file format as the netlist 107 after wiring. . The netlist inverse conversion unit 203 receives the program binary signal 109 as input, and
In accordance with the contents of No. 04, a description of the net listing the contents of the operation of the programmable logic cell and the programmable wiring elements between the terminals is generated. The netlist verification unit 201 verifies the validity of the inverse netlist 205 again.

In this embodiment, in order to verify the validity of the program binary signal 109, the program binary signal 109 is once inversely transformed into an inverse translation netlist 205 having the same format as the original wired netlist 107, and this file is The verification is performed by the netlist verification unit 201. At this time, if there is any error in the program binary signal 109, the inversely converted netlist 205 is often not valid as a netlist. Errors can be detected. Even if an error in the program binary signal 109 is determined to be valid as a netlist in the inverse conversion netlist 205 generated by the inverse conversion, such an error in the program binary signal 109 will not This is a case where a function different from a desired function is realized as the function realized above, and the device is not destroyed to the last.

In this embodiment, it is assumed that there is an error in the program binary signal 109 and that the netlist verifying unit 201 functions normally because there is a bug in the bit image converting unit 202 or the generated program After the binary signal 109 is generated, it is assumed that an error is mixed for some reason. Since the latter case is hardly considered, in this case, it is considered that the bit image conversion unit 202 has a bug in most cases. In such a case, the bit image conversion unit 2
It is dangerous to design the two conversion units by partially diverting the mechanism of No. 02 to the mechanism of the netlist inverse conversion unit 203, and it cannot be said that the program binary signal 109 has been properly verified. Therefore, the design of the bit image conversion unit 202 and the design of the netlist inverse conversion unit 203 are performed completely separately by another designer, and these are combined to construct the system of this embodiment. In this way, the netlist verification unit 201 effectively functions as verification of the validity of the design of both conversion units, which are the core of the entire system.

As described above, according to the present embodiment, the verification of the validity of a program binary signal, which has been extremely complicated and practically difficult in the past, can be verified by using a means called inverse transformation to verify a higher-level netlist. As a result, it is possible to easily verify the validity of the program binary signal.

FIG. 2 shows a circuit information verification system according to a second embodiment of the present invention. The circuit information verification system of the present embodiment is different from the first embodiment in that the netlist 10
7 and an inverted netlist 205 are added to a netlist comparing unit 206, and the other configuration is the same as that of the first embodiment.

Next, the operation of the second embodiment of the present invention will be described. The initial input in the circuit information verification system of the present embodiment is the wired net system 107 described using the higher-level design system or the like. The description of the netlist 107 after the wiring is as described in the first embodiment.

Next, the netlist 107 after wiring is verified by the netlist verification unit 201 for the correctness of the description. The verification items here are that adjacent programmable wiring elements in the description of one net are adjacent, that there is only one signal output terminal in one net, and so on. It is. This verification can be performed by referring to the memory address map 204. As a result of this verification, an error message is shown for a corresponding portion of the netlist determined to be invalid. The netlist 107 after the wiring determined to be valid by the netlist verification unit 201 is input to the bit image conversion unit 202, and according to the content of the memory address map 204, a program binary signal corresponding to the memory content of the FPGA device. It is converted to 109.

In order to verify whether the program binary signal 109 is valid, the netlist reverse conversion unit 20
3, the data is converted again into an inverse conversion netlist 205 having the same file format as the netlist 107 after wiring. The netlist inverse conversion unit 203 receives the program binary signal 109 as an input,
, A description of the net listing the contents of the operation of the programmable logic cell and the programmable wiring elements between the terminals is generated. The inversely converted netlist 205 is compared by the netlist comparing unit 206 with the netlist 107 after the original wiring, and shows different parts between the two. At the same time, if necessary, the reverse conversion netlist 205 is again verified by the netlist verification unit 201 for the validity of the netlist.

In this embodiment, a netlist comparing unit 206, which does not exist in the first embodiment, is added. The netlist comparing unit 206 directly outputs the netlist 107 after the original wiring and the inversely converted netlist 20.
By comparing the file 5 with the file 5, it is possible to directly indicate to the designer where and how the two netlists are different. Since the method of inverse conversion in the netlist inverse conversion unit 203 is not always unique, the netlist 107 after wiring and the inverted netlist 205 do not always match even if the conversion is valid. . Therefore, the netlist comparing unit 206 cannot always be used for verifying the validity of the program binary signal 109. However, when an error occurs in the reverse conversion netlist 205 by the netlist verification unit 201, the netlist comparison unit 206
The advantage is that the designer can easily show the designer how the corresponding parts of the two netlists are different.

FIG. 3 shows a circuit information verification system according to a third embodiment of the present invention. The circuit information verification system according to the present embodiment includes a bit image comparison unit 207 that compares the first program binary signal 109-1 and the second program binary signal 109-2 in the first embodiment.
And a bit image download unit 208 for downloading the program binary signal 109-1 to the FPGA device 111 and a bit image readback unit 209 for reading back the program binary signal 109-2 from the FPGA device 111. Other configurations are the same as those of the first embodiment.

Next, the operation of this embodiment will be described. The initial input in the circuit information verification system of the present embodiment is:
9 is a netlist 107 after wiring described using a higher-level design system or the like. Netlist 10 after this wiring
The description of 7 is as described in the above embodiment.

Next, the netlist 107 after wiring is verified by the netlist verification unit 201 for the validity of the description. The verification items here are that adjacent programmable wiring elements in the description of one net are adjacent, that there is only one signal output terminal in one net, and so on. It is. This verification can be performed by referring to the memory address map 204. As a result of this verification, an error message is shown for a corresponding portion of the netlist determined to be invalid. The netlist 107 after wiring determined to be legitimate by the netlist verification unit 201 is input to the bit image conversion unit 202 and, in accordance with the content of the memory address map 204, the netlist 107 corresponding to the content of the memory of the FPGA device 111. 1 program binary signal 109-1
Is converted to This first program binary signal 10
9-1 is obtained by the bit image download unit 208.
It is downloaded inside the FPGA device 111. F
From the inside of the PGA device 111, the program binary signal stored in the device 111 can be extracted to the outside of the device by the bit image readback unit 209 as necessary. This is referred to as a second program binary signal 109-2. The second program binary signal 109-2 is converted by the bit image comparing unit 207 into the first program binary signal 10-2 as necessary.
9-1. As a result, it is possible to confirm whether the second program binary signal 109-2 once stored in the FPGA device 111 is the same as the first program binary signal 109-1 before storage, and a transmission path error at the time of downloading is confirmed. Can be verified.

On the other hand, the read-back second program binary signal 109-2 has the same file format as that of the wired netlist 107 by the netlist reverse conversion unit 203 in order to verify whether it is valid. It is converted again to the inverse conversion netlist 205. The netlist inversion unit 203 receives the program binary signal 109 and generates a description of a net listing the contents of the operation of the programmable logic cell and the programmable wiring elements between the terminals while following the contents of the memory address map 204. I do. The netlist verification unit 201 verifies the validity of the inverse netlist 205 again.

According to the third embodiment, in addition to the verification of the program binary signal according to the first embodiment, once F
By reading back the program binary signal downloaded to the PGA device and comparing the two program binary signals before and after downloading, it is possible to prevent the destruction inside the chip due to the transmission path error of the download beforehand. As a result, the reliability of the circuit information verification system can be further improved.

FIG. 4 shows a circuit information verification system according to a fourth embodiment of the present invention. The circuit information verification system of the present embodiment is different from the third embodiment in that a netlist comparing unit 206 is added to the netlist 107 after wiring and the inversely converted netlist 205. This is the same as the embodiment.

Next, the operation of this embodiment will be described. In the circuit information verification system of this embodiment, in addition to the operation of the third embodiment, the netlist comparing unit 206 converts the inverted netlist 205, which has been inverted by the netlist inverse conversion unit 203, into the original. Compared with the netlist 107 after wiring, different portions are shown in both netlists. At the same time, if necessary, the inverse conversion netlist 20
In step 5, the netlist verification unit 201 verifies the validity of the netlist again.

In the present embodiment, a netlist comparing unit 206 that does not exist in the third embodiment is added. The netlist comparing unit 206 directly outputs the netlist 107 after the original wiring and the inversely converted netlist 20.
By comparing the file with the file No. 5, it is possible to directly indicate to the designer where and how the two netlists are different. Since the method of the reverse conversion in the netlist reverse conversion unit 203 is not always unique, the netlist 107 after wiring and the reverse conversion netlist 205 do not always match even if the conversion is valid. Therefore, the netlist comparing unit 206 cannot always be used for verifying the validity of the program binary signal 109. However, when an error occurs in the reverse conversion netlist 205 by the netlist verification unit 201, the netlist comparison unit 206
The advantage is that the designer can easily show the designer how the corresponding parts of the two netlists are different.

[0029]

As described above, according to the first aspect of the present invention,
According to (4), it is possible to replace the verification of the validity of a program binary signal, which has been extremely complicated and difficult in the past, with the verification of a higher-level netlist by using a means of inversion. As a result, the validity of the program binary signal can be easily verified. According to the second and fourth aspects, the netlist after the direct routing of the original and the inversely converted netlist are compared by a file by the comparing unit, so that the designer can directly determine where and how the two netlists are different. Can be shown. According to the third aspect of the present invention, the program binary signal downloaded to the device is read back by the read back unit, and the two program binary signals before and after the download are compared by the comparison unit, so that the transmission path error of the download is obtained. Therefore, it is possible to prevent the destruction of the inside of the chip caused by the above.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a circuit information verification system according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a configuration of a circuit information verification system according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a configuration of a circuit information verification system according to a third embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of a circuit information verification system according to a fourth embodiment of the present invention;

FIG. 5 shows a conventional F for designing a circuit on an FPGA device.
Diagram showing the configuration of the PGA design system

FIG. 6 is a diagram illustrating a part of a hardware configuration inside an FPGA;

FIG. 7 is a diagram showing correspondence with FIGS. 5 and 6;

[Explanation of symbols]

107: Netlist after wiring, 109, 109-1,
109-2: Program binary signal, 111: FPG
A device, 122-1, 122-2 ... storage element, 12
3-1, 123-2, 123-3 ... programmable wiring element, 124-1 and 124-2 ... wiring connection switch, 1
25-1, 125-2 ... look-up table memory,
201: Netlist verification unit, 202: Bit image conversion unit, 203: Netlist reverse conversion unit, 204: Memory address map, 205: Reverse conversion netlist, 20
6: Netlist comparison unit, 207: Bit image comparison unit, 208: Bit image download unit, 209 ...
Bit image readback unit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-123269 (JP, A) JP-A-3-219367 (JP, A) JP-A-63-131842 (JP, A) JP-A-5-193 235163 (JP, A) JP-A-4-352284 (JP, A) JP-A-4-153774 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 664 G06F 17/50 666 G01R 31/28 H03K 19/173 101 H01L 21/82 JICST file (JOIS)

Claims (4)

(57) [Claims] An operation of a circuit inside a device is determined by downloading a bit string of circuit information from outside the device, and the bit string of the circuit information is converted from a connection description of a circuit element and downloaded to the device. A circuit information verification system for verifying the validity of the connection description of the circuit element and the validity of the conversion of the circuit information into a bit string in a system, wherein the verification unit verifies the validity of the connection description of the circuit element. A conversion unit that converts a connection description of a circuit element into a bit string of the circuit information; and an inverse conversion unit that converts the bit string of the circuit information into a connection description of the circuit element. A verification system for circuit information, wherein the connection description of the inversely transformed circuit element is verified by the verification unit. 2. A circuit for comparing a connection description of the circuit element inversely transformed by the inverse transformation section with a connection description of a circuit element before the circuit information is converted into a bit string. The circuit information verification system according to claim 1, wherein: 3. The operation of a circuit inside the device is determined by downloading a bit string of circuit information from outside the device, and the bit string of the circuit information is converted from the connection description of the circuit element and downloaded to the device. A circuit information verification system for verifying the validity of connection description of the circuit element and the validity of conversion of the circuit information into a bit string and the validity of downloading the circuit information bit string to a device, A verification unit that verifies the validity of the connection description of the circuit element; a conversion unit that converts the connection description of the circuit element into a bit string of the circuit information; and a download unit that downloads the bit string of the circuit information into the device. The bit string of the circuit information downloaded inside the device is transferred from inside the device to outside. A readback unit that reads out, a comparison unit that compares the bit string of the read back circuit information with the bit string of the circuit information before downloading to the device, and a reverse unit that converts the bit string of the circuit information into a connection description of the circuit element. 4. A conversion unit, wherein the connection description of the circuit element inversely transformed by the inverse transformation unit is verified by the verification unit.
Verification system for the described circuit information. 4. A comparison unit for comparing the connection description of the circuit element inversely transformed by the inverse transformation unit with the connection description of the circuit element before the circuit information is converted into a bit string. 4. The system for verifying circuit information according to claim 3, wherein: