JP2000148807A - Logic synthesis system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prepare a plurality of net lists from one kind of a logical description language by using a signal name correspondence card file and signal name conversion processing. SOLUTION: The first line of a net list is read (S1). After that, the first line of a card file is read (S2). Next, it is decided whether or not the signal name described in the read line of the net list is the same as the signal name defined in the read line of the card file (S3). When they are the same, the signal name of the read line of the net list is converted into the signal name of the card file and is outputted to a new net list (S5). When they are not the same, it is decided whether or not the line read from the card file is the last line of the card file (S4). When it is not the last line, the next line of the card file is read (S6). When it is the last line, the read line of the net list is outputted to the new net list (S7).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to LSI (Large Scale Integrated Circuit) design, and more particularly to a logic synthesis system for creating a netlist from a logic description language.

[0002]

2. Description of the Related Art A netlist conversion system capable of easily recognizing a symbol correspondence between an LSI circuit design CAD (computer-aided design system) and a board design CAD is disclosed in Japanese Patent Application Laid-Open No. Hei 7-141417.
Japanese Patent Application Laid-Open No. 9-245068 discloses a netlist conversion device that can correct a conversion rule of a converted netlist automatically based on the correction.

In such a conventional logic synthesis system using a logic description language as input, only one type of netlist can be created from one type of logic description language. According to the conventional technique, a method of creating a plurality of netlists having the same logic but different signal names from one kind of logic description language is shown in FIG.
Shown in

In the prior art shown in FIG. 3, a plurality of netlists are created from one kind of logical description language. First, a base logical description language (a in FIG. 3) is created.
Next, an operation of copying a plurality of base logic description languages (FIG. 3B) is performed. Next, each logical description language (FIG. 3)
(B) is manually converted to a signal name (c in FIG. 3) to create a logical description language (d in FIG. 3). Finally, a logic synthesis operation (e in FIG. 3) is performed on the logic description language (d in FIG. 3) for which the signal name conversion has been completed, and a netlist (f in FIG. 3) is created.

[0005]

In the above-described conventional logic synthesis system, there are a plurality of logic description languages having the same logic but different signal names. It is necessary to perform the combining operation several times. For this reason, there is a problem that the number of man-hours for logic synthesis work increases.

In addition, since there are a plurality of logic description languages having the same logic and different signal names, when a logic change occurs, a plurality of logic description languages need to be modified. However, there is a problem that the number of man-hours required for correction in the case of occurrence of the problem increases.

Furthermore, since a plurality of logic description languages having the same logic and different signal names exist, if a logic change occurs, it is necessary to correct the plurality of logic description languages.
Therefore, there has been a problem that the number of manual corrections increases and the possibility of a correction error increases.

An object of the present invention is to provide a logic synthesis system that can create a plurality of netlists from one kind of logic description language by using a signal name card file.

Another object of the present invention is to perform a logic synthesis operation only once so that a plurality of netlists can be created.
An object of the present invention is to provide a logic synthesis system that reduces the number of steps required for logic synthesis work.

[0010] Still another object of the present invention is that a plurality of netlists can be created by performing a single logic synthesis operation. Therefore, even if the logic of the logic description language is changed, one logic description language is modified. It is an object of the present invention to provide a logic synthesis system capable of creating a plurality of netlists by simply performing the operation.

Another object of the present invention is to provide a logic synthesizing system which facilitates correction by changing the logic of a logic description language and reduces correction errors due to manual intervention.

[0012]

In order to solve the above-mentioned problems, the logic synthesis system according to the present invention employs the following characteristic configuration.

(1) In a logic synthesis system for creating a plurality of netlists by logic synthesis using a logic description language, a plurality of signal names corresponding card files and signal name conversion processing are used to convert a plurality of netlists from one type of logic description language. A logic synthesis system that creates netlists.

(2) The signal corresponding card file includes:
The logic synthesis system according to the above (1), which describes the correspondence between a signal name of a logic description language, which is an input when creating a netlist after the logic synthesis work, and a converted signal name.

(3) Logic synthesis is performed based on the logic description language, a first netlist is created, signal name conversion processing is performed using the netlist and a signal name corresponding card file, and a plurality of second and subsequent A logic synthesis system that creates a netlist for

(4) A logic synthesis system that includes a logic description language, logic synthesis and netlist, a signal name correspondence card file, and a signal name conversion process and creates a plurality of netlists from one type of logic description language .

(5) The logic synthesis of the above (1), (2), (3) or (4), which makes it possible to modify the logic description language and the signal correspondence card file when a logic change occurs. system.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a logic synthesis system according to the present invention will be described below in detail with reference to the accompanying drawings, particularly FIGS.

FIG. 1 shows a preferred embodiment of a logic synthesis system according to the present invention. The logic synthesis system shown in FIG. 1 includes a logic description language a, a logic synthesis e, a netlist g after logic synthesis work, a signal name correspondence card file h, a signal name conversion process i, and a plurality of netlists after the signal name conversion process. f.

Next, the input / output files a, e, and
g, h, i and f will be described. The logic description language a is
This is an input file to be input to the logic synthesis operation e. The netlist g is a file created in the logic synthesis operation e. The signal name correspondence card file h is a file in which the correspondence between the signal names described in the logic description language a input in the logic synthesis operation e and the converted signal names is described. The netlist (f) is a file created in the signal name conversion processing i.

The operation of the input / output file for each of these functions will be described. The logic synthesis e inputs a logic description language a and outputs a netlist g. In the signal name conversion processing i, the signal name corresponding card file h and the netlist g are input and a plurality of netlists f are output.

Next, the operation of the logic synthesis system of the present invention shown in FIG. 1 will be described. The operation of the signal name conversion processing i of FIG. 1 will be described with reference to the flowchart of FIG. In FIG. 2, a netlist g is a netlist output in the logic synthesis operation e. The card file is a signal name corresponding card file h.

In the flowchart (flow chart) of FIG. 2, the first line of the netlist g output in the logic synthesis operation e is read (S1). Next, the first line of the card file is read (S2). It is determined whether or not the signal name described in the line of the read netlist is the same as the signal name defined in the line of the read card file (S3). It is determined whether the line read from the card file is the last line of the card file (S4). The signal names in the read netlist row are converted into the card file signal names and output to a new netlist (S5). Next, the next line of the card file is read (S6). The line of the netlist read in this process (S6) is output to a new netlist (S7). Then, it is determined whether the line read from the netlist is the last line of the netlist (S
8). Finally, the next line of the netlist is read (S9).

Next, each process (S1) to (S
9) will be described in detail. First, the process (S1) reads the first line of the netlist. In this process (S1), the first line (first line) of the input netlist file is read.
Then, the process of reading the first line of the card file (S2)
I do.

Processing for reading the first line of the card file (S
In 2), the first line (first line) of the input card file is read. Next, the processing (S3) determines whether or not the signal name described in the read netlist line is the same as the signal name defined in the read card file line.

In the sameness determination processing (S3), when the signal name described in the read netlist line is the same as the signal name defined in the read card file line, the read is performed. The process proceeds to a process (S5) of converting the signal name of the line of the netlist into the signal name of the card file and outputting the converted signal to a new netlist. If the signal name described in the read netlist line is not the same as the signal name defined in the read card file line, the line read from the card file is the last line in the card file. Is determined (S4).

In the processing (S4) for determining whether or not the last line of the card file, if the line read from the card file is the last line of the card file, the processing (S4)
In step 7), the read netlist line is output to a new netlist. If the line read from the card file is not the last line of the card file, the next line of the card file is read by the processing (S6).

The signal name of the read netlist row is
In the process of converting the signal name into the card file signal and outputting it to a new netlist (S5), the signal name description part of the line of the read netlist corresponds to the signal name defined in the line read by the card file. Convert to the name of the signal and output to a new netlist. Thereafter, the process proceeds to a process (S8) for determining whether or not the line read from the netlist is the last line of the netlist.

Processing for reading the next line of the card file (S
At 6), the next line of the currently read card file is read. Then, the processing shifts to the above-described processing (S3) for determining whether or not the signal name described in the line of the read netlist is the same as the signal name defined in the line of the read card file. .

On the other hand, in the processing (S7) for outputting the read netlist line to a new netlist without conversion, the signal name is not converted to the read netlist line, but output to the new netlist as it is. Then
The process proceeds to a process (S8) of determining whether the line read from the netlist is the last line of the netlist.

In the processing (S8) for determining whether or not the line read from the netlist is the last line of the netlist, if the line read from the netlist is the last line of the netlist, this processing is performed. finish. If the line read from the netlist is not the last line of the netlist, the process of reading the next line of the netlist (S9)
Move to.

In this process (S9), the next line of the currently read netlist is read. Thereafter, the process shifts to the above-described process (S2) for reading the first line of the card file.

Next, as a specific example of the logic synthesis system of the present invention, a plurality of netlists (example 3) are created from the netlist (example 1) after the logic synthesis operation e using a card file (example 2). The following describes the method and procedure for performing this.

<Example of Netlist Used as Input for Signal Name Conversion Processing (Example 1)>DID;AAA;RONRI;AND;INPUT1;AA1;INPUT2;AA2;OUTPUT;AA3;

<Example of Netlist Corresponding Card File (Example 2)>AA1;BB1;CC1;DD1;AA2;BB2;CC2;DD2;AA3;BB3;CC3;DD3;

<Example of Netlist (Example 3)> DID; BBB; RONRI; AND; INPUT1; BB1; INPUT2; BB2; OUTPUT;

First, (DID; AAA;) in the first line is read from the netlist g to be input to the signal name conversion processing.
Next, the first line (AAA; BB) from the card file h
B; CCC; DDD;). Since the signal name "AAA" defined in the netlist g is defined in the card file h, the AAA is converted into BBB, CCC, and DDD, respectively, and the new netlist f ("DID;BBB;"
"DID;CCC;" and "DID;DDD;"
("DID;BBB;","DID;CCC;"
“DID; DDD;”) is output.

Next, the second line (RONRI; AND;), which is the next line of the netlist g, is read, and the card file h is read.
The first line (AAA; BBB; CCC; DDD;). Since the signal name "AND" defined in the netlist g is not defined in the line of the card file h currently being read, the card file is defined or the card file is read sequentially up to the last line of the card file. Since the signal name "AND" defined in the net file g is not defined in the card file h, the line ("RONRI;AND;") is output as it is to the new net list f.

Next, the next line of the netlist g, that is, the third line (INPUT1; AA1;) is read, and the first line (AAA; BBB; CC) which is the first line of the card file h is read.
C; DDD;). The signal name “AA1” defined in the netlist g is the currently read card file h.
, The card file h is read in order up to the line defined in the card file h or the last line of the card file. The signal name “AA1” defined in the netlist g is the second line (AA
1; BB1; CC1; DD1;)
AA1 is converted into BB1, CC1, and DD1, respectively, and converted into a new netlist f (“INPUT1; BB1;”, “I
NPUT1; CC1; "and"INPUT1; DD
1; "). The same operation is performed up to the last line from the next line of the netlist g.

The preferred embodiment of the logic synthesis system of the present invention and a concrete example based thereon have been described above in detail. But,
It should be understood that the present invention should not be limited to only such examples, and that various modifications can be made without departing from the spirit of the present invention.

[0041]

As will be understood from the above description, the logic synthesis system of the present invention has various remarkable effects as described below.

First, since a plurality of netlists can be created by signal name conversion processing using a signal name corresponding card file as an input, one logic description language is created, and one logic synthesis operation is performed. You can easily create multiple netlists just by doing it once.

Second, even if the logic is changed, a plurality of netlists can be created only by modifying the logic description language for performing logic synthesis and the signal correspondence card file. It is not necessary to modify the logic description language.

Third, since the card file corresponding to the signal name is used, even if the logic is modified, a plurality of netlists can be obtained without modification by modifying one file of the logic description language and the card file corresponding to the signal name. To be able to create
Correction errors due to the intervention of acquisition work can be reduced.

[Brief description of the drawings]

FIG. 1 shows a preferred embodiment of a logic synthesis system according to the present invention.

FIG. 2 is a flowchart of a signal name conversion processing operation in the logic synthesis system of the present invention.

FIG. 3 is an explanatory diagram of a conventional logic synthesis system.

[Description of Signs] a Logic Description Language e Logic Synthesis g, f Netlist h Signal Name Corresponding Card File i Signal Name Conversion Processing

Claims (5)

[Claims] 1. A logic synthesis system for creating a plurality of netlists by logic synthesis using a logic description language,
A logic synthesis system for creating a plurality of netlists from one kind of logic description language by a signal name correspondence card file and a signal name conversion process. 2. A method according to claim 1, wherein said signal correspondence card file describes correspondence between a signal name of a logic description language, which is an input when creating a net list after logic synthesis work, and a signal name after conversion. The logic synthesis system according to claim 1, wherein: 3. Logic synthesis is performed based on a logic description language.
A second netlist is created, and a signal name conversion process is performed using the netlist and the signal file corresponding to the signal name.
A logic synthesis system for creating a plurality of netlists after the first. 4. A logic description language, logic synthesis and netlist, a signal name correspondence card file, and signal name conversion processing, wherein a plurality of netlists are created from one kind of logic description language. Logic synthesis system. 5. The logic synthesis system according to claim 1, wherein the logic description language and the signal corresponding card file can be modified when a logic change occurs.