JP2000222448A - Method for preparing netlist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make quickly retrievable a wiring related to correction on a netlist when circuit correction is reworked by setting to leave a described gate after performing function description including gate description, reading the function description by an automatic logical synthesis tool and performing a logical synthesis. SOLUTION: First, function description including gate description where the call name of a gate in which a signal corresponding to wiring whose name is desired to be left on a netlist becomes an output is specified is performed (S11). Subsequently, a logical synthesis undergoing such setting as to use the gate on which the cell name is specified as it is when optimized is performed (S12). And, the function description is read with an automatic logical synthetic tool and a netlist optimized by logical synthesis is prepared and outputted to a layout tool (S13). Thus, it is possible to quickly perform circuit correction by retrieving a wiring name because the wiring name about correction on the netlist can be corresponded as the wiring name of a signal name defined by the function description.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating a netlist, and more particularly to a method for creating a netlist by performing function description and logic synthesis for digital circuit design.

[0002]

2. Description of the Related Art When designing a digital circuit, a method of automatically synthesizing a gate-level circuit by applying a logic description to a functional description has become a mainstream in recent years. The function description is HD
The operation and function of the circuit are expressed in a text format using a language such as L (Hardware Description Language). One of the major features of this method is that it is expressed in a way that more closely resembles human thinking than conventional methods in which humans construct logic in detail. When this functional description is subjected to logic synthesis by an automatic logic synthesis tool, a circuit optimized with respect to area and speed is generated, and a netlist to be input for an automatic layout in the next step is output. The netlist describes circuit information (cells) having the minimum configuration and connection information between cells.

FIG. 3 shows a flowchart of an example of a conventional method. In the figure, first, a function description not including a gate description is performed (step 101). The reason for not writing the gate to be used in the function description is that if the gate to be used is specified, the number of optimization options is reduced accordingly, which may hinder the reduction of the circuit area. .

Subsequently, the function description without gate designation is subjected to logic synthesis to optimize the circuit (step 10).
2) Output a net list (step 103). As a result, for example, f = (((a & b) | c)
& D) | e (& indicates AND and | indicates OR), the result of the logical synthesis is as shown in FIG.

FIG. 4 is a circuit diagram visually representing the netlist generated in step 103. The input signals a, b, c, d, and e, the output signal f, and the gates G1, G
2, G3 and G4. n35, n36, n3
7 is a wiring name appropriately assigned by the automatic logic synthesis tool.
In the circuit diagram shown in FIG. 4, the input signals a and b are ANDed by the gate G1, the NOR of the AND output and the input signal c is calculated, and the result of the NOR is calculated as the wiring name n37.
Is input to the gate G2 via the wiring of (1) to perform a logical NOT operation.

Further, an output signal of the gate G2 is a wiring name n3.
6 is input to the gate G3 via the wiring of No. 6, where an AND operation is performed between the input signal d and the AND output of the AND signal and the input signal e, and the result of the NOR operation is calculated for the wiring name n35. The signal is input to the gate G4 via the wiring to perform a logical NOT operation to obtain an output signal f.

[0007]

However, in the above-mentioned conventional method, when a defect is found after the product is manufactured and the circuit needs to be corrected (reworked), a problem occurs that more time is required for the rework. . Generally, IC
In the case of circuit rework, a method that only corrects aluminum wiring is preferred, and corrections that change the number and configuration of gates are
It is considered desirable to minimize the time and cost of mask preparation and diffusion, as much as possible. This will be described with reference to FIG.
If the function description of No. 1 is rewritten, the logic synthesis in the subsequent step 102 is performed again, and the number and configuration of gates are changed. This means that the mask is formed in the entire diffusion step and the entire diffusion step is performed, and is a method that should be avoided as much as possible.

[0008] Therefore, usually, in the case of performing circuit correction, only the wiring information in the net list in which circuit connection information is described is modified, and a method is selected in which rework is completed only by correcting aluminum wiring. However, the wiring of the netlist generated by the conventional method is appropriately named by an automatic logic synthesis tool in logic synthesis. That is, since it is not possible to determine which wiring corresponds to which signal defined in the function description of step 101, it is necessary to start by checking which wiring corresponds to the signal relating to the correction. This causes an increase in rework time. In addition, it makes the logic synthesis difficult, resulting in an increase in rework time.

To explain this more specifically with reference to FIG. 4, a signal corresponding to (a & b) | c defined in the function description is given a wiring name of n36 after logic synthesis, and a signal corresponding to a & b is not obtained. Will disappear. That is, (a &
b) When rework is to be performed using a signal corresponding to | c, a search cannot be performed based on the wiring name, and a long time is required for the search. When rework is required using a signal corresponding to a & b, Since there is no corresponding signal, it takes time to prepare an alternative for correction.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a netlist creation method that allows a wiring related to a correction to be quickly searched on a netlist at the time of rework of a circuit correction by giving a name to a wiring defined in a functional description and leaving the name on the netlist. I do.

[0011]

In order to achieve the above object, according to the present invention, after a function description including a gate description is made, a setting is made to leave the described gate, and the function description is made by an automatic logic synthesis tool. By reading and performing logic synthesis, a netlist optimized in terms of area and speed is created.

Further, the present invention is characterized in that the function description is a function description in which a cell name of a gate from which a signal corresponding to a wiring whose name is to be left on the netlist is output is specified. According to the present invention, in the logic synthesis, a setting is made such that a gate whose cell name is specified in the function description is used as it is when optimizing, and the function description is read by an automatic logic synthesis tool to perform the logic synthesis. It is characterized by the following.
Further, the present invention is characterized in that the cell name of the gate is directly described in the function description, and the gate is determined to be used at the time of logic synthesis.

According to the present invention, after a function description including a gate description is made, the above described gate is set to remain and the function description is read by an automatic logic synthesis tool to perform logic synthesis. The intended gate output signal name can be left as the wiring name in the synthesized netlist.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a flowchart of an embodiment of a netlist creating method according to the present invention. First, a function description including a gate description in which a cell name of a gate which outputs a signal corresponding to a wiring whose name is to be left on the netlist is specified (step 11), and then the specified gate is optimized. Logic synthesis is performed so as to be used as it is at the time of conversion (step 12). Then, the function description is read by the automatic logic synthesis tool, a netlist optimized by the logic synthesis in step 12 is created, and output to the layout tool (step 1).
3).

This embodiment will be further described by taking as an example a case where a digital circuit identical to the digital circuit shown in FIG. 4 is designed. In the function description of step 11, AND of signal a and signal b is obtained. It is specified using the cell name that the wiring name of the output signal is g (for example, L312 AND (g, a, b)). That is, the specified cell names include the input signals a and b, the wiring names g of the output signals, and the types of gates.

Next, in the above functional description, the OR of the signal c and the signal corresponding to the wiring name g is specified, and the output of the output signal to the wiring having the wiring name h is clearly specified using the cell name (for example, L212 OR (h, c, g)), and finally f
= (H & d) | e. This is f = (((a & b) | c) & d) described in the prior art.
| E.

Subsequently, the function description is read by an automatic logic synthesis tool and optimization is performed. At this time, optimization is performed by using the cell names L312 and L212 of the gates whose wiring names g and h to be left in the netlist as output signal wirings as they are (for example, se).
t_dont_touch Enter the command L212. ). At this time, as described above, the automatic logic synthesis tool
Although a circuit optimized with respect to speed is generated, the cell with the specified cell name is left as it is, so that the wiring defined by the function description does not disappear and the wiring name remains as it is conventionally.

FIG. 2 is a circuit diagram visually representing a netlist created by the logic synthesis in step 12 described above. The input signals a, b, c, d and e and the output signals f and It comprises gates G11, G12, G13 and G14. On the netlist, the output wiring of the gate G11 is named g, and the output wiring of the gate G12 is named h.

In the circuit diagram shown in FIG. 2, the input signals a and b are ANDed by the gate G11, and the AND output is input to the gate G12 via the wiring of the wiring name g by the gate G12.
Is ORed with The output signal of the gate G12 is input to the gate G13 via the wiring having the wiring name h, where it is subjected to an AND operation with the input signal d, and the NOR output of the AND output and the input signal e is obtained. The result of the logical sum is input to the gate G14, a logical NOT operation is performed, and the output signal f
Get.

As described above, in this embodiment, after logic synthesis, a signal corresponding to a & b and a signal corresponding to (a & b) | c exist as wiring names g and h, respectively.
For this reason, when the circuit is to be corrected using the signal corresponding to a & b or the signal corresponding to (a & b) | c, the search can be easily performed by searching for the wiring names g and h, and the rework TAT Can be shortened.

[0021]

As described above, according to the present invention,
After the function description including the gate description is made, the settings described above are left to keep the described gate, and the function description is read by the automatic logic synthesis tool to perform the logic synthesis, thereby outputting the gate output intended in the netlist after the logic synthesis. Since the signal name is left as the wiring name, if only the wiring information in the netlist is modified and the circuit is corrected only by correcting the aluminum wiring, the wiring name related to the correction on the netlist is defined in the function description Since the corresponding signal name can be handled as a wiring name, by searching for the wiring name, the circuit can be quickly corrected, and the TAT of the rework time can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example in which the netlist created in FIG. 1 is visually represented;

FIG. 3 is a flowchart of an example of the related art.

FIG. 4 is a circuit diagram of an example in which the netlist created in FIG. 3 is visually represented;

[Explanation of symbols]

 11 to 13 Step G11 to G14 Gate a to e Input signal f Output signal g, h Wiring name

Claims (5)

[Claims] After performing a function description including a gate description,
Creating a netlist optimized with respect to area and speed by reading the function description by an automatic logic synthesis tool and performing logic synthesis by setting to leave the described gate. Method. 2. The function description according to claim 1, wherein the function description is a function description specifying a cell name of a gate from which a signal corresponding to a wiring whose name is to be left on the netlist is output. How to create a netlist. 3. The logic synthesis is performed by setting the gate whose cell name is specified in the function description to be used as it is when optimizing, and reading the function description by the automatic logic synthesis tool to perform logic synthesis. 3. The method according to claim 1, further comprising: 4. The netlist creating method according to claim 1, wherein a cell name of the gate is directly described in the function description, and the gate is determined to be used during the logic synthesis. 5. The gate cell name specified in the function description includes a gate type, a wiring name of an input signal and an output signal wiring of the gate in the cell name of the gate. How to create a netlist.