JP2924486B2 - Hierarchical structure expansion method for design data of integrated circuits. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for converting design data of an integrated circuit, and more particularly to a method for developing a hierarchical structure.

[0002]

2. Description of the Related Art At present, design data of an integrated circuit has a hierarchical structure. For example, FIG.
As shown in (a) and (b), the cell A is placed in the cell top.
And a hierarchical structure in which the cell B is included in the cell A. That is, a collection of pattern data repeatedly used in the design data of an integrated circuit or a collection of logically significant pattern data is defined as a cell, and the actual design data is created by referring to the cell. Create. By doing this,
The advantages of reducing the amount of design data and facilitating data management can be obtained.

At this time, as shown in FIG. 5, the design data of the integrated circuit expresses a hierarchical structure by having two types of data, ie, pattern data 14 and cell reference data 13 as cell data 12 for each cell. I do. The pattern data 14 is a coordinate expression of graphic data constituting an actual integrated circuit, and the cell reference data 13 is composed of a reference cell identifier and reference position coordinates.

However, when processing such as data conversion processing for a reticle drawing apparatus or layout verification processing is performed on design data having such a hierarchical structure, expansion processing is performed on all the hierarchical structures in advance, and the hierarchical structure is processed. After that, you have to do that. In addition, the recent increase in the scale of the integrated circuit has caused an increase in the ratio of processing time such as data conversion processing for the reticle drawing apparatus and layout verification processing.

In this type of conventional processing, the cell at the top of the hierarchical structure specified in advance is set as the current target cell, and the hierarchical structure expansion processing is performed recursively in the following procedure according to FIG.

First, the data of the current target cell is searched by the input search means 15 on the input data 1 from the external storage unit. Next, the pattern data of the currently targeted cell is subjected to coordinate conversion in accordance with the reference position coordinates in the cell reference data of the upper cell, and the graphic information is operated by the graphic operating means 5a. Will output. Finally,
The cell of the cell identifier of each cell reference data of the currently targeted cell is newly set as the current target cell by the hierarchy setting means 16.

[0007] The above three-stage processing is performed recursively on all cells in order as in the example shown in FIG. That is, from cell top (0) to cell A
(1), cell B (2), (3), and the next cell A
(4), cells (5), (6)... Cell A (10) and cells B (11), (12) are sequentially processed.

[0008]

In the above-described conventional method of expanding the hierarchical structure of the design data of an integrated circuit, in the above-described method of expanding the design data of the integrated circuit, every time a cell reference appears in the pattern data of the cell that repeatedly appears on the input data, the same cell is applied to the same cell. It is necessary to operate the graphic information, and the operation is performed a plurality of times for the same graphic, resulting in an increase in the processing time and an increase in the search time for the input data on the external storage. That is, in the conventional method, the hierarchical structure of the cells is sequentially obtained from the input data on the external storage during the hierarchical expansion processing. Therefore, each processing is considered to be essential. It has been very difficult to substitute other means because the use of limited internal memory is avoided as much as possible.

An object of the present invention is to solve these problems,
It is an object of the present invention to provide a method of expanding the design data of an integrated circuit into a hierarchical structure, which can speed up the process of expanding the design data into a hierarchical structure.

[0010]

Means for Solving the Problems The configuration of the hierarchical decomposition method of the design data of the integrated circuit of the present invention, have a hierarchical data
First step and, the second step of the first process data input in step temporarily stored in the internal storage unit, said internal storage means is an external input storage unit design processing target data of the integrated circuit Hierarchical structure of data read from
Third step and, by operating the graphic information of the data read from the internal storage means and the third step of the deployment process the hierarchy structure information for each converted actual definition data down the hierarchy
Creates decompressed data according to the cell hierarchy obtained in
The method includes a fourth step and a fifth step of outputting, to the external storage unit, the data whose operation has been completed in the fourth step .

[0011]

FIG. 1 is a flow chart for explaining an embodiment of the present invention. The present embodiment includes an input unit 2 for inputting input data 1, a hierarchical development unit 3, an internal storage unit 4, a graphic operation unit 5, and an output unit 6. Input means 2
Input the pattern data of the designated cell and the input data 1 of the cell reference data independently of each other.

As shown in FIG. 2, the hierarchy expanding means 3 first requests the input means 2 for cell reference data for each cell in step 1 (S1), and stores the result in the internal storage means 4, Next, in step 2 (S2), the depth of the hierarchical structure is changed by one step as shown in FIG. <br/> Convert to a level (hierarchy) .

The graphic operating means 5 performs necessary graphic data operations on the pattern data of each cell input by the input means 2 and converts the result according to the hierarchical structure of the cells obtained by the hierarchical developing means 3. The developed data of the reference point is created, and the data is passed to the output means 6. The output means 6
The requested data is output to the output data 7 on the external storage unit.

Next, the overall operation of this embodiment will be specifically described. As input data, FIG.
When the layout data of the integrated circuit having the hierarchical structure shown in (a) and (b) is input, the data on the internal storage means 4 at the end of step 1 (S1) of the hierarchical developing means 3 is transferred to the input means 2 Is only the cell reference data shown in FIG. 4, and the data on the internal storage means 4 at the end of step 2 (S2) of the hierarchy expanding means 3 is as shown in FIGS. 3 (a) and 3 (b). in the cell top and the cell a, cell B from one stage
Only made cell reference data level (hierarchy) made. The graphic operation means 5 receives the pattern data for each cell from the input means 2, performs a required graphic operation only once on each pattern data, performs a development process according to the reference coordinates in FIG. Pass the data to 6.

[0015]

As described above, according to the present invention, there is no need to use a graphic operation means for each cell reference, and it is only necessary to search cell pattern data to input data in an external storage unit once. This has the effect that the processing time can be reduced about 10 times.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a flowchart of a hierarchy expanding means of FIG. 1;

FIG. 3 is a schematic diagram illustrating a one-layer structure of intermediate data used in FIG. 1;

FIG. 4 is a schematic diagram illustrating a hierarchical structure of general input data.

FIG. 5 is a schematic diagram illustrating the input data of FIG. 4 in blocks.

FIG. 6 is a flowchart illustrating a conventional hierarchical structure development method.

FIG. 7 is a schematic diagram when the flow of FIG. 6 is applied to FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input data 2 Input means 3 Hierarchical development means 4 Internal storage means 5, 5a Graphic operation means 6 Output means 7 Output data 11 All input data 12 Cell data 13 Cell reference data 14 Pattern data 15 Input search means 16 Hierarchy setting means

Claims (1)

(57) [Claims] A first step of inputting design processing target data of an integrated circuit having data of a hierarchical structure from an external storage unit, and internally storing the processing data input in the first step.
Third step of the second step of temporarily storing the unit, the internal storage unit expansion process the hierarchical structure information the hierarchical structure of the data read out for each converted actual definition data one step in the hierarchy from When, a fourth step of creating decompressed data by operating the graphic information of the data read out from said internal storage means according to the cell hierarchy obtained in the third step, and operation end in the fourth step And a fifth step of outputting data to the external storage unit.