JP2705549B2 - Integrated circuit design data conversion apparatus and hierarchical data expansion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for converting design data of an ultra-large scale integrated circuit.
More particularly, the present invention relates to an integrated circuit design data conversion device and a method of hierarchically expanding the data .

[0002]

2. Description of the Related Art Conventionally, design data of an integrated circuit used in a CAD device or the like has a hierarchical structure.
That is, in the design data of an integrated circuit, a collection of pattern data that is repeatedly used in the design data or a collection of logically significant pattern data is defined as a cell, and when the actual design data is created, the defined cell is referred to. I do it. In addition, when the same cell is referred to, the reference position is regularly arranged, in particular, by expressing the regular arrangement information to the cell.

FIG. 3 is a configuration diagram of general input design data. As shown in FIG. 3, general input design data 14
Includes cell A information 15 composed of one cell A and cell A information 16 composed of four cells A. This is to reduce the amount of design data and facilitate data management.

FIG. 4 is a configuration diagram of general input data. As shown in FIG. 4, the integrated circuit input data 17 has three types of data of cell reference data 19, array information data 20, and pattern data 21 for each cell data 18 representing each cell. By having these three types of data for each cell, a hierarchical structure of the data is expressed. Among them, the pattern data 21 is a coordinate expression of graphic data constituting an actual integrated circuit, and the cell reference data 1
Reference numeral 9 denotes an identifier of a cell to be referred to and reference position coordinates, and array information data 20 denotes arrangement information of the cell to be referred in the X and Y-axis directions.

That is, when the input data 17 is the cell A information 15 described above, the input data 17 is composed of cell reference data 19, which is arrangement information of the cell A, 1 × 1 array information data 20, and pattern data 21. When the data 17 is the cell A information 16 described above, the data 17 is composed of cell reference data 19 which is arrangement information of the cell A, 4 × 1 array information data 20 and pattern data 21.

However, when the design data having such a hierarchical structure is subjected to processing such as data conversion processing or layout verification processing for a reticle drawing apparatus as a CAD apparatus, expansion processing is performed for all hierarchical structures in advance. The above-mentioned processing must be performed after a state without a hierarchical structure. For this reason, as the scale of the integrated circuit increases, the proportion of processing time such as data conversion processing for the reticle drawing apparatus or layout verification processing increases.

FIG. 5 shows a CAD for explaining an example of the prior art.
It is a block diagram of an apparatus. As shown in FIG.
In the AD device 1a, an input unit 2 for independently assigning pattern data and cell reference data of a designated cell based on input data, and inputting cell reference data from the input unit 2 to expand the data hierarchically. Hierarchy development unit 3a
A storage device 8 for temporarily storing pattern data input from the input unit 2, a graphic operation unit 9 for operating graphic data based on the pattern data from the storage device 8, a development result and a graphic from the hierarchical development unit 3a. An output unit 10 that creates output data based on the operation result of the operation unit 9 and outputs the output data to the outside as output data. Also, the hierarchy developing unit 3a
Is an input stage 4 for requesting cell reference data from the input unit 2 for each cell, an internal memory 5 for storing a result obtained from the input stage 4, and other cells for a predetermined top-level cell. And a change stage 6 for changing the hierarchical structure so that the data is directly referred to. Further, the graphic operation unit 9 performs necessary graphic data operations on the pattern data of each cell supplied from the storage device 8, and the output unit 10 outputs the result to the hierarchy developing unit 3
The expanded data of each reference point is created based on the hierarchical structure of the cell obtained by a. Hereinafter, the input data and the intermediate data will be described with reference to FIGS.

FIGS. 6A and 6B are diagrams showing the hierarchical structure of the input data in FIG. FIG. 6 (a), (b)
As shown in the figure, the input data here is layout data of a three-layer structure as an example, and the top cell top 22
And the middle cell A (4 × 1) 23 and the lowest cell B
(1 × 2) 24. When such layout data is input in FIG. 5 described above, the data stored in the internal memory 5 of the hierarchical development unit 3a is only three-layer cell reference data.

FIGS. 7A and 7B are diagrams showing the hierarchical structure of the intermediate data in FIG. FIGS. 7A and 7B
As shown in FIG. 5, this intermediate data is an example in which four cells B13a are present in the cell A12 in the cell top 11, and in FIG.
The data read from the internal memory 5 is as shown in FIG.
Only the cell reference data shown in FIG. In this case, when the hierarchical structure is changed so that a cell of a certain hierarchy is directly referred to a previously specified top cell, only the relationship between the hierarchy and the top cell is taken into consideration. , All the cell reference data is stored in the internal memory 5.

On the other hand, the graphic operation unit 9 shown in FIG.
Receives pattern data from the storage device 8 for each cell,
A required graphic operation is performed only once on each pattern data, and the output unit 10 outputs the result of the expansion processing based on the reference coordinates shown in FIG.

[0011]

According to the above-described conventional method of expanding the hierarchy of integrated circuit design data, when a hierarchical structure is changed so that a cell of a certain hierarchy is directly referred to a top-level cell specified in advance. Since only the relationship between the hierarchy and the top cell is considered, the array information of the cell above the hierarchy is lost. Conventionally, in order to avoid this, FIG.
As shown in the cell B13a of FIG. 13B, there is a disadvantage that the amount of intermediate data increases, the amount of data in the internal memory increases, and the processing time for hierarchical development becomes enormous.

An object of the present invention is to provide an integrated circuit design data conversion apparatus and a data hierarchical expansion method that can reduce the amount of data in such an internal memory and reduce the processing time for hierarchical expansion.

[0013]

According to the present invention, there is provided an integrated circuit design data conversion apparatus , comprising: an input unit for inputting processing target data having pattern data and cell reference data; and the cell reference input from the input unit. A hierarchical expansion unit having an internal memory for storing data and a hierarchical structure search unit for performing hierarchical expansion based on the cell reference data of the internal memory and searching for array information data; and the pattern input from the input unit. A storage device for temporarily storing data, a graphic operation unit for reading out the pattern data on the storage device and performing various graphic operations, and an output based on a development result of the hierarchical development unit and an operation result of the graphic operation unit An output unit for creating data, and a cell having array information while the hierarchy is reversed from the lowest to the highest in the hierarchy expanding unit. Is present, the information is added to the cell reference information of the cell of current interest. Also, a method for hierarchically expanding integrated circuit design data according to the present invention.
Is the processing target that has pattern data and cell reference data
Storage for storing data in internal storage means via an input unit
Step, the cell reference stored in the internal storage means.
Hierarchical Structure Searching Array Information Data Based on Reference Data
Hierarchical expansion through hierarchical expansion unit with search unit
Step and the pattern stored in the internal storage means.
Graphic operation for performing various graphic operations on the data with the graphic operation unit
Working step and the hierarchical exhibition obtained in the hierarchical expanding step.
Open result and figure operation obtained in the figure operation step
Creating output data at the output unit based on the result; and
And in the hierarchy expanding step, the hierarchy is changed from the lowest to the highest.
While the cell is moving backwards,
If it exists, the information is referred to the cell of the cell of current interest.
It is configured to be added to the illumination information.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a CAD apparatus for explaining an embodiment of the present invention. As shown in FIG. 1, in a CAD apparatus 1 according to the present embodiment, an input unit 2 for separately assigning pattern data and cell reference data of a designated cell based on input data, and a cell reference from the input unit 2. A hierarchical expansion unit 3 for inputting and storing data and expanding the data in a hierarchy, a storage device 8 for storing pattern data from the input unit 2, and a pattern data for each cell pattern from the storage device 8. It is composed of a graphic operation unit 9 for operating data, and an output unit 10 for outputting to the outside as output data based on the hierarchical development information from the hierarchical development unit 3 and the operation result from the graphic operation unit 9. Moreover,
In this embodiment, the hierarchy developing unit 3 includes an input stage 4 for requesting cell reference data from the input unit 2 for each cell, an internal memory 5 for storing a result obtained from the input stage 4, and In addition to the change unit 6 for changing the hierarchical structure so that the other cells are directly referred to the highest cell, a hierarchical structure search unit 7 is provided. Therefore, this embodiment
Hierarchy expansion procedure in pattern data and cell reference
The data to be processed having data is internally recorded via the input unit 2.
Store in internal memory 5 or storage device 8 as storage means
Storage step and cell stored in the internal storage means
Hierarchical structure for searching array information data based on reference data
Floor to be hierarchically expanded through the hierarchical expansion unit 3 having the structure search unit 7
Layer development step and stored in the above-mentioned internal storage means
Various graphic operations are performed on the pattern data by the graphic operation unit 9.
The figure operation step and the hierarchical
Hierarchy expansion results and figure manipulation steps
The output unit 10 creates output data based on the result of the graphic operation.
And the hierarchy is expanded to the lowest level in the hierarchy development step.
Hold array information while moving backwards from
If there is one cell, the cell whose information is currently focused
To the cell reference information.

That is, in the hierarchy expanding section 3, first, the input stage 4 requests cell reference data for each cell, and stores the result in the internal memory 5. Next, in the change stage 6, the hierarchical structure is changed so that the other cells are directly referred to the top cell specified in advance. At this time, the hierarchical structure search unit 7 is used to go up the cell hierarchy from the cell hierarchy currently being developed to the highest cell, and if there is an array represented in the upper cell, expand the array information. Assign to the cell inside.

In short, a hierarchical structure searching section 7 is provided in the hierarchical expanding section 3 for expanding the hierarchical structure based on the cell reference data of the input data, and the array information is stored while the hierarchical level is reversed toward the top. If there is a cell having, the information is added to the cell of current interest. This makes it possible to reduce the intermediate data of the lower cell.

Hereinafter, a case where layout data of an integrated circuit having a three-layer structure is input as input data, as in the conventional example, will be described with reference to FIG.

FIGS. 2A and 2B are diagrams showing the hierarchical structure of the intermediate data in FIG. First, FIG.
At the point in time when the input data such as (a) and (b) has been input from the input unit 2 to the input stage 4, the data in the internal memory 5 is only the intermediate cell reference data, The data is only the pattern data of each cell. That is, as shown in FIGS. 2A and 2B, when the cell B (1 × 2) 13 is expanded, the hierarchical structure search unit 7 reverses the cell hierarchy toward the cell top 11 as the highest cell. , A cell A (4 × 1) 12 on the way
Is added when the cell B (4 × 2) 13 is output.

In the following, similarly to the conventional example, the graphic operation unit 9 performs the required graphic operation only once on the pattern data of each cell received from the storage device 8, and the output unit 10 transmits the Output processing is performed based on the received reference coordinates.

As described above, according to the present embodiment, the intermediate data amount of the cell B, which is the lower cell, is reduced by one in comparison with the conventional method.
/ 4. That is, if there are many cells having the array information in the input data depending on the memory type or the like, the intermediate data amount can be reduced to 1/10000 or less. For this reason, the processing time for hierarchical development can be greatly reduced, and high-speed processing can be realized.

[0021]

As described above, the integrated circuit design data conversion apparatus and the data hierarchical expansion method of the present invention have a hierarchical structure search section provided in the hierarchical expansion section.
Since the amount of intermediate data of the lower cells can be reduced, there is an effect that the processing time of hierarchical development can be reduced for data in which many cells having array information exist in the input data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a CAD apparatus for explaining an embodiment of the present invention.

FIG. 2 is a diagram illustrating a hierarchical structure of intermediate data in FIG. 1;

FIG. 3 is a configuration diagram of general input design data.

FIG. 4 is a configuration diagram of general input data.

FIG. 5 is a block diagram of a CAD apparatus for explaining an example of the related art.

FIG. 6 is a diagram illustrating a hierarchical structure of input data in FIG. 5;

FIG. 7 is a diagram illustrating a hierarchical structure of intermediate data in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CAD apparatus 2 Input part 3 Hierarchical development part 4 Input stage 5 Internal memory 6 Change stage 7 Hierarchical structure search part 8 Storage device 9 Graphic operation part 10 Output part 11 Cell top 12 Cell A 13 Cell B 17 Input data 18 Cell data 19 Cell reference data 20 Array information data 21 Pattern data

Claims (2)

(57) [Claims] An input unit for inputting processing target data having pattern data and cell reference data; an internal memory for storing the cell reference data input from the input unit; and the cell reference data of the internal memory A hierarchical development unit including a hierarchical structure search unit for performing a hierarchical development based on a search for array information data; a storage device for temporarily storing the pattern data input from the input unit; A graphic operation unit that reads out pattern data and performs various graphic operations; and an output unit that creates output data based on a development result of the hierarchical development unit and an operation result of the graphic operation unit. If there is a cell with array information while the hierarchy is reversed from the bottom to the top, the cell reference of the cell of current interest An integrated circuit design data conversion device for adding information to information. (2) Contains pattern data and cell reference data
Data to be processed is stored in the internal storage means via the input unit
Storing step, and storing in the internal storage means.
Searching array information data based on the cell reference data
Hierarchical expansion through a hierarchical expansion unit with a hierarchical structure search unit
Hierarchies expanding step, and storing in the internal storage means.
Perform various graphic operations on the pattern data with the graphic operation unit.
Figure operation step to be performed and
Hierarchical expansion result and the figure operation step
Create output data in the output unit based on the results of figure manipulation
And the hierarchy is expanded to the bottom in the hierarchy expanding step.
Array information while moving backward from top to top
If there is a cell that has
Integrated circuit to be added to cell reference information of a cell
Hierarchical expansion method of design data.