JP2001091228A - Pattern inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern inspection device, capable of conducting stable detecting operation by reducing influence of noise in detecting defects in a repeated pattern, without previously giving an ideal pattern. SOLUTION: According to plural (three) unit patterns (e.g., PA, PB, PC) contained in an inspection image S formed by a repeated pattern, a reference image PI is automatically generated as an ideal pattern. A defect is determined according to the result of comparison between the generated ideal pattern and the unit patterns contained in the inspection image S. Since the automatically generated ideal pattern is generated by using plural unit patterns, influence of noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern inspection apparatus applicable to inspection of pattern defects in a color filter having a repetitive pattern, a shadow mask, a printed wiring board, a semiconductor wafer, and the like.

[0002]

2. Description of the Related Art In an inspection object having a repetitive pattern (for example, a color filter, a shadow mask, a printed wiring board, a semiconductor wafer, etc.), a defect existing in the repetitive pattern is detected without providing an ideal pattern in advance. There is a technique for automatically detecting a defect using a plurality of unit patterns included in an image to be inspected. For example, as shown in FIG. 22, there is a technique for comparing a pattern PA and a pattern PB, which are unit patterns in a repeated pattern, and detecting a different portion as a defect. In addition, such a comparison alone
Since it is unknown whether the defect exists in the pattern PA or the pattern PB, there is, for example, a technique described in Japanese Patent Publication No. 6-56293 as a technique for solving this. This consists of three unit patterns PA, PB, PC
, The pattern PA and the pattern PB are compared (comparison result AB), the pattern PC and the pattern PB are compared with the comparison (comparison result CB), and the comparison results AB and CB are further compared. By the pattern P
Only the defect existing in B is specified. As shown in FIG. 23, these comparison operations are performed by binarizing (detecting as normal or defective) by dividing the absolute value of the difference between the gradation values of each pixel of both patterns by a threshold value. Will be

[0003]

However, in the above technique, when comparing two unit patterns,
Although the inspection image obtained by the image input unit is used,
This inspection image often contains noise,
The comparison result of the two unit patterns (by binarizing the absolute difference value) is susceptible to noise. In other words, when the above technique is applied to an image to be inspected that contains a lot of noise, the defect detection rate is reduced by overlooking a part that is originally a defect, or conversely, an erroneously detected part that is originally normal is defective. There is a problem in that an excessive detection rate is increased and the detection result becomes unstable.

In view of the above problem, the present invention can perform a stable detection operation by reducing the influence of noise when detecting a defect existing in a repetitive pattern without giving an ideal pattern in advance. It is an object to provide a pattern inspection device.

[0005]

According to a first aspect of the present invention, there is provided a pattern inspection apparatus for performing a defect inspection of a repetitive pattern. An input unit, an ideal pattern generating unit that generates an ideal pattern based on a plurality of unit patterns included in the inspection image, and a comparison result of comparing the generated ideal pattern with a unit pattern included in the inspection image. And comparing and judging means for judging a defect of the unit pattern in the image to be inspected.

According to a second aspect of the present invention, in the pattern inspection apparatus according to the first aspect, unit patterns in the inspection image are sequentially selected as inspection unit patterns, and the ideal pattern is It is generated based on a unit pattern to be inspected and a unit pattern other than the unit pattern to be inspected.

According to a third aspect of the present invention, in the pattern inspection apparatus of the first aspect, unit patterns in the image to be inspected are sequentially selected as unit patterns to be inspected, and the ideal pattern is It is generated based on a plurality of unit patterns other than the unit pattern to be inspected.

According to a fourth aspect of the present invention, in the pattern inspection apparatus according to the first or second aspect, the unit pattern other than the unit pattern to be inspected used for generating the ideal pattern is the same as the pattern inspection apparatus. It is a unit pattern having a predetermined relative positional relationship to the unit pattern to be inspected.

According to a fifth aspect of the present invention, in the pattern inspection apparatus according to the fourth aspect, the unit pattern other than the unit pattern to be used for generating the ideal pattern is the unit pattern to be inspected. Is a unit pattern adjacent to.

A pattern inspection apparatus according to a sixth aspect of the present invention is the pattern inspection apparatus according to the fourth or fifth aspect, wherein a unit pattern exists at a position in the relative positional relationship with respect to the unit pattern to be inspected. If not, the ideal pattern is generated by substituting another unit pattern actually existing in the inspection image.

According to a seventh aspect of the present invention, in the pattern inspection apparatus according to the sixth aspect, the ideal pattern generating means determines that the unit pattern near one end of the inspection image is the inspection target. Means for generating the ideal pattern using a unit pattern adjacent to the other side of the image to be inspected with respect to the unit pattern to be inspected by changing the relative positional relationship when the unit pattern is used. It is characterized by having.

According to an eighth aspect of the present invention, in the pattern inspection apparatus according to any one of the first to seventh aspects, the comparing and judging means determines a difference between the image to be inspected and the ideal pattern. Means for obtaining a series of signal trains obtained for each unit pattern, and extracting, from among the fluctuating sections appearing in the series of signal trains, a fluctuating section having an absolute value equal to or greater than a predetermined threshold, thereby obtaining a unit pattern having a defect. And a position specifying means for specifying the position of (1).

According to a ninth aspect of the present invention, in the pattern inspection apparatus according to any one of the first to seventh aspects, the ideal pattern generating means sequentially converts an image signal of the image to be inspected into a unit pattern. And by delaying the image signal of the image to be inspected by a delay time that is an integral multiple of the repetition period of the unit pattern,
Means for obtaining a plurality of delayed inspected image signals having different delay times from each other, and combining two or more signals from a set consisting of the image signal of the inspected image and the plurality of delayed inspected image signals. Means for obtaining a signal of the ideal pattern;
It is characterized by having.

According to a tenth aspect of the present invention, there is provided a pattern inspection apparatus comprising:
2. The pattern inspection apparatus according to claim 1, wherein the ideal pattern generation unit is capable of generating a plurality of ideal patterns based on different combinations of unit patterns included in the image to be inspected, and A defect of the unit pattern to be inspected is determined by comparing at least two of the plurality of ideal patterns with a unit pattern to be inspected included in the image to be inspected.

[0015]

<First Embodiment> FIG. 1 is a schematic diagram showing a configuration of a pattern inspection apparatus 1 (1A) according to a first embodiment of the present invention. The pattern inspection apparatus 1A includes: an XY table 3 on which an object 2 to be inspected is placed;
A drive unit 4 including motors 4a and 4b for driving the table 3 in the X and Y directions, respectively, and a CCD line sensor 5 are provided. Here, it is assumed that a semiconductor wafer W is inspected as the object 2, and FIG. 2 is a plan view showing details thereof. As shown in FIG. 2, the semiconductor wafer W
It has a structure in which “die” 2a, which is a plurality of unit patterns, is repeatedly arranged in a matrix in the X direction and the Y direction. Also, the pattern inspection apparatus 1A
Includes an image input processing unit 10 for performing input processing of an image to be inspected obtained through the CCD line sensor 5, and the image input processing unit 10 inputs the image to be inspected in cooperation with the CCD line sensor 5. It functions as a test image input means.

Here, the CCD line sensor 5 moves in the Y direction (+) relative to the object 2 with the movement of the XY table 3 in the Y direction (-), and moves on the object 2 in the Y direction. Scanning is performed at a constant speed at (+). The inspection image S is obtained by such scanning in the Y direction. Then, a pattern inspection operation described later is performed on the obtained inspection image S. Thereafter, the CCD line sensor 5 relatively moves in the X direction (+) with respect to the target object 2 by a predetermined width (for example, the width xa), and then relatively moves in the Y direction (-) to scan. By doing so, a similar inspection image S can be obtained. Further, by sequentially repeating the moving operation in the X direction (+) and the scanning operation in the Y direction (+,-), a similar inspection image S is obtained, and the pattern inspection operation can be repeatedly performed. it can.

The size of the inspection image S obtained by such scanning in the Y direction in the X direction is determined by the CCD line sensor 5.
For example, when the effective width xa and the unit pattern width xb (FIG. 2) are the same, each scanning operation in the Y-direction depends on the effective width xa (FIG. 1). Die 2
It is possible to obtain the inspection image S including the whole of a in the X direction. When the width xa is larger than the width xb of the unit pattern, for example, when the width xa is n times the width xb (n> 1), n dies 2a are scanned by one scanning operation in the Y direction. An image S to be inspected in the X direction can be obtained. Conversely, when the effective width xa is smaller than the width xb of the unit pattern, the inspection image S obtained by one scanning operation in the Y direction
Includes only a part of each die 2a in the X direction.

As described above, although the width of the inspection image S in the X direction differs depending on the size of the effective width xa, the die 2a, which is a unit pattern, is always present in the Y direction, which is the scanning direction. The image repeatedly appears at a predetermined cycle. The cycle in this case is also a spatial cycle in which the size yb (see FIG. 2) of the die 2a in the Y direction is one unit (unit), and when the CCD line sensor 5 scans at a constant speed, the CCD line Sensor 5 is at distance yb
At a predetermined speed v (yb / v) is 1
It can also be considered as a time period of a unit. As described above, the inspection image S is obtained as an image including the periodic repetition of the unit pattern in the Y direction which is the scanning direction.

The pattern inspection apparatus 1A includes an ideal pattern generation unit 30A (30) that generates an ideal pattern based on a plurality of unit patterns included in the inspection image S;
A comparison / determination unit 50A (50) for determining a defect by comparing the generated ideal pattern with each unit pattern included in the inspection image is provided.

FIG. 3 is a functional block diagram showing a specific configuration of the ideal pattern generation unit 30A and the comparison and determination unit 50A. FIG. 4 is a diagram showing an outline of each image signal obtained in each operation of a specific pattern inspection. FIG. FIG. 4 shows a case where a defect DT exists in the unit pattern PB. The defect DT has an original image S (that is, the inspection image S) assuming that the defect DT has a relatively large gradation value with respect to surrounding pixels. Has been detected. In FIG. 4, for simplicity, each image signal is represented as a one-dimensional image signal. This is because an image obtained by a single image sensor of the CCD line sensor 5 configured by arranging a plurality of image sensors in the X direction scans the object 2 (for example, from point E to point F). Signal. Below,
A more specific configuration and pattern inspection operation of the pattern inspection apparatus 1 will be described with reference to these drawings.

In the first embodiment, a case will be described in which an average (addition average) of three unit patterns of the obtained image to be inspected S is obtained to generate a reference image PI as an ideal pattern. In order to generate the reference image PI, an ideal pattern generation unit (or a reference image generation unit)
30A is a one-cycle delay circuit 31A, as shown in FIG.
32A, an addition circuit 36A, and a division circuit 38A. The one-cycle delay circuit 31A generates an image SD1 obtained by delaying the original image S by one cycle, and generates a one-cycle delay circuit 32A.
Generates an image SD2 obtained by further delaying the image SD1 by one cycle. Therefore, as shown in FIG.
1 is one cycle delayed from the original image S, and the image SD2
Is delayed by two periods with respect to the original image S. Therefore, the image SD1 is also called a one-cycle delayed image SD1, and the image SD2 is also called a two-cycle delayed image SD2.

The adding circuit 36A adds these three images S, SD1 and SD2, and the dividing circuit 38A divides (divides) the addition result of the adding circuit 36A by three. Thereby, the reference image PI can be obtained. That is, the reference image PI is obtained by calculating the average value of the tone values of the corresponding pixels of the original image S, the one-cycle delayed image SD1, and the one-cycle delayed image SD2 obtained at each moment. Here, PI = (S + SD1 + SD
2) / 3. The addition circuit 3
The division circuit 6A and the division circuit 38A function as synthesizing means for synthesizing the image S to be inspected, the one-cycle delayed image SD1, and the two-cycle delayed image SD2.

The reference image PI is an image in which unit patterns repeatedly appear, and each unit pattern is an “ideal pattern”. Even when the image S to be inspected includes noise, the influence of the noise component included in the image S to be inspected is obtained by calculating the average of a plurality (here, three) of unit patterns (in this case, Is 1 /
3) It is possible to reduce and generate a pattern having a more ideal image signal. As described above, the following comparison operation (and, consequently, the defect detection operation) is performed using the ideal pattern in which the influence of noise is reduced, so that the influence of noise on the detection result is reduced, and stable defect detection is possible. become. Note that the “ideal pattern” is not given in advance prior to the pattern inspection, but is generated automatically from the inspection image S.

Then, using the reference image PI, which is an image repeatedly including the ideal pattern, a comparison / determination operation regarding a defect by the comparison / determination unit 50A is performed. Comparison judgment unit 50
A has a comparison circuit 52A.
Performs a defect inspection of the inspection target image S by performing a comparison operation between the reference image PI and the one-cycle delayed image SD1. Specifically, first, the one-cycle delayed image SD1 and the reference image PI
Is obtained, and the absolute value of each gradation value of the difference image is obtained. Then, binarization is performed using the threshold value TH, and the threshold value T
By detecting a portion having a value equal to or greater than H as a defect, a comparative determination operation regarding the defect is performed.

Here, this ideal pattern corresponds to a pattern obtained by averaging the gradation values of the corresponding pixels for three spatially adjacent unit patterns. For example, as shown in FIG. 4, at a time point two cycles after the imaging time of the unit pattern PA, the unit pattern PC in the original image S, the unit pattern PB in the one-cycle delayed image SD1, and the two-cycle delayed image Image signals relating to the unit pattern PA in SD2 are obtained at the same time, and the reference image PI is the average of these, that is, (PC + PB + PA)
/ 3. Then, by comparing the ideal pattern (reference image PI) with the unit pattern PB in the one-cycle delayed image SD1 obtained at the same time, the above-described comparison determination operation is performed. In this case, The defect DT existing in the unit pattern PB has been detected as a defect by threshold processing.

That is, when a predetermined unit pattern (for example, PB) in the inspection image S is to be inspected, a predetermined unit pattern (here, spatially) located near the unit pattern (PB) is used. An ideal pattern is generated by using three adjacent unit patterns PA, PB, and PC), and the ideal pattern is compared with the unit pattern (PB) to be inspected, thereby obtaining a defect of a predetermined unit pattern (PB). This corresponds to detection being performed.

As described above, each ideal pattern is a unit pattern to be inspected (hereinafter, "unit pattern to be inspected").
) Is generated using a predetermined unit pattern existing in the vicinity (here, adjacent position) of the inspection image. Therefore, even when the unit pattern in the inspection image gradually changes in the scanning direction, An ideal ideal pattern can be generated. For example, even when the size of each unit pattern itself or the size of a predetermined portion in each unit pattern gradually changes (increases or decreases) in the scanning direction, the influence of the change is minimized. It is possible to generate an ideal pattern by suppressing such a pattern.

The reference image PI includes at least two images (in this case, the original image S, the one-cycle delayed image SD1, and the two-cycle delayed image) of at least one delayed image and the image to be inspected obtained at each instant. (The three images SD2) are generated in real time. The above-described comparison and determination operation is performed on the one-period delay image SD1 and the reference image PI at each moment as needed. After the above-described defect detection operation on the unit pattern PB, the unit patterns PC and PD are used.
Are sequentially performed. Therefore,
Despite being delayed by one cycle from the inspection image S, defect detection results for each unit pattern included in the inspection image S are sequentially generated in real time. That is,
By using the reference image PI as an ideal pattern at each predetermined moment, the pattern inspection can be performed in real time.

In the above description, the ideal pattern is generated by calculating the average of three patterns. However, the ideal pattern may be generated by calculating the average of four or more patterns. . By calculating an average using many patterns to generate an ideal pattern, it is possible to further reduce the influence of noise.

<Second Embodiment> In the first embodiment, three adjacent patterns including a unit pattern to be inspected are included.
Although the reference image PI as an ideal pattern is generated using one unit pattern, the present invention is not limited to this. For example, the reference image PI as an ideal pattern may be generated using unit patterns on both sides of the pattern to be inspected. In the second embodiment, such a case will be described.

The pattern inspection apparatus 1B according to the second embodiment comprises:
Except for the ideal pattern generation unit 30B, it has the same configuration as the pattern inspection apparatus 1A of the first embodiment,
Here, differences will be mainly described.

FIG. 5 is a functional block diagram showing a specific configuration of the ideal pattern generation section 30B and the comparison / determination section 50B. FIG. 6 is an explanatory diagram showing an outline of an image signal obtained in each specific pattern inspection operation. It is.

As shown in FIG. 5, the ideal pattern generator 30B includes one-cycle delay circuits 31B and 32B,
B and a division circuit 38B. The one-cycle delay circuit 31B generates a one-cycle delay image SD1, and the one-cycle delay circuit 32B generates a two-cycle delay image SD2. Then, the adder circuit 36B adds the image to be inspected S and the two-cycle delayed image SD2, and the divider circuit 38B divides (divides) the addition result of the adder circuit 36B by 2, thereby obtaining the reference image P.
Get I. That is, the reference image PI is obtained by obtaining the average value of the tone values of the corresponding pixels of the original image S and the two-cycle delayed image SD2 obtained at each instant. Here, PI = (S + SD2) / 2
Will be expressed as Note that the addition circuit 36B and the division circuit 38B provide the image to be inspected S and the two-cycle delayed image S
It functions as a synthesizing means for synthesizing D2. As a result, at least one reference image PI is obtained at each moment.
At least two of the two delayed images and the image to be inspected (in this case, the image to be inspected S, the two-period delayed image SD2
Are synthesized in real time.

The comparison / determination section 50B of the pattern inspection apparatus 1B has a comparison circuit 52B. The comparison circuit 52B performs a comparison operation between the reference image PI and the one-cycle delay image SD1 to obtain a target image. The defect inspection of the inspection image S is performed.

Here, since the ideal pattern does not include the image signal of the unit pattern to be inspected, the ideal pattern can be generated based on objective data excluding its own data. Since the defect inspection for each unit pattern is performed based on such an ideal pattern, the influence of noise on the detection result is reduced, and stable defect detection can be performed.

<Third Embodiment> In the third embodiment, a further modification of the first and second embodiments will be described. Here, a case will be described where a reference image PI as an ideal pattern is generated using two unit patterns having close values among three adjacent unit patterns including a unit pattern to be inspected.

The pattern inspection apparatus 1C according to the third embodiment comprises:
Except for the ideal pattern generation unit 30C, it has the same configuration as the pattern inspection apparatus 1A of the first embodiment,
Here, differences will be mainly described.

FIG. 7 is a functional block diagram showing a specific configuration of the ideal pattern generation section 30C and the comparison / determination section 50C. FIG. 8 is an explanatory diagram showing an outline of an image signal obtained in each specific pattern inspection operation. It is.

As shown in FIG. 7, the ideal pattern generator 30C includes one-cycle delay circuits 31C and 32C,
C, an adder circuit 36C, and a divider circuit 38C. The one-cycle delay circuit 31C generates a one-cycle delay image SD1, and the one-cycle delay circuit 32C generates a two-cycle delay image SD2. Then, the selection circuit 35C outputs the inspection image S,
From the three images of the one-cycle delayed image SD1 and the two-cycle delayed image SD2, two values having similar values are selected. The addition circuit 36C adds the two image signals selected by the selection circuit 35C, and the division circuit 38C divides (divides) the addition result of the addition circuit 36C by 2 to obtain a reference image PI. That is, the reference image PI includes the original image S, the one-cycle delayed image SD1, and the two-cycle delayed image S obtained at each moment.
It is obtained by calculating the average value of the gradation values of the corresponding pixels of each of the two images having similar values among the three images of D2. Note that the selection circuit 35C, the addition circuit 36C, and the division circuit 38C provide the inspection images S, 1
Periodic delay image SD1 and three of two-period delay image SD2
It functions as a synthesizing means for synthesizing two of the two images. Thereby, the reference image PI is obtained at least at least one of the at least one delayed image and the inspected image (in this case, the inspected images S, 1
Periodic delay image SD1 and three of two-period delay image SD2
(Two of the two images) are synthesized and generated in real time.

The comparison / determination section 50C of the pattern inspection apparatus 1C has a comparison circuit 52C. The comparison circuit 52C performs a comparison operation between the reference image PI and the one-period delay image SD1 to obtain an image to be processed. The defect inspection of the inspection image S is performed.

Here, the ideal pattern is obtained by averaging two unit patterns having close values, and does not include an image signal of another unit pattern having a distant value. In other words, an ideal pattern is generated based on two values excluding a portion that is considered to have the highest probability of being a noise or a defect. Therefore, the ideal pattern can be obtained as a pattern in which the influence of noise is reduced. Since the defect inspection for each unit pattern is performed based on such an ideal pattern, the influence of noise on the detection result is reduced, and stable defect detection can be performed.

<Fourth Embodiment> Next, a fourth embodiment will be described. This fourth embodiment is a modification of the first embodiment. In the first embodiment, as described later, since the value of the defect DT affects the generation of the reference image PI at a position separated from the defect position by a unit cycle, the value of the threshold value TH depends on the magnitude of the set value of the threshold value TH. An erroneous detection of detecting a defect other than a true defect as a defect may occur. According to the fourth embodiment, it is possible to suppress such erroneous detection.

The pattern inspection apparatus 1D according to the fourth embodiment comprises:
Except for the comparison / determination unit 50D, the configuration is the same as that of the pattern inspection apparatus 1A of the first embodiment, and the description here will focus on the differences.

FIG. 9 is a functional block diagram showing a specific configuration of the ideal pattern generation section 30D and the comparison / determination section 50D. FIG. 10 is an explanatory diagram showing an outline of an image signal obtained in each specific pattern inspection operation. It is.

As shown in FIG. 9, the comparison / determination unit 50D
It has comparison circuits 51D, 52D, 53D, and each of the comparison circuits 51D, 52D, 53D compares the inspection image S with the reference image PI, compares the one-cycle delayed image SD1 with the reference image PI, The two-cycle delayed image SD2 is compared with the reference image PI. Note that each of the comparison circuits 51D, 52
D and 53D have the same specific configuration as the comparison circuit 52A of the first embodiment, and perform comparison by binarizing the absolute value of the difference between the two image signals to be compared with a predetermined threshold value TH. The result can be obtained. In addition, the comparison determination unit 5
0D is a two-cycle delay circuit 71D, a one-cycle delay circuit 72
D and an AND circuit 76D. The two-cycle delay circuit 71D delays the comparison result COMP1 between the reference image PI and the inspection image S by two cycles and inputs the result to the AND circuit 76D. Similarly, the one-cycle delay circuit 72D outputs the reference image P
The comparison result COMP2 between I and the one-cycle delayed image SD1 is 1
The signal is input to the AND circuit 76D with a period delay. The comparison result COM between the reference image PI and the two-cycle delayed image SD2
P3 is the AND circuit 76D without delay
Is input to The AND circuit 76D calculates the AND of the comparison results COMP1, COMP2 and COMP3.
(Logical product) and outputs the result as an inspection result.

The operation of specifying the true defect position will be described with reference to FIG. Although the images of the unit patterns PA, PB, PC, etc. are not shown in FIG.
In the same manner as described above, the obtained inspection image S and the one-cycle delayed image SD
A one or two cycle delayed image SD2 and the like are shown. FIG.
Signal ABS (SD1-P
I) is the signal ABS shown in the second stage from the bottom in FIG.
The same signal as (SUB) is shown. The symbol ABS ()
Means the absolute value in parentheses.

Here, the defect D in the unit pattern PB
The value of T affects the generation of the reference image PI at a position separated by a unit period from the position of the defect DT. For example, in the case where the reference image PI is obtained by averaging the one-cycle delayed image SD1 and the inspected image S and the two-cycle delayed image SD2 which are shifted by one cycle before and after the one-cycle delayed image SD1, respectively. In the reference image PI, also at the periodic positions (the second and fourth positions from the left in the figure) before and after the periodic position (the third position from the left in the figure) corresponding to the unit pattern PB of the one-cycle delayed image SD1. , About の of the defect component (difference from the normal value) of the value of the defect DT is the reference image P
I, and the value of the defect DT is
Affects three unit patterns surrounded by a broken line A20 in I. As described above, the defect DT affects the generation of the reference image PI in the period before and after the defect position.

In the first embodiment, by comparing the one-cycle delayed image SD1 with the reference image PI,
A defect in the unit pattern PB was detected.
It is assumed that the threshold value TH is an appropriate value, for example, the threshold value TH is larger than a predetermined value TP (TH> TP). Here, the value TP indicates an appropriate lower limit value of the threshold value TH.
If the threshold value TH is not appropriate, for example, the threshold value TH =
If TH2 <TP, the unit patterns PA, P
It is determined that a defect exists in all of B and PC, and a defect other than the true defect is detected as a defect.

In the fourth embodiment, in order to prevent such erroneous detection, comparison circuits 51D and 53D are provided in addition to the comparison circuit 52D. In the following, an operation for specifying a true defect in the unit patterns PA, PB, and PC using these will be described.

The comparison circuit 51D compares the absolute value ABS (S-PI) of the difference between the image to be inspected S and the reference image PI by binarizing it with a predetermined threshold value. In this comparison, three ideal patterns surrounded by a broken line A10 in the reference image PI and each unit pattern P
A, PB, and PC are respectively compared. This image to be inspected S is an image one cycle before the one-cycle delayed image SD1, and is compared with three ideal patterns in the reference image PI to be compared with each unit pattern PA, PB, PC by a broken line A
Three ideal patterns in a broken line A10 one cycle before the three ideal patterns surrounded by 20 correspond. This broken line A
The ideal pattern at the left end of the three ideal patterns in 10 is not affected by the defect DT, and the unit pattern PA is accurately compared with the reference image PI not affected by the defect DT. Obtainable. Therefore, in the comparison result COMP1, PB and PC
The result of the determination that the defect exists only in is obtained.

Similarly, the comparison circuit 53D outputs the absolute value ABS (SD) of the difference between the two-cycle delayed image SD2 and the reference image PI.
2-PI) is binarized with a predetermined threshold to compare the two. In this comparison, three ideal patterns surrounded by a broken line A30 in the reference image PI are compared with each unit pattern PA, PB, PC in the two-period delay image SD2. The two-cycle delayed image SD2 is an image one cycle later (one cycle later) than the one-cycle delayed image SD1, and includes three ideal patterns in the reference image PI to be compared with each of the unit patterns PA, PB, and PC. Correspond to three ideal patterns in a broken line A30 which is one cycle later than the three ideal patterns surrounded by the broken line A20. Since the rightmost ideal pattern among the three ideal patterns in the broken line A30 is not affected by the defect DT, the unit pattern PC is accurately compared with the reference image PI not affected by the defect DT. The result can be obtained. Therefore, in the comparison result COMP3, a determination result that a defect exists only in the unit patterns PA and PB is obtained.

Then, the comparison result COMP1 by the comparison circuit 51D is delayed by two cycles, the comparison result COMP2 by the comparison circuit 52D is delayed by one cycle, and the comparison result COMP3 by the comparison circuit 53D is not delayed.
Each comparison result is synchronized and input to the AND circuit 76D, and the logical product of these comparison results is calculated.
To COMP3 are all "1" (defective)
In this case, it is detected as a true defect. The detection result of the defect is output at a timing delayed by two cycles with respect to the image S to be inspected. In this case, a detection result in which only the defect DT existing in the unit pattern PB is a true defect is obtained by being delayed by two cycles with respect to the image S to be inspected (in the third cycle). In the above description, the three unit patterns PA, PB, and PC have been described. Similarly, detection results for successive patterns in the inspection image S are sequentially output in real time.

Also in this embodiment, binarization is performed by comparing with an ideal pattern in which the influence of noise is reduced, so that the influence of noise on the detection result is reduced, and stable defect detection becomes possible. Further, the comparison determination unit 50D
Correspond to comparison circuits 51D, 52D, 53D, two-cycle delay circuit 71D, one-cycle delay circuit 72D, and AND circuit 76.
D, and these function as defect position specifying means for specifying a defect position. Therefore, the above-described effect, that is, the effect of the defect included in the image to be inspected on the generation of the ideal pattern is eliminated, and this effect is eliminated. Erroneous detection due to the above can be suppressed.

<Fifth Embodiment> This fifth embodiment is a modification of the first embodiment, similarly to the fourth embodiment, and can suppress the erroneous detection described above. The pattern inspection apparatus 1E according to the fifth embodiment has the same configuration as that of the pattern inspection apparatus 1A according to the first embodiment, except for the comparison / determination unit 50E. Here, differences will be mainly described.

FIG. 11 is a functional block diagram showing a specific configuration of the ideal pattern generation unit 30E and the comparison and determination unit 50E. FIG. 12 is an explanatory diagram showing an outline of an image signal obtained in each operation of a specific pattern inspection. It is. In FIG. 12, the image to be inspected S and the one-cycle delayed image SD
Although the one or two cycle delayed image SD2 and the reference image PI are not shown, each of the images S, SD1, SD2, and PI is shown in FIG.
It is the same as (FIG. 4).

As shown in FIG. 11, the comparison / determination unit 50E
Is a differential absolute value calculation circuit 80E, a one-cycle delay circuit 81
E, a two-cycle delay circuit 82E, a maximum value selector 83E, a comparator 84E, an AND circuit 85E, and a binarization circuit 86E.

The absolute difference calculating circuit 80E calculates the absolute value of the difference between the one-cycle delayed image SD1 and the reference image PI as a signal AS.
(The uppermost row in FIG. 12). The one-cycle delay circuit 81E is a signal ASD1 obtained by delaying the signal AS by one cycle.
And the two-cycle delay circuit 82E generates a signal ASD2 obtained by delaying the signal AS by two cycles. Then, the maximum value selection unit 83E outputs the signal AS, the signal ASD1, and the signal ASD2.
The signal MAX is generated by selecting the maximum value at each instant (each position) from the above three values. Further, the comparator 84E compares the signal MAX and the signal ASD1, and outputs a signal EQU that is “true” when both signals are equivalent (same value) and “false” when they are not equivalent.

By these processes, the reference signal AS
D1 and signals AS and ASD2 shifted one cycle before and after D1
Of the three signals described above, only when the signal value of the reference signal ASD1 is the largest (for example, in a region surrounded by a dashed line in FIG. 12), the value of the signal EQU becomes “true”.
Therefore, the unit pattern having the defect and the reference image P
Based on the property that the result of comparison with the ideal pattern of I has a larger value than the value appearing in the result of comparison between the unit pattern of the preceding and succeeding periods and the ideal pattern of the reference image PI, the possibility of a defect is high. A high position can be specified. Here, the signal AS used as a reference
D1 is a signal A delayed by one cycle with respect to the image S to be inspected.
S is a signal delayed by one cycle with respect to S, that is, a signal delayed by two cycles with respect to the image S to be inspected. Therefore, the detection result is output at a timing delayed by two cycles with respect to the image S to be inspected.

Finally, the AND circuit 85E outputs the signal ASD1 (instead of taking the logical product of the binary signals) to the signal EQ.
U is masked, and the signal ESD of the signal ASD1 is
The tone value is extracted only for the portion where the QU is “true”, that is, only for the portion that is likely to be defective. Then, the binarization circuit 86E performs binarization using the threshold value TH, and detects a portion having a value equal to or greater than the threshold value TH as a defect, thereby performing a comparison determination operation regarding the defect.

Also in this embodiment, since comparison with an ideal pattern in which the influence of noise is reduced is performed, the influence of noise on the detection result is reduced, and stable defect detection becomes possible. Further, the comparison determination unit 50E includes a difference absolute value calculation circuit 80E, a one-cycle delay circuit 81E, a two-cycle delay circuit 82E, a maximum value selection unit 83E, and a comparator 84.
E, an AND circuit 85E, and a binarization circuit 86E, which function as defect position specifying means for specifying a defect position. By eliminating the influence on the generation, it is possible to suppress erroneous detection caused by this influence.

<Sixth Embodiment> Next, a sixth embodiment will be described. The sixth embodiment is a modification of the second embodiment. Although the above-described erroneous detection may possibly occur in the second embodiment, the erroneous detection can be suppressed according to the pattern inspection apparatus 1F of the sixth embodiment. The pattern inspection apparatus 1F of the sixth embodiment has the same configuration as that of the pattern inspection apparatus 1B of the second embodiment, except for the comparison / determination unit 50F. Here, the differences will be mainly described.

FIG. 13 is a functional block diagram showing a specific configuration of the ideal pattern generation unit 30F and the comparison determination unit 50F. FIG. 14 is an explanatory diagram showing an outline of an image signal obtained in each operation of a specific pattern inspection. It is. In FIG. 14, the image to be inspected S, the one-cycle delayed image SD
Although the 1, 2 cycle delayed image SD2 and the reference image PI are not shown, the images S, SD1, SD2, PI are the same as those in FIG.

As shown in FIG. 13, the comparison / determination section 50F
Are the difference circuits 91F, 92F, 93F and the addition circuit 94
F, 95F, absolute value calculation circuits 96F, 97F, binarization circuits 98F, 99F, and an AND circuit 76F.

The difference circuit 93F calculates a difference between the image S to be inspected and the reference image PI, and outputs a signal SUB3 (= SP).
I) is output. Note that the symbol SUB () means a difference in parentheses. Similarly, the difference circuit 92F calculates the difference between the one-cycle delayed image SD1 and the reference image PI, and outputs the signal SUB
2 (= SD1-PI), and the difference circuit 91F calculates the difference between the two-cycle delayed image SD2 and the reference image PI, and outputs a signal SUB1 (= SD2-PI). The addition circuit 94F adds the signals SUB1 and SUB2 to generate a signal A.
DD1 is output, and the adder circuit 95F outputs signals SUB3 and SU
B2 is added to output a signal ADD2. The absolute value calculation circuits 96F and 97F respectively output the signal ADD1
And the absolute value of the signal ADD2, and the binarization circuits 98F and 99F binarize the output absolute value signals with a predetermined threshold to generate the signals THD1 and THD2. Further, the AND circuit 76F outputs an inspection result by taking an AND (logical product) of these two binarized signals THD1 and THD2. Then, in such processing, the signals THD1 and TH, which are two comparison results, are obtained.
Using D2, a part where both are "1" can be detected as a part which is a true defect.

Also in this embodiment, since the comparison with the ideal pattern in which the influence of noise is reduced is performed, the influence of noise on the detection result is reduced, and stable defect detection becomes possible. Further, the comparison / determination section 50F includes difference circuits 91F, 92F, 93F and addition circuits 94F, 95F.
Absolute value calculation circuits 96F, 97F and binarization circuits 98F, 9
9F and an AND circuit 76F, which function as defect position specifying means for specifying a defect position. Therefore, the above-described effect, that is, the effect of the defect included in the inspection image on the ideal pattern generation is eliminated. Thus, erroneous detection due to this effect can be suppressed.

<Seventh Embodiment> First to sixth embodiments
In the embodiment, the defect inspection of the inspection image S having the periodic repetition pattern has been described. Here, when the inspection image S is configured by repeating n unit patterns, the (n-
1) For the unit pattern up to the cycle, it is possible to perform a defect inspection in the unit pattern by the above-described technique. However, the unit pattern in the first cycle and the unit pattern in the n-th cycle (in other words, the inspection image S
(The end unit pattern), there is no unit pattern in a predetermined relative positional relationship for generating the ideal pattern. Therefore, the above technique cannot generate the ideal pattern, and the defect inspection is not performed. Can't do it.

In the seventh embodiment, in such a case,
In other words, even when there is no unit pattern having a predetermined relative positional relationship for generating an ideal pattern, generating an ideal pattern by using a different unit pattern and performing defect detection (specifically, The defect detection operation for all the unit patterns in the inspection image S is performed by performing the defect detection using an ideal pattern existing at a different periodic position in the reference image R).

The pattern inspection apparatus 1 G according to the seventh embodiment
Except for the comparison / determination unit 50G, it has the same configuration as the pattern inspection apparatus 1C (FIG. 7) of the third embodiment,
Here, differences will be mainly described.

FIG. 15 is a functional block diagram showing a specific configuration of the ideal pattern generation section 30G and the comparison / determination section 50G. FIGS. 16 and 17 show an outline of an image signal obtained in each specific pattern inspection operation. FIG.

As shown in FIG. 15, the ideal pattern generator 30G has the same configuration as the ideal pattern generator 30C (FIG. 7). However, in FIG. 15, for simplification, a plurality of circuits corresponding to the selection circuit 35C, the addition circuit 36C, and the division circuit 38C in FIG. 7 are collectively described as a reference image creation circuit 40G.

The comparing / determining section 50G includes a comparing circuit 52
G, comparison circuits 51G, 53G, two-cycle delay circuit 71G, one-cycle delay circuit 72G, and selector 77G
have.

The comparison circuit 51G outputs a signal C0 representing the result of comparison between the inspected image S and the reference image R (same as PI).
(= SR), and the two-cycle delay circuit 71G delays the signal C0 by two cycles, generates a signal C0D, and outputs the signal C0D to the selector 77G. Further, the comparison circuit 52G outputs a signal C1 (= O1-R) representing a comparison result between the one-cycle delayed image O1 (same as the above SD1) and the reference image R, and the one-cycle delay circuit 72G outputs the signal C1. Delay the signal C by one cycle
1D is generated and output to the selector 77G. further,
The comparison circuit 53G outputs a signal C2 (= O2) representing a comparison result between the two-cycle delayed image O2 (same as SD2) and the reference image R.
2-R) is output to the selector 77G as it is. Then, the selector 77G selects the signal C2 in a cycle delayed by two cycles (that is, a third cycle) with respect to the time of capturing the first unit pattern of the image S to be inspected, and a cycle delayed by three cycles (ie, a fourth cycle) The signal C1D is selected from the signal C1D to the cycle delayed by n cycles (ie, the (n + 1) th cycle) from the cycle delayed by (n + 1) cycles (ie, the (n +
2) In the cycle), the signal C0D is selected. This makes it possible to continuously obtain the defect detection result of the inspection image S in real time.

Here, the principle of operation will be described with reference to FIG. 16 and FIG. The numbers at the top of FIGS. 16 and 17 represent the cycle numbers (cycle numbers) of the respective signals having periodicity.

FIG. 16 shows an image S to be inspected, a one-cycle delayed image O1, a two-cycle delayed image O2, and a reference image R. This reference image R is created using three images, the image S to be inspected, the one-cycle delayed image O1 and the two-cycle delayed image O2, and in the third to n-th cycles of the reference image R, An effective reference image R has been created.

Next, the description will be continued with reference to FIG. First, from the second cycle of the inspection image S to the (n−
1) For each unit pattern up to the cycle, the inspection image S
In the one-cycle delayed image O1 delayed by the cycle, each unit pattern from the third cycle to the n-th cycle (broken line B10
, And also in the reference image R, an ideal pattern (broken line B1) effective at the corresponding periodic position.
1), the corresponding portion of the signal C1, which is the comparison result between the two (the portion surrounded by the dashed line B12), is a valid detection result. The selector 77G outputs a corresponding portion (a portion surrounded by a broken line B13) of the signal C1D obtained by further delaying an effective unit pattern (a portion surrounded by a broken line B12) in the signal C1, that is, a signal C1D. The detection results appearing from the fourth cycle to the (n + 1) th cycle are selected and output as the defect detection results.
In this manner, the (n-
1) The defect detection result for each unit pattern up to the cycle is delayed by two cycles with respect to the image S to be inspected, and the signal C
Appears from the 4th cycle to the (n + 1) th cycle of 1D,
This detection result is selectively output by the selector 77G.

On the other hand, the unit pattern in the first cycle (first cycle) of the image to be inspected S corresponds to the unit pattern in the second cycle in the one-cycle delayed image O1. There is no effective ideal pattern at the cycle position of the second cycle. In the second cycle of the reference image R, the two-cycle delayed image O2 is invalid data having an invalid value, so that the predetermined unit pattern does not exist in the second cycle of the two-cycle delayed image O2. That is, an effective ideal pattern cannot be generated in the second cycle of the reference image R. Therefore, defect detection cannot be performed by the same method as described above.

Therefore, in the defect inspection of the unit pattern in the first cycle (first cycle) of the image S to be inspected, the unit pattern originally used for the defect detection in the second cycle of the image S to be inspected (ie, the reference) The comparison detection operation is performed using the unit pattern in the third cycle of the image R). Therefore, a signal C2 representing the result of the comparison operation between the unit pattern in the third cycle of the two-cycle delayed image O2 and the unit pattern in the third cycle of the reference image R is obtained. Since the unit pattern in the third cycle of the two-cycle delayed image O2 corresponds to the unit pattern in the first cycle of the image to be inspected S, the signal C2 in this portion is converted to the first cycle of the image S to be inspected. It can be selected as an eye defect detection result. This selection is made by the selector 7
7G. Accordingly, even if a defect exists in the first cycle of the inspection target image S as illustrated,
The defect can be detected.

Similarly, the unit pattern of the n-th cycle (last cycle) of the inspection image S corresponds to the (n + 1) -th cycle of the unit pattern in the one-cycle delayed image O1. No effective ideal pattern exists at the (n + 1) -th cycle position. Therefore, the unit pattern originally used for the (n−1) th cycle defect detection of the inspection image S (that is, the unit pattern of the nth cycle of the reference image R) is used to detect the defect of the inspection image S. A comparison detection operation with the unit pattern in the n-th cycle is performed. for that reason,
The unit pattern of the n-th cycle of the inspection image S and the reference image R
A signal C0 representing the result of the comparison operation with the unit pattern of the n-th cycle is obtained. Then, the selector 77G selects and outputs the (n + 2) -th unit pattern of the signal C0D obtained by delaying the signal C0 by two cycles as a defect detection result for the n-th cycle of the inspection target image S. This allows
As shown, the n-th cycle (last cycle) of the inspection image S
Even if a defect exists in the device, the defect can be detected.

As described above, in the defect detection of the unit patterns in the first cycle (first cycle) and the n-th cycle (last cycle) of the inspection image S, the unit patterns having a predetermined relative positional relationship are not detected. Even if the ideal pattern required for the comparison detection operation cannot be generated because it does not exist,
Comparison detection operation based on an ideal pattern for detecting a defect related to a unit pattern at a different cycle position (that is, an ideal pattern for detecting a defect of a unit pattern in the second cycle and the (n-1) th cycle) Can be performed, so that the defect inspection can be performed on all the unit patterns in the inspection target image S. In this case, the comparison detection operation is performed using the ideal pattern for defect detection of the unit pattern existing at a different periodic position as it is, but a different ideal pattern is used by using a unit pattern different from the predetermined unit pattern. A pattern may be newly generated, and the comparison detection operation may be performed using the generated ideal pattern. This generally means that when there is no unit pattern having a predetermined relative positional relationship for generating an ideal pattern, a unit pattern different from the unit pattern having the predetermined relative positional relationship is generated. An ideal pattern is generated using the pattern, and a comparison operation is performed based on the ideal pattern. Also in the seventh embodiment, the ideal pattern used for defect detection of the unit pattern in the first cycle (first cycle) and the n-th cycle (last cycle) of the image S to be inspected is a predetermined relative pattern. It can also be understood that the unit pattern is an ideal pattern generated based on a unit pattern different from the unit pattern having a positional relationship (ie, the unit pattern to be inspected and a total of three unit patterns adjacent before and after the unit pattern).

<Eighth Embodiment> The eighth embodiment is a modification of the seventh embodiment. In the seventh embodiment, when comparing each pattern in the inspection image S with an ideal pattern in the reference image R, one predetermined ideal pattern of the reference image R and one ideal pattern in the inspection image S are compared. In the eighth embodiment, a case where two predetermined ideal patterns existing at different positions in the reference image R are compared with one pattern in the image to be inspected S will be described. . More specifically, in the eighth embodiment, the inspection image S having n repetition unit patterns
Generates a plurality of ((n-2)) ideal patterns based on a combination of a plurality of (3) unit patterns existing at different positions in the at least two (here, two)
The defect of each unit pattern is determined using a plurality of comparison results obtained by comparing each of the different ideal patterns with each unit pattern included in the inspection image. More specifically,
Defect detection is performed using the respective comparison results between two adjacent ideal patterns in the reference image and a predetermined pattern to be inspected in the image to be inspected S. According to this, the influence of noise included in the inspection image S can be further reduced.

In the eighth embodiment, as in the seventh embodiment, when there is no unit pattern having a predetermined relative positional relationship for generating an ideal pattern, the ideal pattern is formed using a different unit pattern. (Specifically, defect detection using ideal patterns existing at different periodic positions in the reference image R) will be described.

The pattern inspection apparatus 1H of the eighth embodiment is
Except for the ideal pattern generation unit 30H and the comparison determination unit 50H, the configuration is the same as that of the pattern inspection apparatus 1G of the seventh embodiment (FIG. 15), and the description here will focus on the differences.

FIG. 18 is a functional block diagram showing a specific configuration of the ideal pattern generation section 30G and the comparison / determination section 50G. FIGS. 19 and 20 show an outline of an image signal obtained in each operation of a specific pattern inspection. FIG.

As shown in FIG. 18, ideal pattern generator 30H includes one-cycle delay circuits 31H, 32H, 33H, 3H.
4H and a reference image creation circuit 40H.

The one-period delay circuit 31H generates a one-period delay image O1 obtained by delaying the image to be inspected S by one period, and the one-period delay circuit 32H further converts the one-period delay image O1 by one.
A two-cycle delayed image O2 delayed by a cycle is generated. Similarly, the one-period delay circuit 33H generates a three-period delay image O3 obtained by further delaying the two-period delay image O2 by one period.
The cycle delay circuit 34H generates a four-cycle delayed image O4 by further delaying the three-cycle delayed image O1 by one cycle. Then, the reference image creation circuit 40H outputs the one-cycle delayed image O1, the two-cycle delayed image O2, and the three-cycle delayed image O
3 to generate a reference image R (same as the above PI). Specifically, the reference image creation circuit 40H has a configuration similar to that of the third embodiment.

The comparison / determination section 50H includes a comparison circuit 51
H, 52H, 53H, 54H, 55H, one cycle delay circuits 56H, 57H, 58H, 59H, AND circuit 61H,
62H, 63H, 64H, a three-cycle delay circuit 66H, a two-cycle delay circuit 67H, a one-cycle delay circuit 68H, and a selector 69H.

The comparison circuit 51H calculates the comparison result between the image S to be inspected and the reference image R and outputs a signal C0 (= SR). The comparison circuit 52H outputs the one-cycle delay image O1 and the reference image R. And outputs a signal C1 (= O1-R) representing the result of the comparison. Similarly, the comparison circuit 53H outputs the two-cycle delayed image O2
And the comparison result between the reference image R and the signal C2 (= O2
-R), and the comparison circuit 54H outputs the three-cycle delayed image O
3 and the signal C3 (= O3-
R), and the comparison circuit 55H outputs the four-cycle delayed image O4
C4 (= O4-
R) is output.

The one-cycle delay circuit 56H outputs the signal C0
Is delayed by one cycle to generate a signal C0D, and an AND circuit 6
1H calculates AND (logical product) of the signal C0D and the signal C1 and outputs the result as a signal A0. The three-cycle delay circuit 66H delays the signal A0 by three cycles and outputs a signal A0D
Is generated and output to the selector 69H.

Similarly, one-cycle delay circuit 57H outputs signal C
1 is delayed by one cycle to generate a signal C1D, and the AND circuit 62H obtains an AND (logical product) of the signal C1D and the signal C2 and outputs the result as a signal A1. The two-cycle delay circuit 67H delays the signal A1 by two cycles to generate a signal A1D
Is generated and output to the selector 69H.

Further, one-cycle delay circuit 58H outputs signal C
The signal C2D is generated by delaying the signal C2 by one cycle, and the AND circuit 63H obtains AND (logical product) of the signal C2D and the signal C3 and outputs the result as a signal A2. One-cycle delay circuit 68H delays signal A2 by one cycle to generate signal A2D
Is generated and output to the selector 69H.

The one-cycle delay circuit 59H outputs the signal C3
Is delayed by one cycle to generate a signal C3D, and an AND circuit 6
4H obtains an AND (logical product) of the signal C3D and the signal C4 and outputs it as a signal A3 to the selector 69H as it is.

Then, the selector 69H outputs the image S to be inspected.
, The signal A3 is selected in a cycle delayed by four cycles from the imaging time of the first unit pattern, that is, in the fifth cycle, and the signal A2 is selected in the sixth to (n + 2) th cycles.
D is selected, and in the (n + 3) th cycle, the signal A1D
Is selected, and the signal A0D is selected in the (n + 4) th cycle. This makes it possible to continuously obtain the defect detection result of the inspection image S in real time.

Next, the principle of detection will be described with reference to FIGS. 19 and 20. FIG. 19 shows the image S to be inspected, the one-cycle delayed image O1, the two-cycle delayed image O2, the three-cycle delayed image O3, the four-cycle delayed image O4, and the reference image R. This reference image R is composed of a one-cycle delayed image O1, a two-cycle delayed image O2, and a three-cycle delayed image O3.
And an effective reference image R is created in the fourth to (n + 1) th cycles of the reference image R.

Here, for example, in detecting a defect in the pattern U (2) in the second cycle of the inspection image S, the ideal pattern R in the fifth cycle of the reference image R is used.
(5) and the pattern U in the fifth cycle of the three-cycle delayed image O3
(2) is compared with the ideal pattern R (4) in the fourth cycle of the reference image R and the fourth pattern of the two-cycle delayed image O2.
A signal C2, which is a result of comparison with the pattern U (2) in the cycle, is obtained, and a signal C2D obtained by delaying the signal C2 by one cycle and the result C3 are synchronized with each other to form an AND circuit 63H.
, And a signal A2 as a result of the comparison can be obtained as a result. However, here, in order to synchronize with another signal, the signal A2 is obtained by delaying the signal A2 by one cycle.
D is the detection result.

As described above, in the present embodiment, when detecting a defect of one unit pattern in the image S to be inspected, the comparison and determination operation is performed by using two or more different ideal patterns in the reference image R. , The effect of noise can be reduced. Hereinafter, the above operation and the like will be described in more detail with reference to FIG. The numbers at the top of FIG. 20 represent the cycle numbers (cycle numbers) of the respective signals having periodicity. FIG.
Here, the case where n = 6 is illustrated, and
Is present at the position shown in FIG.

First, the defect inspection for each unit pattern from the second cycle to the (n-2) th cycle of the inspection image S will be described. This is the signal C of the two comparison results.
2, C3, that is, the two-cycle delayed image O2 and the reference image R
And a signal C3 representing a result of comparison between the three-cycle delayed image O3 and the reference image R.

Here, the second to fourth (= n−2) cycles of the image S to be inspected correspond to the fifth to seventh cycles of the three-cycle delayed image O3. The fifth to seventh cycles of the reference image R are obtained as valid data, and the signal C3, which is the comparison result between the three-cycle delayed image O3 and the reference image R, is also obtained from the fifth cycle to the seventh cycle. It becomes a valid value in the seventh cycle. Similarly, the second to fourth cycles of the inspection image S correspond to the fourth to sixth cycles of the two-cycle delayed image O2. The fourth to sixth cycles of the reference image R are obtained as valid data, and the signal C2, which is a comparison result between the two-cycle delayed image O2 and the reference image R, is also obtained from the fourth cycle to the sixth cycle. It becomes a valid value in the sixth cycle.

Then, the signal C2 is delayed by one cycle to generate the signal C2D, thereby synchronizing with the signal C3,
An AND operation is performed by the AND circuit 63H to obtain a signal A2. Thus, the comparison operation is performed for each pattern in the second to fourth cycles of the inspection image S using two ideal patterns existing at different positions in the reference image R. Here, considering the pattern U (2) in the second cycle of the inspection image S, two ideal patterns (ideal patterns R (4) and R (4) in the fourth and fifth cycles) of the reference image R which are different from each other. The comparison operation is performed using (5)). Therefore, erroneous detection can be suppressed by using different ideal patterns, and the influence of noise can be reduced.

On the other hand, the unit pattern in the first cycle (initial cycle) of the image S to be inspected corresponds to the unit pattern in the third cycle in the second cycle delayed image O2, but the reference image R
, There is no effective ideal pattern at this third cycle position. This is because in the third cycle of the reference image R, the three-cycle delayed image O3 is invalid data having invalid values.

Therefore, two different ideal patterns in the reference image R originally used for the defect detection in the second cycle of the inspection image S (ie, the fourth and fifth ideal patterns in the reference image R).
Using the unit pattern U (4), U (5) of the cycle,
A comparison detection operation with the unit pattern in the first cycle of the inspection image S is performed. Here, the signals C3 and C of two comparison results
4, that is, the comparison operation is performed using the signal C3 indicating the comparison result between the three-cycle delayed image O3 and the reference image R and the signal C4 indicating the comparison result between the four-cycle delayed image O4 and the reference image R.

Here, the first cycle of the inspected image S corresponds to the fifth cycle of the four-cycle delayed image O4. The fifth cycle of the reference image R is obtained as valid data, and the signal C4, which is the comparison result between the four-cycle delayed image O4 and the reference image R, also has a valid value in the fifth cycle. Therefore, in the fifth cycle, the pattern of the first cycle of the image to be inspected S is compared with the ideal pattern by comparing the four-cycle delayed image O4 with the reference image R and obtaining the comparison result signal C4. Can be. Similarly, the first cycle of the inspected image S corresponds to the fourth cycle of the three-cycle delayed image O3. The fourth cycle of the reference image R is obtained as valid data, and the signal C3, which is the comparison result between the three-cycle delayed image O3 and the reference image R, also has a valid value in the fourth cycle. Therefore, in the fourth cycle, the three-cycle delayed image O3 is compared with the reference image R, and a signal C3 of the comparison result is obtained.
The pattern in the cycle can be compared with the ideal pattern. Then, the signal C3 is delayed by one cycle to produce a signal C3.
The signal A3 is obtained by generating D and performing an AND operation by the AND circuit 64H in synchronization with the signal C4. Thereby, the pattern U of the first cycle of the inspection image S
Regarding (1), 2 existing at different positions of the reference image R
The comparison operation can be performed using one ideal pattern (the ideal patterns R (4) and R (5) in the fourth and fifth cycles).

The unit pattern of the fifth (= n−1) -th cycle (the second cycle from the end) of the inspection image S is the third cycle.
Although this corresponds to the eighth (= n + 2) -th cycle unit pattern in the cycle delay image O3, there is no effective ideal pattern at the cycle position in the eighth cycle in the reference image R. This is because in the eighth cycle of the reference image R, the one-cycle delayed image O1 is invalid data having an invalid value.

Therefore, two different ideal patterns in the reference image R originally used for the defect detection in the fourth cycle of the inspection image S (ie, the sixth and seventh cycles of the reference image R).
Using the unit pattern U (6), U (7) of the cycle,
A comparison detection operation with the unit pattern in the fifth cycle of the inspection target image S is performed. Here, the two comparison result signals C1, C
2, that is, a comparison operation is performed using a signal C1 representing a comparison result between the one-cycle delayed image O1 and the reference image R and a signal C2 representing a comparison result between the two-cycle delayed image O2 and the reference image R.

Here, the fifth cycle of the inspected image S corresponds to the seventh cycle of the two-cycle delayed image O2. Further, the seventh cycle of the reference image R is obtained as valid data, and the signal C2 which is a comparison result between the two-cycle delayed image O2 and the reference image R also has a valid value in the seventh cycle. Therefore, in the seventh cycle, the two-cycle delayed image O2 and the reference image R are compared to obtain a comparison result signal C2, whereby the pattern of the fifth cycle of the image S to be inspected is compared with the ideal pattern. Can be. Similarly, the fifth cycle of the inspected image S corresponds to the sixth cycle of the one-cycle delayed image O1. Further, the sixth cycle of the reference image R is obtained as valid data, and the signal C1, which is a comparison result between the one-cycle delayed image O1 and the reference image R, also has a valid value in the sixth cycle. Therefore, in the sixth cycle, the one-cycle delayed image O1 and the reference image R are compared to obtain a comparison result signal C1, thereby obtaining the 5
The pattern in the cycle can be compared with the ideal pattern. Then, the signal C1 is delayed by one cycle to generate the signal C1D, and the AND operation is performed by the AND circuit 62H in synchronization with the signal C2 to obtain the signal A1. Thereby, the pattern U (5) in the fifth cycle of the image to be inspected S
, A comparison operation is performed using two ideal patterns (ideal patterns R (6) and R (7) in the sixth and seventh cycles) existing at different positions in the reference image R. In this case, in order to synchronize with other signals,
A signal A1D obtained by delaying the signal A1 by two periods is used as a detection result.

Further, the unit pattern of the sixth (= n) cycle (last cycle) of the image S to be inspected corresponds to the unit pattern of the ninth (= n + 3) cycle in the third cycle delayed image O3. In the reference image R, there is no effective ideal pattern at the ninth cycle position. In the ninth cycle of the reference image R, the one-cycle delayed image O1 is
This is because the invalid data has invalid values.

Therefore, two different ideal patterns in the reference image R originally used for the defect detection in the fourth cycle of the inspection image S (ie, the sixth and seventh cycles of the reference image R).
Using the unit pattern U (6), U (7) of the cycle,
A comparison detection operation with the unit pattern in the sixth cycle of the inspection target image S is performed. Here, the signal C, which is the result of the two comparisons,
The comparison operation is performed using 0, C1, that is, the signal C0 representing the comparison result between the image to be inspected S and the reference image R, and the signal C1 representing the comparison result between the one-cycle delayed image O1 and the reference image R.

Here, the sixth cycle of the inspected image S corresponds to the seventh cycle of the one-cycle delayed image O1. Further, the seventh cycle of the reference image R is obtained as valid data, and the signal C1, which is a comparison result between the one-cycle delayed image O1 and the reference image R, also has a valid value in the seventh cycle. Therefore, in the seventh cycle, the one-cycle delayed image O1 and the reference image R are compared to obtain a comparison result signal C1, whereby the pattern of the sixth cycle of the image S to be inspected is compared with the ideal pattern. Can be. Similarly, the sixth cycle of the reference image R is obtained as valid data, and the signal C0, which is the comparison result between the inspection image S and the reference image R, also has a valid value in the sixth cycle. Therefore, in the sixth cycle, the image S to be inspected is compared with the reference image R to obtain the comparison result signal C0, so that the pattern in the sixth cycle of the image S to be inspected can be compared with the ideal pattern. it can. Then, a signal C0D is generated by delaying the signal C0 by one cycle, synchronized with the signal C1, and AND
The signal C0D and the signal C1 are ANDed by the circuit 61H to obtain the signal A0. Thus, for the pattern U (6) in the sixth cycle of the inspection image S, two ideal patterns (ideal patterns R (6) in the sixth and seventh cycles) existing at different positions in the reference image R , R (7)). Here, in order to synchronize with other signals, a signal A0D obtained by delaying the signal A0 by three periods is used as a detection result.

Further, as described above, the selector 69H
The signals A0D, A1D,
One of the signals A2D and A3 is selected. That is, the selector 69H selects the signal A3 in a cycle delayed by four cycles from the time of capturing the first unit pattern of the image S to be inspected, that is, in the fifth cycle, and selects the signal A3 from the sixth cycle to the eighth (= n + 2). The signal A2D is selected up to the cycle, the signal A1D is selected in the ninth (= n + 3) cycle, and the signal A0D is selected in the tenth (= n + 4) cycle.
Select This makes it possible to sequentially and continuously obtain defect detection results for the n unit patterns included in the inspection image S in real time. In particular, the defect detection of the unit pattern of the first cycle (first cycle), the (n-1) th cycle (second last cycle), and the nth cycle (last cycle) of the inspection image S In the case where there is no unit pattern in a predetermined relative positional relationship for generating the ideal pattern, even if there is no unit pattern in the predetermined relative positional relationship, an ideal pattern Is generated, and the defect inspection is performed by performing the comparison operation based on the ideal pattern. Therefore, the defect inspection can be performed for all the unit patterns in the inspection target image S.

Here, in FIG. 20, the inspection image S
3 shows a case where noise is included in the first cycle and the fourth cycle. FIG. 21 is a diagram illustrating a processing result by the pattern inspection apparatus 1G according to the seventh embodiment, and illustrates a case where noise is included at the same position as in FIG. When noise is included, erroneous detection may be caused depending on the magnitude of the noise or the set value of the threshold in the comparison operation. In both FIGS. 20 and 21, erroneous detection due to noise is indicated by a black portion (portion painted black). In these figures, for the sake of convenience in description, it is assumed that erroneous detection due to noise frequently occurs.

As can be seen by comparing FIGS. 20 and 21, in the inspection result of FIG. 21, the third and third unit patterns corresponding to the detection results of the unit patterns in the first, second, fourth and sixth cycles of the image S to be inspected. In the fourth, sixth, and eighth periods, a total of four erroneous detections are involved. On the other hand, the inspection result shown in FIG. 20 involves a total of three erroneous detections in the fifth, eighth, and tenth cycles corresponding to the detection results of the unit patterns in the first, fourth, and sixth cycles of the image S to be inspected. . That is, in the case shown in FIG. 20, one erroneous detection is reduced as compared with the case shown in FIG.

As described above, according to the pattern inspection apparatus 1H of the eighth embodiment, a plurality of ideal patterns generated based on a combination of a plurality of (three) unit patterns included in the image S to be inspected are included. , At least two different ideal patterns included in the reference image R are selected, and a defect is determined using a plurality of comparison results obtained by comparing each of the selected at least ideal patterns with a unit pattern included in the inspection image. Therefore, even when the same noise is included in the image to be inspected S, the erroneous detection can be suppressed and the influence of the noise can be reduced as compared with the pattern inspection apparatus 1G of the seventh embodiment. I understand.

<Others> In the seventh and eighth embodiments, the reference image creation circuits 40G and 40H for generating the reference image R have the same configuration as in the third embodiment. The present invention is not limited to this, and may have the same configuration as the first embodiment or the second embodiment. Using the reference image R generated by these,
The same defect detection operation as described above can be performed.

In each of the above embodiments, the case where “dies” are repeatedly arranged as unit patterns on the semiconductor wafer has been described. However, the present invention is not limited to this. A "unit pattern" may be used.

Further, in each of the above embodiments, the semiconductor wafer is exemplified as the object to be inspected. However, the invention is not limited to this, and any object having a repetitive pattern may be used, for example, a color filter, a shadow mask, a printed wiring board. And so on.

[0115]

As described above, claims 1 to 1 are described.
According to the pattern inspection apparatus described in Item 0, the inspection image input means for inputting the inspection image, the ideal pattern generation means for generating an ideal pattern based on a plurality of unit patterns included in the inspection image, A comparison / determination unit that determines a defect of the unit pattern in the inspected image by using a comparison result of comparing the ideal pattern and the unit pattern included in the inspected image. By automatically generating a pattern and performing defect detection by comparing the generated ideal pattern with the generated ideal pattern, it is possible to reduce the influence of noise on the detection result and perform stable defect detection.

In particular, according to the pattern inspection apparatus of the present invention, since the ideal pattern is generated using the unit pattern adjacent to the unit pattern to be inspected, the unit pattern in the image to be inspected gradually becomes smaller. Even if it changes, a more ideal pattern can be generated.

Further, according to the pattern inspection apparatus of the sixth aspect, even if there is no unit pattern having a predetermined relative positional relationship for generating an ideal pattern, the actual pattern exists in the image to be inspected. Since the ideal pattern is generated by substituting the other unit patterns to be inspected, the defect inspection can be performed for all the unit patterns in the image to be inspected.

Further, according to the pattern inspection apparatus of the present invention, since the comparing and judging means has the defect position specifying means for specifying the position of the unit pattern having the defect, the defect contained in the image to be inspected is ideal. By eliminating the influence on the pattern generation, erroneous detection due to this influence can be suppressed.

According to the pattern inspection apparatus of the ninth aspect, the ideal pattern generating means includes means for sequentially inputting the image signal of the image to be inspected in unit patterns, and converting the image signal of the image to be inspected into the unit pattern. Means for obtaining a plurality of delayed inspected image signals having different delay times by delaying by an integral multiple of the repetition period, and an image signal of the inspected image and a plurality of delayed inspected image signals. Means for synthesizing two or more signals of the set to obtain a signal of an ideal pattern is provided, so that an ideal pattern can be generated in real time. Therefore, the pattern inspection can be performed in real time by using the ideal pattern obtained in real time.

Further, according to the pattern inspection apparatus of the tenth aspect, the ideal pattern generation means can generate a plurality of ideal patterns based on different combinations of the unit patterns included in the image to be inspected. Since the means determines at least two of the plurality of ideal patterns and the unit pattern to be inspected included in the image to be inspected to determine a defect in the unit pattern to be inspected, the influence of noise can be further reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a pattern inspection apparatus 1A according to a first embodiment of the present invention.

FIG. 2 is a plan view illustrating details of a semiconductor wafer W.

FIG. 3 shows an ideal pattern generation unit 30A and a comparison determination unit 5
It is a functional block diagram of 0A.

FIG. 4 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1A.

FIG. 5 shows an ideal pattern generation unit 30B and a comparison determination unit 5
It is a functional block diagram of 0B.

FIG. 6 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1B.

FIG. 7 shows an ideal pattern generation unit 30C and a comparison determination unit 5
It is a functional block diagram of 0C.

FIG. 8 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1C.

FIG. 9 shows an ideal pattern generation unit 30D and a comparison determination unit 5
It is a functional block diagram of 0D.

FIG. 10 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1D.

FIG. 11 is a functional block diagram of an ideal pattern generation unit 30E and a comparison determination unit 50E.

FIG. 12 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1E.

FIG. 13 is a functional block diagram of an ideal pattern generation unit 30F and a comparison determination unit 50F.

FIG. 14 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1F.

FIG. 15 is a functional block diagram of an ideal pattern generation unit 30G and a comparison determination unit 50G.

FIG. 16 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1G.

FIG. 17 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1G.

FIG. 18 is a functional block diagram of an ideal pattern generation unit 30H and a comparison determination unit 50H.

FIG. 19 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1H.

FIG. 20 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1H.

FIG. 21 is an explanatory diagram showing an outline of each image signal obtained in the pattern inspection apparatus 1G.

FIG. 22 is a diagram for explaining a conventional technique.

FIG. 23 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 1, 1A to 1H Pattern inspection apparatus 2 Object 3 XY table 10 Image input processing unit 30, 30A to 30H Ideal pattern generation unit 50, 50A to 50H Comparison judgment unit DT Defect PI, R Reference image R (i) Ideal pattern S Inspection image (original image) U Unit pattern W Semiconductor wafer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01N 21/956 H01L 21/66 J G06T 7/00 G01B 11/24 F H01L 21/66 K G06F 15/62 405A (72) Inventor Hiroyuki Onishi 4-chome Tenjin Kitamachi 1-chome, Horikawa-dori Teranouchi, Kamigyo-ku, Kyoto F-term (reference) 2F065 AA49 AA56 BB02 BB18 CC01 CC19 CC25 DD04 FF01 FF04 JJ02 JJ25 MM03 PP12 QQ04 QQ11 QQ25 QQ26 QQ31 QQ42 RR03 2G051 AA51 AA65 AA90 CA03 DA07 EA04 EA08 EA11 EA25 EB01 EB09 EC03 4M106 AA01 AA20 CA39 DB02 DJ04 DJ14 DJ18 5B007 AA03 DA03 DA03 DA03 DA03 DA03 DA03 DA03 DA03

Claims (10)

[Claims] 1. A pattern inspection apparatus for performing a defect inspection of a repetitive pattern, comprising: an inspection image input means for inputting an inspection image; and an ideal pattern generated based on a plurality of unit patterns included in the inspection image. An ideal pattern generation unit, a comparison determination unit that determines a defect of the unit pattern in the inspection image using a comparison result of comparing the generated ideal pattern and a unit pattern included in the inspection image, A pattern inspection apparatus comprising: 2. The pattern inspection apparatus according to claim 1, wherein unit patterns in the inspection image are sequentially selected as inspection unit patterns, and the ideal pattern is the inspection unit pattern and the inspection unit. A pattern inspection apparatus, which is generated based on a unit pattern other than a unit pattern. 3. The pattern inspection apparatus according to claim 1, wherein unit patterns in the inspection image are sequentially selected as inspection unit patterns, and the ideal pattern is a plurality of units other than the inspection unit pattern. A pattern inspection apparatus characterized by being generated based on a pattern. 4. The pattern inspection apparatus according to claim 1, wherein a unit pattern other than the unit pattern to be inspected used for generating the ideal pattern is a predetermined unit pattern with respect to the unit pattern to be inspected. A pattern inspection apparatus characterized by being unit patterns having a relative positional relationship. 5. The pattern inspection apparatus according to claim 4, wherein the unit pattern other than the unit pattern to be used for generating the ideal pattern is a unit pattern adjacent to the unit pattern to be inspected. A pattern inspection apparatus, characterized in that: 6. The pattern inspection apparatus according to claim 4, wherein, when a unit pattern does not exist at a position having the relative positional relationship with respect to the unit pattern to be inspected, the image to be inspected. A pattern inspection apparatus, wherein the ideal pattern is generated by substituting another unit pattern actually existing therein. 7. The pattern inspection apparatus according to claim 6, wherein the ideal pattern generating unit is configured to: when a unit pattern near one end of the inspection image becomes the inspection unit pattern, Means for generating the ideal pattern using a unit pattern adjacent to the other side of the image to be inspected with respect to the unit pattern to be inspected by changing a relative positional relationship. . 8. The pattern inspection apparatus according to claim 1, wherein the comparison and determination unit obtains a difference between the image to be inspected and the ideal pattern for each unit pattern, Means for obtaining a signal sequence; and a position specifying means for extracting a variable portion having an absolute value equal to or greater than a predetermined threshold value from among the variable portions appearing in the series of signal sequences, thereby specifying a position of a unit pattern having a defect. A pattern inspection apparatus comprising: 9. The pattern inspection apparatus according to claim 1, wherein the ideal pattern generating unit is configured to sequentially input an image signal of the image to be inspected in a unit pattern; Means for obtaining a plurality of delayed inspected image signals having different delay times by delaying the image signal of the image by an integral multiple of the repetition period of the unit pattern; and Means for synthesizing two or more signals of a set consisting of a plurality of delayed image signals to be inspected to obtain a signal of the ideal pattern. 10. The pattern inspection apparatus according to claim 1, wherein the ideal pattern generation unit can generate a plurality of ideal patterns based on different combinations of unit patterns included in the inspection image. A pattern inspection apparatus for comparing at least two of the plurality of ideal patterns with a unit pattern to be inspected included in the image to be inspected to determine a defect of the unit pattern to be inspected; .