JPH01173172A - Pattern defect inspecting method - Google Patents

Abstract

PURPOSE:To detect the defect of fine repetitive patterns with high sensitivity and high accuracy by delaying an image signal obtained by scanning optically an object to be inspected by an extent equal to the time needed for scanning a distance of an integer multiple as much as the repetitive pitch of the same pattern and comparing this delayed signal with a non-delayed signal. CONSTITUTION:Main scanning is carried out while an XY stage 5 is moved to the direction X against the optical axis of an objective lens 4. At the same time, the stage 5 is moved to the direction Y for secondary scanning. Image signals obtained from a photodetecting element 7 emerge repetitively in a cycle equal to a fixed time TP required for the main scanning carried out in the direction X by a distance equivalent to a cell pitch P. In case a certain cell has a defect D, a comparator 9 compares a delayed image signal with a non- delayed image signal. Thus no defect signal emerges at the part of the same pattern but the defect D is detected at the discordant part of the pattern. In such a way, a pattern defect can be detected with high sensitivity and high accuracy even in case fine patterns are contiguous to the defective pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pattern defect inspection method, and particularly to a pattern defect inspection method when the same pattern appears many times at a constant pitch.

(Prior Art) For example, the applicant has made various proposals regarding defect inspection techniques for patterns on photomasks used in the manufacture of semiconductor integrated circuits, but the basic technology is We focused on the fact that the same pattern appears repeatedly many times, and compared the image signals obtained by simultaneously optically scanning the same part of two patterns.
It is determined that there is a defect when the two do not match.

(Problems to be Solved by the Invention) In the conventional defect inspection method described above, a light beam emitted from a light source is split and projected as a spot onto an object to be inspected using two objective lenses. The reflected light from the object is guided to each light receiving element and image signals are output simultaneously.In this case, in order to improve inspection accuracy, it is desirable that the two patterns be as close as possible. Although the same pattern on two chips separated by chips is compared, it is impossible to bring them any closer together because the barrels of the objective lenses mechanically interfere with each other.

On the other hand, in semiconductor integrated circuits, in large-scale memory, 1
A large number of cells with the same pattern are arranged in a matrix within a single chip, and each cell has a fine structure, so compared to the cells of a chip that is made of several chips as in the past. If you try to do this, it will be very difficult to match the cell patterns, and if you increase the detection sensitivity and perform detection, parts that are not originally defects will be detected as defects.
The disadvantage is that accuracy is significantly reduced. In other words, it becomes extremely difficult to distinguish whether it is a pattern itself or a defect.

An object of the present invention is to eliminate such drawbacks and provide a method capable of detecting pattern defects with high sensitivity and accuracy even when fine patterns are adjacent to each other.

(Means and effects for solving the problems) The present invention has the following features:
When inspecting pattern defects on an object to be inspected that has a large number of identical patterns at a constant repeating pitch, an image signal obtained by optically scanning the object to be inspected and this image signal are separated at a distance equal to the pitch of the pattern. This is characterized by comparing the image signals delayed by the time required for scanning, and determining that there is a defect when there is a significant difference between these image signals.

According to the pattern defect inspection method of the present invention, 1
For example, the presence or absence of defects is detected by comparing the image signals detected by two optical systems with the image signals delayed by the time required to scan a distance equal to the cell array pitch with the image signals that are not delayed. can be performed with high sensitivity and precision.

(Example) FIG. 1 is a diagram showing the basic configuration of the defect inspection method of the present invention. The light emitted from the light source 1 is incident on the objective lens 4 through the half mirror 2 and the total reflection mirror 3, and
A beam spot is projected onto an object to be inspected 6 placed on a table 5. The light reflected by the object to be measured 6 is transmitted by the objective lens 4 to the light receiving element 7 via the mirrors 3 and 2.
is incident on the light receiving element, and an image signal is output from the light receiving element. This image signal is delayed through a delay circuit 8 and then supplied to one input terminal of a comparison circuit 9. An undelayed image signal is supplied to the other input terminal of this comparison circuit 9.

For example, in a semiconductor integrated circuit memory, a large number of cells 11 having the same pattern as shown in FIG. 2 are arranged in a matrix. Assuming that the stage 5 performs main scanning while moving in the X direction with respect to the optical axis of the objective lens 4, and performs sub-scanning by moving it in the Y direction, the image signal obtained from the light receiving element 7 is as shown in Fig. 3. As shown in A, it appears repeatedly at intervals of a constant time Tp required for main scanning in the X direction by a distance corresponding to the cell pitch P. Also, this image signal is converted to a time τ=T.

The signal delayed by this amount becomes as shown in FIG.

Assuming that there is a defect in the current cell, when the comparison circuit 9 compares the delayed image signal and the non-delayed image signal, no defect signal appears in the portions of the same pattern, but in the portions of the mismatched pattern. Then, defects are detected as shown in FIG. 2C. In this case, defect signals appear with opposite polarities when a defective cell is compared with its right neighbor cell and when it is compared with its left neighbor cell. Therefore, it is possible to determine in which cell a defect exists from these defect signals. In addition, cells located at the boundary between the cell area where the cell was formed and the circuit area around it are not compared twice as described above, but they are compared once, so they can be inspected for defects. Can be done.

FIG. 4 is a diagram showing the configuration of an embodiment of an apparatus for carrying out the defect inspection method according to the present invention. For example, when manufacturing large-scale memories made of semiconductor integrated circuits, a large number of chips are arranged in a matrix on one wafer, and each chip has a large number of cells having the same pattern as described above arranged in a matrix. However, inspection for defects in patterns in circuit parts other than cells cannot be performed using the above-mentioned delay means. Therefore, in this example, two objective lenses are placed apart in the X direction by an integral multiple of the chip arrangement pitch, and pattern defects in areas other than cells are detected by comparing the corresponding parts of the two chips. It is something to do. For this purpose, two objective lenses 21 and 22 are provided, and the light emitted from a light source 23 is made to enter the objective lens 21 via half mirrors 24 and 25, and to enter the objective lens via half mirrors 24, 26, and 27. The beam spot is made to enter the lens 22 and onto the wafer 29 placed on the xY child table 8. The reflected light from the wafer 29 is sent to the objective lens 2.
1 and 22, the light is incident on the light receiving elements 30 and 31 via the half mirrors 25 and 27. In this way, image signals from two points on the wafer can be obtained simultaneously.

The output signal of one light receiving element 30 and the output signal of the other light receiving element 31 are supplied to a differential amplifier 32 . As mentioned above, since the distance between the optical axes of the two objective lenses 21 and 22 is an integral multiple of the pitch interval of the semiconductor chips formed on the wafer 29, If the patterns match, there is no output from the differential amplifier, but if there is a defect in one of the patterns and they do not match, a signal corresponding to the difference is supplied to the determination circuit 33 as a defect detection signal. Ru. This makes it possible to detect pattern defects in circuit parts other than the cells of each chip.

The output image signal of one of the light receiving elements 30 is supplied to one input terminal of a differential amplifier 35 through a delay circuit 34 having a delay time τ required to scan the pitch distance between cells formed in the chip. . The other input terminal of the differential amplifier 35 is supplied with an undelayed image signal. In this way, the differential amplifier 35 supplies an error signal representing the difference between the patterns of two successive cells. This error signal is simultaneously supplied to first and second slice circuits 36 and 37.

The first slice circuit 36 passes an error signal that exceeds the slice level L (+) shown in FIG. 3C in a positive direction, and the second slice circuit 37 passes an error signal that exceeds a level L (-) in a negative direction. The output signals of these slice circuits are supplied to the determination circuit 33 via first and second gate circuits 38 and 39. A control signal is supplied from the determination circuit 33 to these gate circuits 38 and 39, and when the objective lens 21.22 is scanning the peripheral circuit portion surrounding the cell area and at a boundary position adjacent to the peripheral circuit area. When cells are being scanned, both gates 38 and 39 are closed, and defects in the peripheral circuit pattern are detected from the output signal of the differential amplifier 32. Objective lens 21.2
2 further enters the cell area and performs scanning, the gate circuits 38 and 39 are opened and an error signal as shown in FIG. 3C is supplied to the determination circuit 33. In this case, the determination In the circuit 33, patterns of cells adjacent to the peripheral circuit portion are compared with the adjacent cells only once, but other cells are compared twice with the adjacent cells on both sides.

FIG. 5 is a circuit diagram showing another example of an apparatus for carrying out the defect inspection method according to the present invention, and portions corresponding to those shown in FIG. 4 are designated with corresponding symbols. In this example, the output image signal of the second light-receiving element 31 is supplied to one input terminal of a differential amplifier 41 via a delay circuit 40 that delays it by the time τ required to scan the cell pitch, and the other input terminal of the differential amplifier 41. Supplied directly to the input terminal of In this way, the differential amplifier 41 supplies an error signal corresponding to the difference between the patterns of successive cells. Differential amplifier 35
The error signal output from the differential amplifier 41 is supplied to the first and second slice circuits 42 and 43, and the error signal output from the differential amplifier 41 is supplied to the third right and fourth slice circuits 44 and 45. First and third slice circuits 42
and 44 are supplied to gate circuits 46 and 47, respectively. As shown in FIG. 4, each of these slice circuits 42 to 45 and gate circuits 46 and 47 includes a slice circuit for detecting a positive direction error signal, a slice circuit for detecting a negative direction error signal, and a slice circuit for detecting a negative direction error signal, respectively. Although it has a gate circuit connected to the output side, FIG. 5 shows one slice circuit and one gate circuit, respectively, to simplify the drawing. The output signal of the second slice circuit 43 is supplied as a control signal to the second gate circuit 47, and the output signal of the fourth slice circuit 45 is supplied as a control signal to the first gate circuit 46. When output signals are supplied from circuits 43 and 45, gate circuits 46 and 47 are closed. Therefore, defect signals are supplied from the gate circuits 46 and 47 only when there is a pattern defect within the cell region. Judgment circuit 3 detects these defective signals.
Supply to 3.

The determination circuit 33 is basically a circuit that takes the logical sum of the output signal of the differential amplifier 32 and the output signals of the gate circuits 46 and 47, and detects defects from the output signal of the differential amplifier 32 in the peripheral circuit area. , defects are detected from the output signals of the gate circuits 46 and 47 in the cell region.

Note that the delay circuits 34 and 40 are variable delay circuits and are configured so that they can be adjusted according to the time required to scan the cell pitch of the chip to be tested, but they may be adjustable in conjunction with each other, or they may be adjusted separately. It may be possible to do so.

In the example shown in FIG. 5, the scanning position information on the chip is constantly supplied to the determination circuit 33, and the determination circuit changes the output signal of the differential amplifier 32 and the gate according to this position information. The output signals of circuits 46, 47 may be selectively processed to detect defects.

The present invention is not limited to the embodiments described above, and can be modified and modified in many ways. For example, in the embodiment described above, defects in the pattern of a large number of chips formed on a wafer are detected, but it is also possible to detect defects only in the pattern of cells within one chip.

Furthermore, in the above example, a defect in a chip pattern on a wafer is detected, but it is also possible to detect a defect in a pattern formed on a photomask. In this case, the light transmitted through the mask is made incident on the light receiving element. Just do it like this. Further, in the above example, the image signal is delayed by the time required to scan a distance equal to one pitch of the repeating pattern, but it may be delayed by an integral multiple of this time. Furthermore, in the above example, it was assumed that all the cells formed within the chip had the same arrangement pitch, but there are memories in which a large number of cells are formed in several regions with different arrangement pitches, but this is not the case. When testing a large chip, a plurality of processing circuits each including a delay circuit having a delay time corresponding to each pitch may be connected in parallel.

(Effects of the Invention) According to the defect inspection method of the present invention described above, the time required to scan an image signal obtained by optically scanning an object to be inspected over a distance that is an integral multiple of the repeating pitch of the same pattern. Since the signal is delayed and compared with a non-delayed signal, defects in fine repeating patterns can be detected with high sensitivity and accuracy.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the pattern defect inspection method according to the present invention, Fig. 2 is a plan view showing the pattern of a memory cell to be inspected, and Figs. 3 A to C are for explaining the operation thereof. FIG. 4 is a diagram showing the configuration of an example of an apparatus for carrying out the defect inspection method of the present invention, and FIG. 5 is a diagram showing the configuration of another example. 1... Light source 4... Objective lens 5...
・xY stage 6...Test object 7...Light-receiving element...Delay circuit 9...Comparison circuit

Claims (1)

[Claims] 1. When inspecting pattern defects on an object to be inspected that has a large number of identical patterns at a constant repeating pitch, an image signal obtained by optically scanning the object to be inspected and this image signal are applied to the pitch of the pattern. A pattern defect inspection method characterized by comparing an image signal with an image signal delayed by the time required to scan an equal distance, and determining that a defect exists when there is a significant difference between these image signals.