JP4564768B2 - Pattern inspection method and apparatus - Google Patents

Description

  The present invention relates to a substrate manufacturing apparatus having a circuit pattern such as a semiconductor device or a liquid crystal, and more particularly to a technique for inspecting a pattern of a substrate being manufactured.

A general appearance inspection apparatus acquires an image with respect to an object to be inspected, and performs defect inspection by an image processing apparatus. FIG. 17 shows a typical appearance inspection apparatus for defect inspection of a semiconductor wafer, which comprises a stage 1701, a sensor 1703, an AD circuit 1704, an image processing apparatus 1705, and an overall control computer 1706. A wafer 1702 as an object to be inspected is fixed on a stage 1701, and digital image data is acquired through a sensor and an AD circuit while moving the stage in the X direction and the Y direction. The digital image input data is subjected to defect detection in the image processing apparatus, and the detected defect information is stored in the overall control computer.

  FIG. 18 illustrates a typical die comparison method and cell comparison method processed by the image processing apparatus of the semiconductor wafer defect inspection apparatus. Note that a die and a chip are used in the same meaning, but in this specification, only a method is referred to as a die, and the rest are expressed as a chip. On the wafer to be inspected, a plurality of chips processed in the manufacturing process (separated into LSI in the future) are arranged in a lattice pattern. In FIG. 18, chips of n-1, n, n + 1, n + 2 are displayed for easy understanding. The apparatus acquires continuous image input data having a certain width in the scanning direction.

  In the die comparison inspection method, adjacent chips are compared using a lattice-like arrangement of chips on a wafer. For example, if n chips are to be inspected, n-1 is reference data to be compared. By repeating this as shown in the figure and scanning the entire surface, all defects on the wafer can be detected.

  On the other hand, the cell comparison inspection method compares repeated patterns called cells such as memory mat portions. For example, if a specific cell m in n chips is an inspection target, the previous (m−1) cell is reference data to be compared. By scanning the entire surface of the memory mat portion by stage control, a defect in the memory mat portion can be detected.

  The die comparison inspection method is effective for logic chips and the like, and the cell comparison inspection method is effective for memory chips, etc., but the memory mixed logic etc. has recently appeared, and the cell die mixed comparison inspection that can inspect cell comparison and die comparison simultaneously There is also.

  FIG. 19 is a diagram showing a configuration of an image processing apparatus that detects defects by a general cell die mixed comparison inspection. Data acquired through the sensor 1903 and the AD circuit 1904 are input to the die comparator 1901 and the cell comparator 1902, respectively.

  The die comparator 1901 prepares a reference image one chip earlier (an image delayed by one chip) from the image (inspection image) currently acquired by the chip delay 1905, and performs position correction and matching the positional relationship between the inspection image and the reference image. Brightness correction 1906 for correcting the difference in brightness between the two images is performed. Thereafter, a difference image calculation 1907 and a feature amount calculation 1908 of the two images are performed and stored in the overall control computer 1909 as defect information.

  The cell comparator 1902 has substantially the same configuration, but the difference is how to create a reference image. In other words, the cell comparison is to prepare a reference image one cell before (delayed image) by the cell delay 1910, and is otherwise the same. These configurations need to execute a large amount of processing at high speed, and are often pipelined by a hard wafer.

  Recently, a parallel data processing type image processing apparatus including a plurality of processor elements (PE) has been proposed due to improvement in processing performance of a processor. For example, it is disclosed in Patent Document 1. FIG. 20 is a block diagram showing a processor type image processing apparatus, in which 2001 is a data input unit, 2002 is a processing distribution unit, 2005 is a communication bus, and 2006 to 2009 are processor elements (PE (1) to (n)). ). For parallel processing of image data, a method is known in which the order in which input data is distributed to a plurality of processors is set.

  FIG. 21 shows operation timings assuming that four processors (1), (2), (3), and (4) are used. The image data operates so as to be distributed to each processor in order for each unit image data. Therefore, every third unit data D1, D5,... Is distributed to the processor PE (1) and processed (the oblique hatching portion in FIG. 21 represents the processing time of the unit image data), and the processor PE (2) Every third unit data D2, D6 ... is distributed and processed, and processor PE (3) is further distributed every other unit data D3, D7 ... and processor PE (4) is left Every three unit data D4, D8,... Are distributed and processed. In this case, how many times each processor processes the unit image data is determined by the processing time of the unit image data and the throughput of the input image. In general, the higher the input speed of image input, the shorter the unit data acquisition interval, and the more processors are used.

  When the image input data is divided into unit image data, the peripheral portion of the image is subjected to processing that shifts the input image by differentiation processing or position correction processing. There is a high possibility that a possible area will occur. Patent document 1 just describes this improvement. Specifically, it is said that the data is divided into a plurality of areas where the boundary portions overlap each other. The adjacent boundaries (for example, between D2 and D3) when divided are overlapped on the D2 side and the D3 side by the number of pixels in the non-computable area that can be predicted from the computation process. Can be prevented.

JP-A-11-259434 JP-A-6-325162

  As described above, it is possible to eliminate the area where calculation processing is not possible by providing an overlapping portion at the boundary position of image distribution and to perform effective calculation processing of all unit image data. However, this is only an effective area of image data. This is insufficient for cell inspection. As described in the cell comparison inspection method, when performing defect inspection by cell comparison, in addition to the inspection cell (inspection image) of the unit image data, the previous inspection cell (reference image) is required, especially unit image data. There is no reference image for the first inspection cell. Also in Patent Document 2, the relationship between the inspection cell and the previous cell (reference cell) is not described. For this reason, in the above-described cell comparison method, even if the improvement shown in the above-mentioned conventional example is viewed as an inspection called cell comparison, an uninspectable region occurs.

  An object of the present invention is to provide an image processing apparatus for appearance inspection capable of continuously inspecting cell comparison inspection, die comparison inspection, and cell die mixed comparison inspection using a plurality of processors.

  In order to achieve the above-described object, according to the present invention, a pattern inspection apparatus includes a stage unit on which a sample having a pattern formed on a surface is placed and can be moved continuously in at least one direction. An imaging unit that images the sample placed on the stage unit when continuously moving in a direction, and a plurality of consecutive images partially overlapping the image of the sample obtained by imaging by the imaging unit Image processing for detecting a defect in the pattern on the sample surface by including a plurality of division units for dividing the partial image into the divided partial images and a plurality of processing units for processing in parallel the continuous partial images divided by the division unit using a plurality of processor elements And a control means for controlling the stage means, the imaging means, and the image processing means.

  In order to achieve the above-described object, in the present invention, a stage unit on which a sample having a pattern formed on the surface is placed and can be moved continuously in at least one direction, and the stage unit is continuous in one direction. An imaging means for imaging the sample placed on the stage means while moving and outputting a digital image of the sample; and processing the digital image output from the imaging means to In a pattern inspection apparatus comprising an image processing means for detecting a defect in a pattern, and a control means for controlling the stage means, the imaging means, and the image processing means, the image processing means comprises a plurality of processing units, A distribution unit that distributes the digital image output from the imaging unit to the plurality of processing units, and the distribution unit includes a digital image output from the imaging unit. Was partitioned partially overlapping a plurality of the divided and the plurality of processing units in a state were together, the plurality of processing units, and so the digital image distributed respectively processed in parallel.

  Furthermore, in order to achieve the above object, according to the present invention, in a method for inspecting a defect of a pattern formed on the surface of a substrate, imaging is performed with the line sensor while moving the sample relative to the line sensor. To obtain a digital image of the sample surface, divide the digital image into a plurality of continuous image data such that the areas overlap each other in the longitudinal direction of the line sensor, and input to a plurality of image processing units, In each of a plurality of image processing units, the divided continuous image data is sequentially allocated to a plurality of processor elements, and the image data sequentially allocated by the plurality of processor elements is processed to be formed on the surface of the substrate. The defect of the pattern was detected.

  Furthermore, in order to achieve the above object, according to the present invention, in a method for inspecting a defect of a sample in which a plurality of chips each having a repeated pattern portion and a non-repeated pattern portion are formed on the surface, the sample is applied to a line sensor. The digital image of the sample surface is obtained by imaging with the line sensor while relatively moving the image, and the digital image is divided into a plurality of continuous images so that the areas overlap each other in the longitudinal direction of the line sensor. Each of the divided plurality of consecutive images is divided so as to overlap each other and sequentially allocated to a plurality of processor elements, and the images sequentially allocated by the plurality of processor elements are used as positional information on the sample of the images. In the repetitive pattern portion, a pattern defect is detected by cell comparison, and in the non-repetitive pattern portion, And to detect the defect pattern by die comparison.

  According to the present invention, real-time processing that requires high-speed and large-scale processing is performed in a system that performs parallel processing of image data that is continuously imaged using a plurality of processors in order to detect defects in an appearance inspection apparatus for an inspection object. It is possible to provide an image processing apparatus for appearance inspection capable of performing cell comparison inspection, die comparison inspection, and cell die mixed comparison inspection while being satisfied.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image processing apparatus for visual inspection according to the present invention, wherein 130 is a wafer as an object to be inspected, 120 is a stage, and the wafer 130 is placed and moved in a plane. It has a possible configuration. Reference numeral 101 denotes a sensor which is the same as the sensor 1703 in FIG. Reference numeral 102 denotes an AD circuit having the same function as the AD circuit 1704 in FIG. Reference numeral 100 denotes an image processing apparatus, and 103 denotes an overall control computer. In the figure, a sensor 101 is a detector that detects two-dimensional image data (a 640 pixel width line sensor or a TDI (Time Delay Integration) sensor), and is a continuous image data digitized through an AD circuit 102. Input to the image processing apparatus 100. In FIG. 1, the output from the sensor 101 to the AD circuit 102 and the output from the AD circuit 102 to the image processing apparatus 100 are each displayed by one line, but a plurality of signals are output in parallel. Including cases.

  The image processing apparatus 100 includes a plurality of processors, and performs a defect inspection by cutting out predetermined image data in units of basic images and assigning them to the plurality of processors. The overall control computer 103 stores detected defect information, sets pre-inspection recipe information in the image processing apparatus, and performs display, analysis, data exchange with other apparatuses, and the like.

  The internal configuration of the image processing apparatus 100, which is a feature of the present invention, includes a channel dividing unit 108 and a plurality of image processing units that process the images divided by the channel dividing unit 108. The image processing unit 104 of the channel 1 and the channel 2 The image processing unit 105 includes a channel 3 image processing unit 106 and a channel 4 image processing unit 107.

  As shown in FIG. 2, the channel dividing unit 108 has a function of dividing 640 pixels of the input width into 256 pixels (128 pixel overlap) 4ch. The input image data 640 pixel image data 201 is input to the channel 1 image processing 104 as 256-pixel continuous data of 1 to 256 images, and is input to the channel 2 image processing 105 as 256-pixel continuous data of 129 to 384 pixels. It is transferred to the image processing 106 of the channel 3 as 256-width continuous data of ˜512 pixels and to the image processing 107 of the channel 4 as 256-width continuous data of 385 to 640 pixels.

  Returning to FIG. 1, the image processing units 104 to 107 of each channel have the same function with continuous image data having a width of 256 pixels as an input. Each of the image processing units 104 to 107 has a function of distributing an image divided and cut out in units of basic image data by the dividing circuit 111 to the four processor elements (PE) PE0, PE1, PE2, and PE3. Each PE performs defect determination processing on an image cut out by dividing into basic image data units, and stores defect information detected therein through the bus 110 in the overall control computer. When defect information from all PEs processed in units of basic image data is collected, it becomes defect information of continuous image data having a width of 256 pixels.

  A detailed description of the dividing circuit 111 that cuts out an image in units of basic image data will be given with reference to FIGS. In FIG. 3, 301 is continuous image data having a width of 256 pixels, and is an enlarged view of the vicinity of image divisions Dn-1, Dn, Dn + 1 when the basic image data unit is 256 pixels wide × 1024 lines. It is. When the image segmentation Dn is cut out, an arithmetic processing overlap is necessary as already known. The overlap in the ch direction is omitted because it overlaps sufficiently as described in FIG. 2, and the division direction is considered. If the overlap between the image divisions Dn-1 and Dn is defined as OF and the overlap between the image divisions Dn and Dn + 1 is defined as OR, the cut-out image of the image division Dn is 256 pixels wide × (OF + image division Dn + OR). Become. OF is the calculation processing overlap + cell pitch size, and OR is the calculation overlap.

  As a specific numerical example, if the basic image size is 1024, the already known calculation processing overlap is 32 pixels, and the cell pitch size of the cell comparison is 256 pixels, OF is 32 + 256 and 288 pixels, OR is 32 Since it is a pixel, the cut-out image has a width of 256 pixels × (288 + 1024 + 32). As can be seen from the present embodiment, the front end overlap OF of the basic image size is characterized in that the cell pitch size is overlapped more than the overlap required for the operation processing overlap. Also, because the recipe that is the inspection condition differs for each inspection wafer, the OF value based on the cell pitch is recalculated for each inspection recipe, but the OF value is calculated based on the maximum cell pitch size determined by the equipment specifications. It is also possible.

  The continuous image (line direction) is coordinate-managed with the chip boundary as the origin by a line counter that detects the synchronization signal of the line sensor and obtains position information. This cut-out image is a cut-out line as shown in FIG. It can be expressed by the pointer LP and the cutout width W. In the cut image of the image division Dn, the value of the line pointer LP is Dn × 1024−OF, and the value of the cut width W is (OF + 1024 + OR). As a specific numerical example, for example, a clipped image when n = 3 has an LP of 3 × 1024-288 = 2784, W is 1344, and a clipped image when n = 4 has an LP of 4 × 1024 -288 = 3808, W becomes 1344.

  FIG. 4 is a time chart showing the relationship between continuous images, cut-out images in basic image data units, and distribution to processors. 301 is a continuous image having a width of 256 pixels, and basic image data units are indicated by D1, D2, D3. Reference numeral 302 denotes a cut-out image 302 divided for each PE, which is an image including OF and OR. The extracted image including D1 is PE0, the extracted image including D2 is PE1, the extracted image including D3 is PE2, the extracted image including D4 is PE3, the extracted image including D5 is PE0, The extracted image including D6 is in PE1, the extracted image including D7 is in PE2, the extracted image including D8 is in PE3, the extracted image including D9 is in PE0, the extracted image including D10 is in PE1 ... And operates so as to be distributed at the timing shown in FIG. Thus, in order to cut out the continuous image 301 into each cut-out image, it is possible to cut out from the first line LP1, LP2, LP3... And the cut-out width W of each cut-out image. The circuit configuration of the division 111 is shown below using FIG.

  The division 111 has a function of extracting continuous image data as a cut image and distributing it to a predetermined processor. Reference numeral 109 denotes a path through which continuous image data is input, which is input simultaneously to the cutting circuits 520, 521, 522, and 523 corresponding to the processor. Each cropping circuit has a function of receiving only the cropping activation signal (510 to 513) and the cropping width information 509, and outputting only the width W from the image in which the cropping activation signal is asserted.

  Prior to inspection, LP1, LP2, LP3,... Are calculated from the calculation processing overlap information, recipe information, and cell pitch information based on the concept described above. Next, it is determined to which processor the clipped image is assigned and stored in the determined memory. For example, LP1 is memory 501, LP2 is memory 502, LP3 is memory 503, LP4 is memory 504, LP5 is memory 501, LP6 is memory 502, LP7 is memory 503, LP8 is memory 504, ... To do. The line counter 530 is a counter that counts up from the top of the chip. When the inspection starts, the line counter 530 operates so that the activation signal is asserted whenever the value of the line counter matches the value of each memory.

  As another viewpoint, the operation focusing on the processor PE0 will be described. The memory 501 stores LP1, LP5... In advance, and the extraction width setting register 509 stores the extraction width W. When the inspection starts, the line counter counts up, and when the value of the counter coincides with LP1, the image extraction start signal 510 is asserted. The cut-out circuit 520 outputs, to the cut-out PE0, images corresponding to the cut-out width W stored in the cut-out width setting register 509 from the timing when the activation signal is asserted from the images 109 that are continuously input. Subsequently, when the value of the line counter coincides with LP5, the image cutout signal 510 is asserted again, and the image corresponding to the cutout width W stored in the cutout width setting register 509 is cut out from that timing and output to PE0. To do.

  This is exactly the movement corresponding to the cut-out images D1 and D5 to PE0 shown in FIG. When the next chip starts, the line counter is cleared and starts counting up, so that images at the same location can be transferred to the same processor.

  As described above, the image segmentation method that is a feature of the present invention has been described with reference to FIGS. 1 to 5, and subsequently, inspection of die comparison, cell comparison, and die cell mixed comparison for defect inspection that is a function of the present image processing. This will be explained separately. Prior to the inspection, the inspection condition, cell comparison, and area information for die comparison are transferred to the processor in response to a command from the overall control computer 103.

(1) Die Comparison Inspection Defect inspection by die comparison will be described with reference to FIGS. FIG. 6 shows a configuration of four processors PE0 to PE3 (621 to 624). Each processor has a CPU and memory. In particular, a part of the memory has an area for storing the extracted image data. The image memory configuration in this embodiment employs a 4-bank ring buffer system as shown in FIG. For example, when the processing of the nth chip is currently being executed, control is performed so that chip image data of n-1, n-2, and n-3 before that is stored. Returning to FIG. 6, the contents of the four banks in the memory store the cut image data assigned to each processor. For example, D1 is arranged in PE0, D2 in PE1, D3 in PE2, D4 in PE3, D5 in PE0, D6 in PE1, D7 in PE2, D8 in PE3, and so on.

  Next, the operation will be described using the time chart of FIG. Reference numeral 801 denotes continuous image data, which mainly describes n-1, n, and n + 1 chips. Further, 802 is an enlarged view of the n-th chip, and basic image data units D1, D2, D3,. When the cut-out image including D1 is transferred to PE0, the die comparison operation is started immediately. When the cut-out image including D2 is transferred to PE1, the die comparison operation is started immediately. Focusing on PE0, the die comparison inspection calculation process may be completed before the next cut-out image including D5 enters. There is a relationship between the number of PEs and the processing securing time. By increasing the number of PEs, the processing time for die comparison inspection can be secured.

  FIG. 9 shows a flowchart of the CPU program of each PE. A die comparison area is determined based on the area information transferred from the overall control computer 103 in 901 and the coordinate information managed by the line counter, and an inspection image is acquired in the die comparison area, and a reference image is acquired in 902. . Next, various corrections are performed on the inspection image and the reference image in 903, a defect is determined in 904, a feature amount is extracted in 905, and defect information is output in 906. The same program is stored in all PEs, and starts operating when image transfer is completed. The transfer timing is shifted in time as shown in FIG. 8, so that the program execution timing of each CPU is also shifted.

  As a specific example of the program, for example, the operation of the program with respect to the basic image data D5 of the nth chip will be explained. The image of D5 is arranged in the memory of PE0, and when the data of D5 is transferred, the data of PE0 The program on the CPU starts operating. First, in 901, as the inspection image acquisition, n-chip D5 data is copied to the work area WKF. Next, in 902, as reference image acquisition, the data of D5 in the bank in which the n-1 chip is stored is copied to the work area WKG. Next, in 903, processing such as position correction and brightness correction is performed using WKF containing n-chip D5 data and WFG containing n-1 chip D5 data. Next, the difference image calculation is performed only in the inspection area of the die comparison using the two corrected images in 904 to identify the defect. Next, at 905, feature amounts such as center coordinates and defect areas are calculated for each defect. Next, an operation is performed so that defect information including the feature amount obtained for each defect in 906 and an ID indicating the n-chip D5 are attached and output to the overall control computer 103. Thereafter, the program enters an idle state, and when the next data D9 is transferred, the program starts to operate again.

(2) Cell Comparison Inspection Defect inspection by cell comparison will be described with reference to FIGS. FIG. 10 shows a configuration of four processors PE0 to PE3 (621 to 624). Each processor has a CPU and memory. In particular, a part of the memory has an area for storing the extracted image data. In the image data area, cut image data assigned to each processor is stored. For example, D1 is stored in PE0, D2 is stored in PE1, D3 is stored in PE2, D4 is stored in PE3, D5 is stored in PE0, D6 is stored in PE1, D7 is stored in PE2, D8 is stored in PE3, and so on. As will be described later, since the cell comparison is performed based on information in units of basic image data, only the target image data need be stored at that time. For example, when the processing of the image data D1 of PE0 is completed and the image data of D5 to be subsequently processed is transferred, the D1 data may be overwritten.

  Next, the operation of the cell comparison inspection will be described using the time chart of FIG. Reference numeral 1101 denotes continuous image data, which mainly describes n-1, n, and n + 1 chips. Further, an enlargement of the n-th chip is 1102, and basic image data units D1, D2, D3,... Are shown. When the cutout image including D1 is transferred to PE0, the cell comparison operation is started immediately. When the cutout image including D2 is transferred to PE1, the cell comparison operation is started immediately.

  1103 is an enlarged image centered on the cut out images of D2 and D3. The cell is a name that calls a repetitive pattern like the memory cell of the memory mat portion. For the sake of explanation, the cell is represented by using a figure 1104 in FIG. Further, 1105 indicates a D2 cut image including OF and OR, and 1106 indicates a D3 cut image including OF and OR.

  Focusing on PE0, the calculation process of the cell comparison inspection is completed until the next cutout image including D5 is input. There is a relationship between the number of PEs and the computation processing securing time, and the computation processing time for cell comparison can be secured by increasing the number of PEs.

  FIG. 12 shows a flowchart of the CPU program of each PE. In 1201, a cell comparison area is determined based on the area information transferred from the overall control computer 103 and the coordinate information managed by the line counter, and an inspection image is acquired in this cell comparison area, and a cell reference image is acquired in 1202. To do. Next, various corrections are performed on the cell inspection image and the cell reference image in 1203, a defect is determined in 1204, whether a predetermined number of cells in the cell comparison area are inspected, and detected in 1206 The feature amount of the defect is extracted, and defect information is output in 1207. The same program is stored in all PEs, and starts operating when image transfer is completed. Since the transfer timing is shifted in time as shown in FIG. 11, the program execution timing of each CPU is also shifted.

  As a specific example of the program, for example, the movement of the program for the basic image data D2 of the nth chip will be described with reference to FIGS. 11 and 12. The image of D2 is arranged in the memory of PE1, and the data of D2 When the transfer ends, the program on the CPU of PE1 starts operating. First, in 1201, as an inspection image acquisition, in the case of the cell comparison inspection area, the data of the cell 4 of D2 is copied to the work area WKF. If it is not the cell comparison inspection area, the next area is input and the input operation of the cell 4 is repeated. Next, as reference image acquisition at 1202, the data of cell 3 of D2 is copied to the work area WKG. Next, in 1203, processing such as position correction and brightness correction is performed using WKF containing data of cell 4 of D2 and WFG containing data of cell 3 of D2. Next, a difference image calculation is performed using the two corrected images at 1204 to identify defects. Next, in 1205, the number of cells is determined.

  Since the test object includes four cells from cell 4 to cell 7 this time, the loop 1201 to 1204 is operated four times. Observing the loop focusing on WKF and WKG, the first time D2 cell 4 → WKF, D2 cell 3 → WKG, the second time D2 cell 5 → WKF, D2 cell 4 → WKG, the third time D2 Cell 6 → WKF, D2 cell 5 → WKG, and the fourth time is stored and executed in D2 cell 7 → WKF and D2 cell 6 → WKG. When the loop for the required number of cells is completed, feature amounts such as center coordinates and defect areas are calculated for each defect in 1205. Next, in 1206, the defect information including the feature amount obtained for each defect and the ID indicating the n-chip D2 are attached and output to the overall control computer 103. Thereafter, the program enters an idle state, and when the next data D6 has been transferred, the program starts the same operation again.

  In the present invention, since the cell pitch size is included in the OF, the processor PE1 can perform the cell comparison inspection from the clipped image to all the cells including the cell 4 (cells 4 to 7). Similarly, the processor 2 can inspect the cells 8 to 11. This means that continuous image data 1103 cannot be cut as a test by dividing it, and a continuous test can be performed without data exchange between processors.

(3) Cell Die Mixing Comparison Inspection Defect inspection by cell die mixing comparison will be described with reference to FIGS. When the cell die mixed comparison inspection is performed, the processing amount of each processor increases, so that an eight processor configuration from PE0 to PE7 is adopted. Since it is a configuration in which the number of PEs is increased by the 4-back method, which is the extended method of FIG. 6 already described, the drawing is omitted. The contents of four banks on the memory store cut-out image data assigned to each processor. For example, D1 is PE0, D2 is PE1, D3 is PE2, D4 is PE3, D5 is PE4, D6 is PE5, D7 is PE6, D8 is PE7, D9 is PE0, etc. Be placed.

  Next, the operation will be described using the time chart of FIG. Reference numeral 1301 denotes continuous image data, which mainly describes the (n-1, n, n + 1) th chips. Further, an enlargement of the n-th chip is 1302, and basic image data units D1, D2, D3,... Are shown. When the cut-out image including D1 is transferred to PE0, the Dicel mixture comparison operation starts immediately. When the cut-out image including D2 is transferred to PE1, the Dicell mixture comparison operation starts immediately. Paying attention to PE0, the calculation process of the Daicel mixed comparison inspection may be completed before the next cut-out image including D9 enters.

  There is a relationship between the number of PEs and the processing securing time, and by increasing the number of PEs, it is possible to secure the processing time for the Daicel mixed comparison. In the present embodiment, the number of processors is determined so as to secure the calculation processing time for the maximum time that the Daicel mixed comparison program calculates.

  FIG. 14 shows a flowchart of the CPU program of each PE. A die comparison area is determined based on the area information transferred from the overall control computer 103 in 1401 and the coordinate information managed by the line counter, and a die inspection image is acquired in the die comparison area. get. Next, various corrections are performed on the die inspection image and the die reference image in 1403, and a defect is determined in 1404. Subsequently, a cell comparison area is determined based on the area information transferred from the overall control computer 103 in 1405 and the coordinate information managed by the line counter, and an inspection image is acquired in this cell comparison area. Get an image. Next, in 1407, various corrections are made to the cell inspection image and the cell reference image, in 1408 a cell defect is determined, in 1409 it is determined whether a predetermined number of cells in the cell comparison area have been inspected, and in 1410 The feature amount of the detected defect is extracted, and defect information is output in 1411. The same program is stored in all PEs, and starts operating when image transfer is completed. The transfer timing is shifted in time as shown in FIG. 13, so that the program execution timing of each CPU is also shifted.

  As a specific example of the program, for example, with respect to the basic image data D2 of the nth chip, the movement of the program will be described with reference to FIGS. 13 and 14 and FIG. The program on the CPU of PE1 starts operating when the D2 data is transferred. First, in 1401, n2 D2 data is copied to the work area WKF as an inspection image acquisition. Next, at 1402, as reference image acquisition, the data of D2 in the bank in which the n-1 chip is stored is copied to the work area WKG. Next, in 1403, processing such as position correction and brightness correction is performed using WKF containing n chip D2 data and WFG containing n-1 chip D2 data. Next, a difference image calculation is performed using the two corrected images in 1404 to identify defects. Subsequently, in 1405, the data of the cell 4 of D2 is copied to the work area WKF as the cell inspection image acquisition. Next, in 1406, as the cell reference image acquisition, the data of the cell 3 of D2 is copied to the work area WKG. Next, in 1407, processing such as position correction and brightness correction is performed using WKF containing data of cell 4 of D2 and WFG containing data of cell 3 of D2. Next, using the two images corrected in 1408, if it is a die comparison inspection area, a difference image calculation is performed to identify a defect. Next, in 1409, the number of cells is determined. Since the test object includes four cells from cell 4 to cell 7 this time, the loop of 1405 to 1408 is operated four times.

  When the loop is observed focusing on WKF and WKG, the first time is D2 cell 4 → WKF, D2 cell 3 → WKG, the second is D2 cell 5 → WKF, D2 cell 4 → WKG, the third is D2 Cell 6 → WKF, D2 cell 5 → WKG, and the fourth time is stored and executed in D2 cell 7 → WKF and D2 cell 6 → WKG. When the loop for the required number of cells in the cell comparison inspection area is completed, in 1410, feature quantities such as center coordinates and defect areas are calculated for each defect. Next, in 1411, the defect information including the feature amount obtained for each defect and the ID indicating the n-chip D2 are attached and output to the overall control computer 103. Thereafter, the program enters an idle state, and when the next data D9 has been transferred, this program starts the same operation again.

  Since the defect information output to the overall control computer 103 is a comparative inspection, it cannot know which location is a true defect. Therefore, the true defect position is specified by the real control determination by the overall control computer 103. Real ghost is a logic that makes a true defect a true defect when the corresponding place is determined as a defect in both cases where the corresponding place is compared as a detected image and compared as a reference image.

  The real ghost determination in the case of cell comparison will be described in detail with reference to FIG. FIG. 22 shows an image distributed to the processor, and shows a state in which there is a defect 2201 in the repetitive pattern. In any case of the comparison A2202 and the comparison B2203, it is determined as a defect. That is, the comparison A is a comparison between 2201 parts having defects as detected images and 2204 parts as normal parts as reference images, and the difference is determined. The comparison B2203 is a comparison between the normal portion 2205 as a detected image and the defective portion 2201 as a reference image, and a difference is determined. From these, all the coordinates of these comparison places are once registered as defect candidates. That is, 2201 is registered twice and 2204 and 2205 are registered as defect candidates once. Of these candidates, if there are two or more defect candidates within a certain distance, it is determined that the defect is a true defect, and 2201 is determined to be a real defect (real), and 2205 is determined to be a defect because it is compared with a defect. It can be determined that it is a ghost defect.

  Real ghost determination in the case of die comparison will be described in detail with reference to FIG. FIG. 23 shows an image distributed to the processor and shows a defect 2301 in the dies to be compared. In any case of comparison A2302 and comparison B2303, it is determined as a defect. That is, the comparison A is a comparison between the defective 2301 parts as the detected image and the normal part 2304 as the reference image, and the difference is determined. The comparison B2303 is a comparison between a normal part 2305 as a detected image and a defective part 2301 as a reference image, and a difference is determined. All the coordinates of these comparison places are once registered as defect candidates. That is, 2301 is registered twice and 2304 and 2305 are registered as defect candidates once. Of these candidates, if there are two or more defect candidates within a certain distance, it is determined as a true defect, so 2301 is determined as a real defect (real) and 2305 is determined as a defect because it is compared with a defect. It can be determined that this is a ghost defect.

  In the case of cell / die mixed comparison, an inspection method tag is assigned to a defect, and a real ghost method is selected using the tag. True defects obtained by real ghost determination for each cell comparison and die comparison include defects detected by cell comparison and defects detected by die comparison in an area where cell comparison is possible. In the area where cell comparison is impossible, only defects detected by die comparison exist. These defects are merged into defect data by a program of the overall control computer 103, and merge processing is performed.

  The merge process will be described. Defects are defined as Dn (xn, yn, lxn, lyn, mn, sn), xn, yn are x and y coordinates, lxn, lyn are projection lengths, mn is an inspection method, sn is a defect area, and n is a defect serial number. . Two types of tolerance values are provided and are designated as A1 and A2. When | xi-xj | <(lxi + lxj) / 2 + A1, | yi-yj | <(lyi + lyj) / 2 + A1, mi == mj, the proximity region detected by the same method It can be considered that the defect is a separate defect or one defect detected in two. Therefore, if si> sj, the I-th defect Di is the representative defect, and if sj> si, Dj is the representative defect. The defect attributes are defects detected by two inspection methods, the area is si + sj, the projection length in the x direction is max (xi + lxi / 2, xj + lxj / 2) -min (xi-lxi / 2). , xj-lxj / 2), and the projection length in the y direction is max (yi + lyi / 2, yj + lyj / 2) -min (yi-lyi / 2, yj-lyj / 2).

  | xi-xj | <(lxi + lxj) / 2 + A1, | yi-yj | <(lyi + lyj) / 2 + A1, mi! = mj This is a case where a defect exists in an adjacent region, and there is a high possibility that it is the same defect. Therefore, if si> sj, the I-th defect Di is the representative defect, and if sj> si, Dj is the representative defect. The defect attributes are the same except for the inspection method, and the inspection method is determined to be a defect detected by two methods. In this merge determination, first, whether or not to merge is determined for all defects, and after completion of the determination, merge defect generation processing is performed.

  In this embodiment, the data is uniformly divided, and the die comparison processes the cut image entirely to find defects, so the data amount and the calculation processing amount are uniform, and the calculation processing time is almost uniform. There is a merit that From another viewpoint, in processing distribution to multiple processors, data can be uniformly divided and distributed to each PE in a sequential order without dynamically controlling the distribution by monitoring the processor status. There is a merit that real-time control is possible with less processor control overhead.

  1 shows a first variant of the invention. In the case of the die cell mixed comparison, there are a die effective inspection area and a cell effective inspection area, and it is only necessary to calculate or output defect information of each effective inspection area. Therefore, a basic image data unit of a processor unit or a processing region unit Then, only the cell comparison inspection or only the die comparison inspection is executed. According to this modification, since either the die comparison or the cell comparison has to be executed, the number of processors can be reduced.

  FIG. 15 shows a second modification of the present invention. This is a further improvement from FIG. 11 described above, and the difference lies in the extraction method when there are different cell pitch sizes. The cell pitch of the cell 1501 exists in the D2 image division region, and the cell pitch of the cell 1502 exists in the D10 image division region. The OF of the cut image in this case is to determine the value of OF from the maximum cell pitch among a plurality of cell pitches in the chip. Cutout images D2 and D10 in this case are as indicated by 1503 and 1504, and have the same OF and OR. Therefore, the two cells 2 and 3 are included in the OF of the cut image 1504 of D10. Originally, the cell 2 is unnecessary, but it is sufficient to compare the cells to be inspected 4 to 8.

  As in this embodiment, the maximum cell pitch of the entire chip is obtained before inspection, and during the inspection, all images are cut out with OF obtained from the maximum cell pitch, thereby enabling high-speed operation.

  FIG. 16 shows a third modification of the present invention. This is a further improvement from FIG. 3 described above, and the difference is that the inspection effective area is expanded beyond the image division area for inspection. In FIG. 16, 301 is continuous image data having a width of 256 pixels, and the vicinity of image divisions Dn-1, Dn, Dn + 1 when the basic image data unit is 256 pixels wide × 1024 lines is enlarged. FIG. When the image segmentation Dn is cut out, an arithmetic processing overlap is necessary as already known. The overlap in the ch direction is omitted because it overlaps sufficiently as described in FIG. 2, and the division direction is considered. If the overlap between the image divisions Dn-1 and Dn is defined as OF and the overlap between the image divisions Dn and Dn + 1 is defined as OR, the cut-out image of the image division Dn is 256 pixels wide × (OF + image division Dn + OR). Become. OF is arithmetic processing overlap + cell pitch size, and OR is arithmetic overlap + cell pitch size.

  As a specific numerical example, if the basic image size is 1024, the already known calculation processing overlap is 32 pixels, and the cell pitch size of the cell comparison is 256 pixels, OF is 32 + 288 and 288 pixels, OR is 32 Since +256 is 288 pixels, the cut-out image is 256 pixels wide × (288 + 1024 + 288). After detecting the defect, real ghost processing is performed in each processor. Since there is OR, it is possible to extract defects up to adjacent processor boundaries even if real ghost processing is performed in the processor. According to the present embodiment, since the real ghost processing can be performed by being distributed within each processor, there is a feature that high-speed processing can be performed. Further, in this modification, the difference image indicating the defect is further superimposed by shifting by the cell pitch, the small difference value is set as the true difference image of the pixel, and the true difference image is binarized. Take out. According to this modification, since real ghost processing can be performed at the image level, there is a feature that sufficient performance can be ensured even when a processor suitable for image processing that is not good at real number arithmetic is used.

  Next, the configuration of the second embodiment of the present invention is shown in FIG. An electron beam source 2401, a deflector 2403 that deflects the electron beam 2402 from the electron beam source 2401, an objective lens 2404 that converges the electron beam 2402 on the target substrate 2405 mounted on the stage 2406, and two generated by the target substrate 2405 Detector 101 for detecting secondary electrons, AD converter 102 for digitizing the signal detected by the detector, and processing the digital signal, the defect information of pattern defect 2411 is sent to overall control computer 103 via defect information path 110. The image processing circuit 100 is configured to transfer. As already shown in FIG. 16, the image processing circuit 100 has channel division 108, a division circuit for processing the channel-divided image, and a channel 1 image composed of a plurality of processors PE0, PE1, PE2, and PE3. The process 104 includes a channel 2 image process 105, a channel 3 image process 106, and a channel 4 image process 107 having the same configuration.

  The pattern defect 2411 is detected by the following operation. That is, the target substrate 2405 is irradiated with an electron beam 2402 from an electron beam source 2401, and the generated secondary electrons are detected by the detector 101 and digitized by the AD converter 102. A digital image is obtained by driving the stage 2406 in the Y-axis direction and deflecting the deflector 2403 in the X-axis direction in synchronization with the drive. From the obtained image, the image is supplied to the processor by the method already described in FIGS.

  In the image processing in the processor, die comparison is already performed by the method described in the first embodiment, and cell comparison is processed by the method shown in FIG. The image shown in the figure is an image transferred to one processor, and the detected image and the reference image are indicated by both ends A and B of the arrows, respectively. That is, the detected image and the reference image are compared at a constant interval L. When the distance is L from the lower end of the image, the detected image exceeds the range of the image as shown by the broken line, but the detected image is separated by 2L in the reverse direction. Compare the images of the positions of the solid line by setting the positions. Similarly, in the range where the distance from the upper end of the image is L, the reference image exceeds the range of the image as indicated by a broken line, but the position of the reference image is set 2L away in the reverse direction, and the positions of the solid lines Compare images.

  Locations where the difference is more than a certain level compared by cell comparison and die comparison are extracted by binarization and labeled, and the center position, projection length in X / Y direction, area, perimeter, circularity, and elongate for each label Calculate geometric features such as degrees. From the detected / reference image corresponding to the label portion, the grayscale feature amount such as each texture and signal amount is calculated. Difference image feature values such as average gray level difference and maximum gray level difference are calculated from the difference image before binarization. These geometric feature values, shading feature values, and difference image feature values are used as feature values of the defect. Based on the obtained feature value, real ghost determination is performed in the processor.

  That is, real ghost determination is performed for determining a true defect when R and D match within an allowable range separately for cell comparison and die comparison. Here, the positions of the detected image of the detected defect and the reference image are represented by D (dx, dy, px, py, lx, ly), R (dx, dy, px, py, lx, ly), (dx , dy) is the die number, (px, py) is the in-die coordinate, (lx, ly) is the projection length, and (dx, dy) is the same as the allowable range, and | px (D) -px (R) | <= (lx (D) + lx (R)) / 2 and | py (D) -py (R) | <= (ly (D) + ly (R)) / 2 It is established.

  For each comparison method, what is determined to be a true defect in the real ghost determination is automatically calculated based on the feature amount and defect classification information based on the feature amount, the detected comparison method, and detection and reference of the defect. The defect information having the difference image and the binarized difference image is transferred to the overall control computer 103 via the defect information path 110. The transferred defect information is displayed on the GUI 2600 shown in FIG. 26 during inspection. One of the defect classification or feature quantity is displayed on the object wafer map 2601 by symbol, chromaticity, and brightness. The display magnification can be changed as necessary. In addition, the display can be changed to a display format in which two feature values are taken on the X / Y axes as required. By specifying the designated defect 2602 being displayed, the feature amount in the defect information is displayed in the defect information display area 2603, and the image information is displayed in the image display area 2604. According to the present embodiment, it is not always necessary to set the overlap amount to be equal to or greater than the cell pitch, and the real ghost determination of the cell comparison and the die comparison can be closed in the processor.

  Next, a first modification of the present embodiment will be described with reference to FIG. In general, the pattern of the target substrate is a two-dimensional repetitive pattern in a staggered or grid pattern. Although the comparison place is made to coincide with the stage moving direction Y axis, as shown in FIG. 27, it is possible to compare with an arbitrary place such as the X direction and the oblique direction including the Y direction. The figure shows that there are four places that can be compared with the detection position 2701 as indicated by the tip of the arrow. Select any of these locations to compare. According to this modification, it is possible to compare with a position as close as possible and to improve detection performance.

  Next, a second modification of the present embodiment will be described with reference to FIG. Since the object has repeatability, this is a cell comparison method in which defects are detected by averaging all repetitions to create an ideal pattern 2801 of at least one repetition and comparing the detected image with the ideal pattern. Since the ideal pattern is created by averaging, it can be guaranteed that the defect is not substantially included. Therefore, real ghost processing for cell comparison is unnecessary, and the entire detected image can be image-processed.

  Next, a third modification of the present embodiment will be described with reference to FIG. The cell comparison is divided into an even number of image areas having a width equal to or greater than the repetition pitch L. An odd number (for example, A) and an even number (for example, B) are compared to extract a portion having a difference. If there is a difference, A and B are compared with C, respectively. When a defect is detected by comparing A and C, it can be determined that A is a true defect, and when a defect is detected by comparing B and C, it can be determined that B has a true defect. According to this modification, when there is no defect, the image processing area is ½, which is high speed.

1 is a diagram illustrating an image processing apparatus according to an embodiment of the present invention. It is a figure which shows the overlap between channels. It is a figure which shows detailed image division. FIG. 9 is a diagram showing image division into a plurality of processors. It is a figure which shows the circuit structure of image distribution. It is a figure which shows the structure of each PE in die | dye comparison inspection. It is a figure which shows 4 bank buffer image memory in die | dye comparison test | inspection. It is a figure which shows the operation | movement timing in die | dye comparison inspection. It is a figure which shows the flowchart in die | dye comparison inspection. It is a figure which shows the structure of each PE in a cell comparison test | inspection. It is a figure which shows the operation timing in a cell comparison test | inspection. The figure which shows the flowchart in the cell comparison inspection It is a figure which shows the operation timing in a cell die mixed comparison test. It is a figure which shows the flowchart in a cell die mixing comparison inspection. It is a figure explaining another improvement 1 of a cell comparison inspection. It is a figure explaining another improvement 2 of a cell comparison inspection. It is a figure which shows a known test | inspection apparatus. It is a figure explaining a known die and cell comparison inspection method. It is a figure which shows the structure of a known image processing apparatus. It is a figure which shows the test | inspection apparatus structure in a known multiple processor. It is a figure which shows the operation timing in a known multiple processor. It is a figure explaining the real ghost determination of a cell comparison. It is a figure explaining the real ghost determination of die comparison. It is a figure which shows the structure of a 2nd Example. It is a figure which shows the cell comparison defect determination method of a 2nd Example. It is a figure explaining the GUI screen in 2nd test | inspection. It is a figure explaining the reference position of a several cell comparison. It is a figure explaining the cell comparison system by comparison with an ideal pattern. It is a figure which shows the cell comparison system of 2nd Example 3rd modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus 101 ... Sensor 102 ... AD circuit
103 ... Overall control computer 104 to 107 ... Image processing for each channel
108 ... Channel division 301 ... Continuous image data 302 ... Cut-out image data
501 to 504... Line pointer storage memory 505 to 508... Comparison circuit
509 ... Cutout width setting memory 520 to 523 ... Cutout circuit
530 ... Line counter 601-604 ... CPU for each PE
611 to 614 ... memory for each PE 621 to 624 ... each PE (0) to (3)
801, 802 ... Continuous image data 1101, 1102, 1103 ... Continuous image data 1105, 1106 ... Cut-out image data 1301-1302 ... Continuous image data
Reference numerals 1503 to 1504, cut-out image data 1701, stage 1702, wafer 1703, sensor 1704, AD circuit 1705, image processing apparatus
1706: Overall control computer 1901 ... Die comparator 1902 ... Cell comparator 1903 ... Sensor 1904 ... AD circuit 1905 ... Chip delay circuit
1906: Position correction and brightness correction circuit 1907: Difference image calculator
1908: Feature value calculator 1909 ... Overall control computer
1910: Cell delay circuit 1911: Position correction, brightness correction circuit
1912 ... Difference image calculator 1913 ... Feature quantity calculator 2001 ... Input
2002 ... Distributing 2004 ... Output 2101 ... Continuous image data 2201 ... Defect 2401 ... Electron beam source 2402 ... Electron beam 2403 ... Deflector
2404 ... Objective lens 2405 ... Object substrate 2406 ... Stage
2411 ... Pattern defect 2601 ... Map 2602 ... Designated defect
2603 ... Defect information display area 2604 ... Image display area 2801 ... Ideal pattern

Claims (1)

Stage means capable of continuously moving in at least one direction by placing a sample in which a plurality of chips each having a repeated pattern portion and a non-repeated pattern portion are formed on the surface;
An imaging means for imaging the sample placed on the stage means and outputting a digital image of the sample when the stage means is continuously moving in one direction;
Image processing means for processing the digital image output from the imaging means to detect a pattern defect on the sample surface;
A pattern inspection apparatus comprising a control means for controlling the stage means, the imaging means, and the image processing means,
The image processing unit includes a plurality of processing units including a dividing circuit unit and a plurality of processor elements, and a dividing unit that distributes the digital image output from the imaging unit to the plurality of processes.
The dividing unit divides a digital image output from the imaging unit into a plurality of continuous digital images in a partially overlapping state, and distributes the divided digital images to the plurality of processing units.
Wherein the plurality In the processing unit, by dividing the digital image successive that is the distribution to a plurality uniformly to each other in a state in which the dividing circuit unit was duplicated processing overlap fraction and the cell pitch size of each other, wherein Each of the plurality of processor elements performs cell comparison for the repetitive pattern portion and die comparison for the non-repetitive pattern portion based on position information on the sample of the digital image uniformly divided by the division circuit portion. while the cell die mixed comparison with the pattern inspection apparatus and detects more defects to processing in parallel to each other.

Images