JP5178658B2 - Appearance inspection device - Google Patents

Description

  The present invention relates to an appearance inspection apparatus for inspecting defects such as circuit patterns and foreign matters formed on a semiconductor wafer.

  As an appearance inspection device that detects defects in circuit patterns formed on semiconductor wafers, it acquires a circuit pattern image, compares the reference image that is the inspection standard with the inspection image, and determines that there is a difference in the image as a defect. Conventionally, an appearance inspection apparatus for extraction is known. As the reference image, there are a method of using design data used at the time of designing a circuit pattern, a method of using an image immediately before the inspection image, and the like. When the detected image is used as a reference image, the circuit pattern to be inspected needs to be repeatable for each inspection image. A method of comparing and inspecting chips repeatedly formed on a wafer is called a die comparison inspection method, and a method of comparing and inspecting repeated patterns called cells such as a memory mat portion in one chip is a cell comparison inspection. This is called a method. The die comparison inspection method is applied to a logic chip or the like, and the cell comparison inspection method is applied to a memory chip or the like. In recent years, since the demand for memory mixed logic has increased, there has been an increasing demand for a cell die mixed comparison inspection in which a die comparison inspection and a cell comparison inspection are simultaneously performed in one inspection.

  As a representative example of the cell die mixed comparison inspection according to the prior art, there is known a method of inputting detected image data to each of the die comparison inspection unit and the cell comparison inspection unit and integrating the results of defect extraction in each unit. In the case of this method, it is necessary to prepare a dedicated unit for each of the die comparison and the cell comparison, and there is a problem that the scale of the system becomes large.

  Recently, an image processing apparatus of a parallel data processing type having a plurality of processor elements has been proposed due to an improvement in the processing performance of the processor (see, for example, Patent Document 1). There has also been proposed an image processing apparatus for continuously inspecting cell comparison inspection, die comparison inspection, and cell die mixed comparison inspection using a plurality of processors (see, for example, Patent Document 2). In these methods, when performing the cell die mixed comparison inspection, the image data is uniformly divided and distributed to the respective processor elements, and the die comparison inspection and the cell comparison inspection are respectively processed. Therefore, the calculation load of each processor element increases. There is a problem. In order to perform defect detection processing in real time, it is necessary to finish the processing until the next image data to be processed is input. To ensure real-time performance, each processor is increased by increasing the number of processor elements. It becomes necessary to reduce the calculation load around the element. On the other hand, in the cell die mixed comparison inspection, there is an area where the cell comparison inspection is not required, so the processor element that processes the image data not including the data in the cell comparison inspection area is compared with the processor element that performs the cell die mixed comparison inspection. Therefore, the calculation load is small and the waiting time is increased, and these methods cause a problem that the calculation processing capability of the entire system cannot be sufficiently extracted.

JP-A-11-259434 JP 2004-259228 A

  An object of the present invention is to provide an appearance inspection apparatus capable of performing die comparison inspection, cell comparison inspection, and cell die mixed comparison inspection by efficiently utilizing the processing capabilities of a plurality of processors.

  In order to solve the above problems, an embodiment of the present invention divides a plurality of image data of a circuit pattern in an appearance inspection apparatus that detects defects using image data of a substrate on which a circuit pattern of a semiconductor device is formed. An overall control computer that sets the conditions for cutting out and distributing in the image processing apparatus, and an image distribution processing unit that cuts out image data according to the conditions set in the image processing apparatus and distributes the image data to a plurality of processors. The defect detection process is performed on the image data distributed by the image distribution processing unit.

  According to the present invention, it is possible to provide an appearance inspection apparatus capable of performing die comparison inspection, cell comparison inspection, and cell die mixed comparison inspection using a plurality of processors by efficiently utilizing the processing capability of each processor.

It is a block diagram of an image processing apparatus. It is a block diagram of a processor element. It is a block diagram of transfer image data. It is a top view of a semiconductor wafer. It is a top view of a semiconductor wafer. FIG. 5 is an enlarged plan view of a part of a top view of the semiconductor wafer shown in FIG. 4. It is an operation | movement sequence diagram of the processor by a conventional method. It is an operation | movement sequence diagram which shows the example of a countermeasure by the conventional method. It is an operation | movement sequence diagram which shows the example of a countermeasure by the conventional method. It is an operation | movement sequence diagram of the processor by a conventional method. FIG. 6 is an enlarged plan view of a part of a top view of the semiconductor wafer shown in FIG. 5. It is an operation | movement sequence diagram of the processor by this invention. It is an operation | movement sequence diagram of the processor by this invention. It is an operation | movement sequence diagram of the processor by this invention. It is a top view which shows the area | region division example of the chip | tip by the conventional method. It is a top view which shows the area | region division example of the chip | tip by this invention. It is an operation | movement sequence diagram of the processor by a conventional method. It is an operation | movement sequence diagram of the processor by this invention. It is a top view of a chip. It is a top view of a chip. It is a screen figure which shows an example of an inspection area designation | designated screen. It is a screen figure which shows an example of the calculation load ratio designation screen in a chip | tip. It is a screen figure which shows an example of the calculation load ratio confirmation screen in a chip | tip. It is a screen figure which shows an example of the calculation load ratio confirmation screen in a test | inspection stripe.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to a following example, It can change timely within the range of the technical idea of this invention.

  First, the embodiments of the present invention are summarized as follows. According to the present invention, in an appearance inspection apparatus that detects defects using image data of a substrate on which a circuit pattern of a semiconductor device is formed, a condition for dividing, cutting out, and distributing a plurality of image data of a circuit pattern is set in the image processing apparatus. An overall control computer to be set; and an image distribution processing unit that cuts out image data in accordance with the conditions set in the image processing apparatus and distributes the image data to a plurality of processors, the processor distributing the image data distributed by the image distribution processing unit A configuration for performing defect detection processing is provided.

  More specifically, there is provided means for designating an inspection area according to the characteristics of the circuit pattern of the object to be inspected, such as a repetitive pattern or a non-repetitive pattern, and designating an inspection algorithm, an inspection condition, etc. A die comparison inspection area, a cell comparison inspection area, and a cell die mixed comparison area are calculated for each inspection stripe based on the set conditions. Furthermore, a means for giving calculation load information for each calculated area is provided, and a large number of processors are allocated to areas with a large calculation load based on the information, thereby reducing the amount of data to be processed by one processor and reducing the calculation load. A small number of processors are allocated to the area, and the number of processors allocated to each area and the image division width in each inspection stripe are calculated so that one processor processes a larger amount of data, and the image is distributed and defect detection is performed. With this configuration, it is possible to efficiently utilize the processing capability of the entire system in image processing by parallel processing using a plurality of processors.

  Further, the image distribution processing unit has a function of adding attribute data such as an inspection algorithm and inspection conditions designated for each inspection area and a block number of transmission data to the divided image data. If the processing is performed according to the information of the processor, even if the processing content is different for each processor or the processing content is changed for each inspection stripe, the processor may operate according to the received data information. Processes such as parameter resetting due to changes can be greatly reduced, and an optimal appearance inspection for performing inspections that include die comparison inspection, cell comparison inspection, and cell die mixed comparison inspection in one inspection. An image processing system can be provided.

  FIG. 1 shows an example of a configuration diagram of an image processing apparatus suitable for realizing the present invention. A wafer 102, which is an object to be inspected, is fixed on a stage 101 and irradiated with detection light such as an electron beam or a laser on the circuit pattern of the wafer 102 while moving the stage 101 in the X direction and the Y direction. The sensor 103 receives detection signals such as secondary electrons, reflected light, and transmitted light. The sensor 103 is a detector (for example, a line sensor or a CCD camera) that detects two-dimensional image data. The sensor 103 acquires continuous image data digitized through the AD circuit 104 and inputs it to the image processing apparatus 105. Is done. The input image data is subjected to defect detection processing by a plurality of processor elements 111, 112, and 113 in the image processing apparatus 105, the detected defect information is stored in the overall control computer 106, and the defect detection result is displayed on an interface such as a display. Displayed at 107, the inspection is completed.

  Here, the overall control computer 106 displays and analyzes the data of the defect detection result, and also the image data to be processed by each processor element 111, 112, 113 from the inspection condition (recipe information) given by the operator before the inspection. It plays a role of calculating conditions such as the location, size, processing method, and the like, and setting each parameter of the image processing apparatus 105 via the communication bus 114 as various parameter information for processing the image. The image processing apparatus 105 inputs the input image data from the AD circuit 104 to the image distribution processing unit 109 via the buffer memory 108. The image distribution processing unit 109 divides continuously input image data into a predetermined image size according to the data of the image distribution table 115 in the image distribution processing unit 109 set by the overall control computer 106 before inspection. Then, the image data is distributed to the processor elements 111, 112, 113 via the path switch 110.

  FIG. 2 is a configuration diagram illustrating a typical configuration example of the processor element 111. FIG. 3 is a configuration diagram showing a configuration example of transfer image data divided and distributed by the image distribution processing unit 109. In FIG. 2, an input / output controller 201 for controlling input / output of image data, an image memory 203 for storing transfer image data 301 input from the path switch 110 via the input / output controller 201, and defect detection for the image data. At least one or more processors 204 performing processing are provided, and data access therebetween is arbitrated by the bus arbiter 202.

  In FIG. 3, header information 302 and footer information 304 are added to the transfer image data 301 by the image distribution processing unit 109 before and after the divided image data 303. In the header and footer information 302 and 304, information such as a block number, a detection method, and a recipe number set for each divided data is set in the image distribution table in the image distribution processing unit 109 shown in FIG. It is added as attribute data of the image data 303.

  In FIG. 2, the processor 204 includes a coordinate table 205 indicating coordinate information of the transfer image data 301 and an inspection condition table 206 indicating inspection conditions corresponding to recipe information indicating inspection conditions. Inspection conditions are set in advance. Each processor 204 interprets the attribute data added to the header information 302 and footer information 304 of the transfer image data 301 and executes defect detection processing according to the data in the coordinate table 205 and the inspection condition table 206 corresponding to the attribute data. . Accordingly, the processing content can be changed for each divided image data, and an image processing apparatus that realizes flexible image processing that matches the characteristics of each transfer image data 301 can be provided.

  Next, a specific example of an inspection method using the image processing apparatus shown in FIG. 2 will be described. 4 and 5 are top views of the semiconductor wafer. FIG. 4 shows a die comparison inspection method processed by the image processing apparatus 105 of the appearance inspection device, and FIG. 5 shows a cell comparison inspection method. A plurality of chips 401, which are semiconductor circuit patterns processed in the manufacturing process, are arranged in a lattice pattern on a wafer 102, which is an object to be inspected. In the drawing, for simplification, n−1, n , N + 1, n + 2 only chips are displayed. The appearance inspection apparatus acquires continuous image data having a certain width in a scanning direction called an inspection stripe 402. Usually, defects are detected for each inspection stripe 402, the entire surface is scanned while shifting the scanning position, and the process is repeated to detect defects on the entire surface of the wafer 102.

  FIG. 4 shows a die comparison inspection method. In the die comparison inspection method, adjacent chips are compared using a lattice-like arrangement of chips on the wafer 102, and a non-matching portion between both images is extracted as a defect. For example, the nth chip Is an inspection image to be inspected, the (n-1) th chip is a reference image to be compared. Basically, the entire chip can be inspected, and it is possible to inspect regardless of whether the pattern is repeated or non-repeated. There is a feature that alignment correction processing in a range is necessary. Note that a chip and a die are usually used in the same meaning, but in the present specification, only a method is expressed as a die.

  FIG. 5 shows a cell comparison inspection method. In the cell comparison inspection method, with respect to a repetitive pattern portion called a cell such as a memory mat portion in one chip, the cell pitches are separated from each other by using the repetitive pitch as a cell pitch, and the mismatched portion is compared. It is extracted as a defect. For example, when a specific cell in the nth chip is an inspection image to be inspected, the previous cell is a reference image to be compared. Since the patterns having relatively narrow intervals are compared with each other, the influence of the positional deviation is not so great, but there is a feature that area management is required for a plurality of repeated pattern portions. In order to perform such highly reliable defect detection processing, it is necessary to select and inspect an inspection method according to the characteristics of a circuit pattern to be inspected. In recent years, there has been an increasing demand for cell die mixed comparison in which a die comparison inspection method and a cell comparison inspection method are simultaneously performed in a single inspection for memory embedded logic and the like.

  FIG. 6 is an enlarged view of a part of the top view of the semiconductor wafer shown in FIG. 4, and shows an example of an in-chip pattern arrangement of a memory-embedded logic chip and an example of in-chip image division in the conventional method. As shown in the figure, a chip 401 is provided with a memory mat portion 502 which is a repeated pattern area in a non-repeated pattern area 501. In the figure, only three inspection stripes 503, 504, and 505 suitable for explaining the effect of the present invention are shown. However, in the normal inspection, the inspection stripes are overlapped so that non-inspection areas are not generated. Scan the entire surface. In the following description, an embodiment will be described assuming that 16 processor elements 111 are mounted in the image processing apparatus 105. In the conventional image division method, the area of the chip 401 in each of the inspection stripes 503, 504, and 505 is equally divided by the number of processor elements 111, 112, and 113 (16 in this embodiment) in the image processing apparatus 105. Area division is performed using a as a basic division size, and data with overlap areas added before and after is transmitted to each processor element 111, 112, 113 so that a non-inspection area does not occur based on the division information. In the case of the conventional method, it is equally divided by the number of processor elements 111, 112, and 113 regardless of the circuit pattern to be inspected. If there is a region, and there is a region including both the non-repeated pattern portion and the repetitive pattern portion, as shown by the hatched region in the figure.

  FIG. 7 is an operation sequence diagram of a processor according to a conventional method, in which only a non-repeated pattern portion region is subjected to only die comparison inspection, a repeated pattern portion only region is associated with only cell comparison inspection, and a region including both is die comparison, An inspection sequence in the case where both cell comparison inspections are performed is shown. 7 corresponds to the region of the inspection stripe 503 shown in FIG. In FIG. 7, the divided area data D1, D2,..., D16 of the nth chip are transferred to the processor elements PE (0), PE (1),. As soon as image data is received, a defect detection process is executed. PE (0) to PE (5) and PE (13) to PE (15) perform only die comparison inspection, and PE (7) to PE (11) perform only cell comparison inspection. Since the data received by PE (6) and PE (12) includes a non-repeated pattern and a repeated pattern, both the die comparison inspection and the cell comparison inspection are executed. As can be seen from the figure, PE (6) and PE (12) perform both die comparison inspection and cell comparison inspection, so that the computation load is larger and the processing time is longer than other processor elements. End up. Each processor element needs to complete the processing of the nth data until it receives the data of the next n + 1th chip to be processed next. In the example of FIG. 7, PE (6) is n + 1th. The cell comparison inspection process is not completed at the timing 601 for receiving the data, and cannot be processed in real time. In this way, when the calculation processing of the processor element does not fit within the image distribution cycle of each chip, conventionally, it has been dealt with by (1) slowing down the detection speed of image data, (2) increasing the number of processor elements, etc. Was.

  FIG. 8 is an operation sequence diagram in a case where the above-described problem is taken by reducing the detection speed of image data. As can be seen from the figure, the image distribution cycle is extended by reducing the detection speed of the image data, and normal processing can be performed by increasing the time allowed for calculation processing for one image data. Yes. However, slowing down the detection speed of image data increases the inspection time, which causes a problem of causing a reduction in throughput.

  FIG. 9 is an operation sequence diagram in the case where the number of processor elements is increased by, for example, two to take measures against the above problem. By increasing the number of processor elements, the amount of image data distributed around one processor element is reduced and the processing time is reduced, so that normal processing can be performed without degrading throughput. It has become. However, this method also has problems such as an increase in apparatus size and cost. As described above, in order to perform defect detection processing in real time in accordance with the collection of image data, it is necessary to complete the defect detection processing until the next data is received. , It is necessary to adjust the detection speed of the image data in accordance with the processing time of the processor element that performs both of the cell comparison inspections. As described above, in the conventional method, the maximum detection speed of the image data is determined by the processing end timing 802 of the processor element having the heaviest calculation load, and the other processor elements are not in operation time waiting for data input such as the interval 801. As a result, the processing capability of the image processing apparatus cannot be fully utilized.

  FIG. 10 is an operation sequence diagram of the processor according to the conventional method in the inspection stripe 504 shown in FIG. The non-operation time 901 occurs for the same reason as in the case of the inspection stripe 503 shown in FIG. 6 described in FIG.

  FIG. 11 is an enlarged view of a part of the top view of the semiconductor wafer shown in FIG. 5, and an example of an in-chip pattern arrangement of a memory-embedded logic chip similar to FIG. 6 and in-chip image division based on the present invention. An example of image division when the above is performed is shown. The overall control computer 106 gives the area information of the non-repeated area 501 and the memory mat portion 502 in advance. Here, for the sake of explanation, the area 506 has a width of “4” and the area 507 It is assumed that the width is given as “3.8” and the width of the region 508 is given as “2.4”. The calculation load ratio when performing only the die comparison inspection is “1”, the calculation load ratio when performing only the cell comparison inspection is “0.5”, and the calculation load ratio when performing the cell die mixed comparison is “1.5”. ".

  First, an image dividing method in the inspection stripe 503 will be described. The inspection stripe 503 is divided into three regions, a region 509, a region 510, and a region 511, based on region information given in advance. A region 509 and a region 511 are die comparison inspection regions, and a region 510 is a cell comparison inspection region. Here, the ratio of the area widths of the areas 509, 510, and 511 is “4: 3.8: 2.4”, and the ratio of the calculation load is “1: 0.5: 1”. When the number of processor elements is 16, the number of processor elements allocated to each of the three areas can be calculated by the following procedure.

<Procedure 1> Calculate the load ratio in each area: area width ratio × computed load ratio area 509 load ratio: 4 × 1 = 4
Load ratio of area 510: 3.8 × 0.5 = 1.9
Load ratio of area 511: 2.4 × 1 = 2.4
<Procedure 2> Calculate the sum of the load ratio in Procedure 1. Sum of the load ratio = 4 + 1.9 + 2.4 = 8.3
<Procedure 3> Calculate the ideal number of processor allocations: Number of allocated processors = total number of processors × area load ratio / total load ratio Area 509 allocation number: 16 × 4 / 8.3 = 7.71
Number of allocations in the area 510: 16 × 1.9 / 8.3 = 3.67
Number of allocated areas 511: 16 × 2.4 / 8.3 = 4.62
<Procedure 4> The assigned number is converted to an integer by comparing the decimal part size. The total of the integer part in Procedure 3 is 7 + 3 + 4 = 14.
The assignment of the remaining two processor elements is determined from the comparison of the decimal part and converted to an integer. Number of assignments in the area 509: 7.71 → 8
Number of allocated areas 510: 3.67 → 4
Number of allocated areas 511: 4.62 → 4
The division widths b, c, and d in the regions 509, 510, and 511 are calculated based on the number of processor elements assigned to each region calculated in this way.

  Similarly, the number of processors allocated to the areas 512, 513, and 514 of the inspection stripe 504 is calculated as follows, with the area 513 being the cell die mixed comparison area.

<Procedure 1>
Load ratio of area 512: 4 × 1 = 4
Load ratio of area 513: 3.8 × 1.5 = 5.7
Load ratio of area 514: 2.4 × 1 = 2.4
<Procedure 2>
Total load ratio = 4 + 5.7 + 2.4 = 12.1
<Procedure 3>
Number of allocated areas 512: 16 × 4 / 12.1 = 5.28
Number of allocated areas 513: 16 × 5.7 / 12.1 = 7.53
Number of allocated areas 514: 16 × 2.4 / 12.2.1 = 3.17
<Procedure 4>
Sum of integer parts: 5 + 7 + 3 = 15
The assignment of the remaining one processor element is determined from the comparison of the fractional part and indexed. Number of assignments in the area 512: 5.28 → 5
Number of allocated areas 513: 7.53-> 8
Number of allocated areas 514: 3.17 → 3
FIGS. 12 and 13 are inspection sequence diagrams of the processor according to the present invention in the inspection stripes 503 and 504 subjected to the above-described image division. In the inspection stripe 503, the processor elements for performing the cell die mixed comparison inspection are eliminated, and a large number of processor elements are allocated to the die comparison inspection area having a high calculation load, so that the entire calculation load is balanced and the intervals 1001 and 1002 are balanced. The difference is reduced. In the inspection stripe 504, it can be seen that the overall calculation load is balanced by assigning more processor elements to the cell die mixed comparison inspection region 513 having a high calculation load. As described above, according to the embodiment of the present invention, the calculation load of each processor element is balanced, and it is not necessary to limit the detection speed of image data to the processing time of a specific processor element.

  FIG. 14 is also a test sequence diagram of the processor according to the present invention. In the test in the test stripe 503 shown in FIG. 12, intervals 1001 and 1002 minutes, which are calculation allowance times obtained by balancing the calculation load, are shown. The operation sequence when the detection speed of image data is increased will be shown. According to the present invention, it is possible to further improve the throughput without increasing the scale of the apparatus and the cost. It becomes.

  FIGS. 15 and 16 are plan views showing an example of chip area division similar to that in FIG. 6, and shows an example of image division when the memory mat portion 502 which is a repetitive pattern is inspected by cell die mixed comparison. FIG. 15 shows an example of image division according to the conventional method, and FIG. 16 shows an example of image division according to the present invention. Divided areas indicated by diagonal lines are cell die mixed comparison inspection areas. The calculation load ratio of the die comparison inspection area is “1”, the calculation load ratio of the cell die mixed comparison inspection in the inspection stripe 1301 is “2”, and the calculation load ratio of the cell die mixed comparison inspection in the inspection stripe 1302 is “1.5”. In this case, when the allocation number of processor elements is calculated in the same manner as in the second embodiment, the area 1304 is “4”, the area 1305 is “9”, the area 1306 is “3”, the area 1307 is “5”, and the area 1308 is “8” and the area 1309 are “3”.

  FIG. 17 is an operation sequence diagram of the processor according to the conventional method in the inspection stripe 1301, and FIG. 18 is an operation sequence diagram of the processor according to the present invention in the inspection stripe 1301. As can be seen from both figures, in the conventional method, both the processor element only for die comparison and the processor element that performs both die comparison and cell comparison are mixed, and the computation time for both die comparison and cell comparison becomes longer. A large difference occurs in the calculation load between the processor elements, and a large number of processor elements that generate a waiting time are generated. On the other hand, according to the method of the present invention, it can be seen that the calculation load is balanced and the dead time can be reduced. By balancing the calculation load in this way, it is possible to fully draw out the calculation capability of the image processing apparatus, to have a sufficient processing capability, or to further increase the detection speed of image data. Etc. can be obtained.

  In the first embodiment described above, a method of performing image processing by dividing an area according to the characteristics of the circuit pattern to be inspected, for example, the repeatability of the circuit pattern has been shown. From another aspect of the present invention, the condition for dividing the area need not be based on the repeatability of the circuit pattern. For example, in a chip, there are a region where the circuit pattern is dense and a region where the circuit pattern is sparse. 19 and 20 are plan views of the chip. As shown in FIG. 19, when there are a dense circuit pattern area 1901 and a coarse area 1902 in the chip 401, the same die comparison inspection or Even in the cell comparison inspection, it is possible to meet a demand for executing processing by changing a detection algorithm for detecting a defect. Alternatively, as shown in FIG. 20, there are areas 2001, 2002, 2003, and 2004 in which there are pattern groups that are likely to cause defects in the chip 401, and only those areas are to be processed using an advanced detection algorithm. It is possible to meet this requirement. This is because if the detection algorithm is changed, the calculation load naturally changes. However, according to the present invention, image division can be performed in consideration of the calculation load for each arbitrary region, and a detection method is performed for each divided image data. This is because, by adding information designating the detection algorithm as attribute data, the inspection conditions can be easily changed for each divided region, so that flexible image processing can be realized.

  Next, specific examples will be described with reference to the drawings regarding the inspection areas and inspection methods required for carrying out the present invention, the calculation load ratio designation method, and the effect confirmation method.

  FIG. 21 is a screen diagram illustrating an example of a designation screen for designating an examination area. This screen is provided as a part of a user interface screen for setting various conditions necessary for defect detection in accordance with the manufacturing conditions of chips processed on the wafer to be inspected, and the overall control computer 106 and interface This is realized at 107. Alternatively, it can be provided by an off-line computer that can be connected to the overall control computer 106 by communication means such as a network.

  A chip selection window 2102 in the screen 2101 is a window for selecting a chip for setting a detection method, an algorithm, recipe information, and the like from the chips 401 arranged in a lattice pattern on the wafer. The operator selects and highlights the chip selection window 2102 with the mouse pointer 2104, and selects a selection method from methods such as all chip designation, row designation, column designation, and individual designation with the area setting button 2105. Select a tip. After selecting the chip, the operator selects an inspection method selection of die comparison inspection, cell comparison inspection, cell die mixed comparison inspection, algorithm selection such as high sensitivity detection and high speed detection, and selection of recipe number from the inspection condition setting button 2106. It can be carried out. The inspection conditions selected here are valid for the entire area of the selected chip.

  When the operator designates an inspection condition for each arbitrary area in the chip, the chip area designation window 2103 is selected with the mouse pointer 2104 and highlighted, and then two points are designated or a numerical value is designated by the area selection button 2105. An arbitrary area is selected from a selection method such as input designation, and designated from the inspection condition setting button 2106 in the same manner as described above.

  After setting all the specified information, the operator presses the setting save button 2107 to confirm the setting information, and closes the screen 2101 with the close button 2108 to complete the specification of the in-chip divided area.

  Next, a procedure for setting the calculation load ratio for each divided area will be described. Usually, after setting information necessary for an inspection by an operator, an inspection called a test inspection for several chips is performed in order to confirm whether there is a problem under the set conditions. The operator calls the screen 2101 after executing the test test, selects a chip for which the calculation load ratio is to be specified in the chip selection window 2102, presses the calculation load adjustment button 2109 in the test condition setting button 2106, and is shown in FIG. Display the calculation load ratio specification screen.

  FIG. 22 is a screen diagram showing an example of the intra-chip calculation load ratio designation screen. In the calculation load ratio inspection result window 2202 in the screen 2201, processing time data required for each processor element sent to the overall control computer 106 from each processor element via the communication bus 114 at the time of executing the test test is displayed. Based on the above, the calculation load ratio obtained for each divided region is displayed as a two-dimensional map. The operator clicks an arbitrary divided area in the inspection result window 2202 with the mouse pointer 2203 and can individually check the calculation load ratio of the divided area clicked on the numerical value box 2204 and the indicator 2205. . Note that this window is not displayed when the trial inspection is not performed. The calculation load ratio designation window 2206 is a window for designating the calculation load ratio of each area. When the operator presses the automatic calculation button 2207, the result of calculating the average value of the calculation load ratio for each region from the result of the trial inspection is displayed in the calculation load ratio designation window 2206. After the operator presses the manual setting button 2208, an arbitrary area in the calculation load ratio designation window 2206 is selected by the mouse pointer 2203, and the calculation load ratio is individually specified by the numerical value box 2204 or the indicator 2205. Any setting of the load ratio is possible. When the operator presses the setting button 2209 after setting the calculation load ratio, the calculation load ratio calculation result window shown in FIG. 23 is displayed. The close button 2210 is a button for ending the display of the intra-chip calculation load ratio designation screen shown in FIG.

  FIG. 23 is a screen diagram illustrating an example of the intra-chip calculation load ratio confirmation screen. In the calculation load ratio calculation result window 2301 in the same screen 2201 as in FIG. 22, the image division calculation described with reference to FIG. 11 is performed according to the information specified in the calculation load ratio specification window 2206, and each image is divided. The calculation load ratio for each divided area is displayed as a two-dimensional map. When the trial inspection is performed, it is also possible to display the corrected result by reflecting the actual processing time data obtained by the trial inspection in the above-described calculation result. If the operator confirms the result and wants to change the setting contents, the operator can return to the original setting screen by pressing the reset button 2302. Further, the operator selects and double-clicks an arbitrary test stripe in the calculation load ratio inspection result window 2202 or the calculation load ratio calculation result window 2301 with the mouse pointer 2203, thereby providing a stripe unit as shown in FIG. The calculation load ratio setting screen can be displayed.

  FIG. 24 is a screen diagram illustrating an example of a calculation load ratio confirmation screen in the inspection stripe. The inspection stripe number box 2402 in the calculation load ratio confirmation screen 2401 displays the number of the inspection stripe displayed on the screen. When the operator directly inputs a numerical value into the inspection stripe numerical value box 2402, the inspection stripe to be displayed on the screen can be changed. The upper window 2403 displays the calculation load ratio inspection result, and the lower window 2404 displays the calculation load ratio calculation result. Since the calculation addition ratio for each processor number is shown in a graph, it is easy for the operator to grasp the situation. In addition, the processors having similar calculation load ratios such as the first group 2405, the second group 2406, and the third group 2407 among the processors are grouped and emphasized by color-coded display or the like for each group. It becomes possible to easily check the change in the number of assigned elements and the change in calculation load. In addition, the operator selects the color-coded display area with the mouse pointer 2408, specifies the calculation load factor with the numerical value box 2409 or the indicator 2410, and presses the setting button 2411 to reflect the setting result and recalculate. The result is displayed in a numerical value box 2409. The close button 2412 is a button for ending the display of the calculation load ratio confirmation screen shown in FIG.

  In this way, it is possible to change not only the calculation load ratio designation for each inspection area, but also the calculation load ratio designation for each inspection stripe. In the actual image processing apparatus 105, since the number of processor elements is limited, there is a possibility that the calculation load is not completely flat even if image division according to the present invention is performed. Therefore, in order to make the best use of the processing capability of the image processing apparatus 105, it may be necessary to make fine adjustments such as in which region more processor elements should be allocated. Even in that case, fine adjustment is possible by providing the function to adjust the calculation load ratio for each inspection stripe as described above, and defect detection is performed by efficiently utilizing the processing capacity of the system. An image processing apparatus for a visual inspection apparatus that can be processed can be provided.

  As described above, in the embodiment of the present invention, the inspection area is designated by dividing the circuit pattern characteristics of the inspected object, for example, a repetitive pattern or a non-repetitive pattern, and an inspection algorithm or Means for designating inspection conditions and the like are provided, and a die comparison inspection area, a cell comparison inspection area, and a cell die mixed comparison area are calculated for each inspection stripe based on the set conditions. Furthermore, a means for giving calculation load information for each calculated area is provided, and a large number of processors are allocated to areas with a large calculation load based on the information, thereby reducing the amount of data to be processed by one processor and reducing the calculation load. A configuration in which a small number of processors are allocated to a region, and the number of processors allocated to each region and the image division width in each inspection stripe is calculated and an image is distributed to detect defects so that one processor processes a larger amount of data. It was adopted. With this configuration, it is possible to efficiently utilize the processing capability of the entire system in image processing by parallel processing using a plurality of processors.

  Further, the image distribution processing unit has a function of adding attribute data such as an inspection algorithm and inspection conditions designated for each inspection area and a block number of transmission data to the divided image data. If the processing is performed according to the information of the processor, even if the processing content is different for each processor or the processing content is changed for each inspection stripe, the processor may operate according to the received data information. Processes such as parameter resetting due to changes can be greatly reduced, and an optimal appearance inspection for performing inspections that include die comparison inspection, cell comparison inspection, and cell die mixed comparison inspection in one inspection. An image processing system can be provided.

  As described above, according to the present invention, it is possible to perform a die comparison inspection, a cell comparison inspection, and a cell die mixed comparison inspection using a plurality of processors by efficiently utilizing the processing capability of each processor, and an image. A processing device can be provided.

101 Stage 102 Wafer 105 Image Processing Device 106 Overall Control Computer 107 Interface 109 Image Distribution Processing Unit 110 Path Switch 111, 112, 113 Processor Element 114 Communication Bus 115 Image Distribution Table 201 Input / Output Controller 202 Bus Arbiter 203 Image Memory 204 Processor 205 Coordinate Table 206 Inspection condition table 401 Chip 402 Inspection stripe 501 Non-repeated pattern area 502 Memory mat part 2101, 2201 Screen 2102 Chip selection window 2103 In-chip area designation window 2104 Mouse pointer 2105 Area setting button 2106 Inspection condition setting button 2202 Inspection result window 2206 Operation Load ratio designation window 2207 Automatic calculation button 2208 Dynamic setting button 2301 operation load ratio calculation result window 2401 operation load ratio confirmation screen

Claims (7)

In an appearance inspection apparatus capable of detecting defects with a plurality of inspection algorithms using image data of a substrate on which a circuit pattern of a semiconductor device is formed,
An overall control computer for setting a condition for cutting out a plurality of image data of the circuit pattern and distributing the plurality of image data to a plurality of processors ;
Accordance with the conditions, cut out the image data, and an image distribution processing section for distributing to the plurality of processors,
The processor performs a defect detection process with a predetermined inspection algorithm for an inspection target region on the substrate using the image data distributed by the image distribution processing unit ,
The overall control computer sets the condition based on the information on the size of the inspection target area processed by one inspection algorithm and the calculation load ratio of the inspection algorithm. . The appearance inspection apparatus according to claim 1,
The whole control computer, the information of the inspection algorithm, which added as the attribute data of the clipped image data,
The visual inspection apparatus, wherein the processor detects a defect with an inspection algorithm selected according to the information of the attribute data. The appearance inspection apparatus according to claim 1,
The division of the image data, or the circuit pattern to be inspected is repeated pattern is divided in a region that is set based on another or a non-repeating pattern, for each of the regions, the die as the inspection algorithm An appearance inspection apparatus characterized in that a comparison inspection, a cell comparison inspection, or a cell die mixed comparison inspection is designated. In the description of the appearance inspection apparatus according to claim 1,
The appearance inspection apparatus characterized in that the condition is the number of processors assigned to the inspection target area and the size of each image data distributed to each of the plurality of processors . The appearance inspection apparatus according to claim 1,
The overall inspection computer displays a calculation load ratio for each processor on a display, and the calculation load ratio can be changed. The appearance inspection apparatus according to claim 5,
An appearance inspection apparatus, wherein a range of division of the image data is changed by changing the calculation load ratio. The appearance inspection apparatus according to claim 1,
A plurality of semiconductor chips are formed on the substrate, and the overall control computer acquires image data for a part of the semiconductor chips, performs a test inspection for detecting defects for the image data, and performs a predetermined inspection on a predetermined area. An appearance inspection apparatus for displaying a calculation load ratio for each processor in the trial inspection on a display.

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