JP3752849B2 - Pattern defect inspection apparatus and pattern defect inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for extracting defects on an inspection object in which portions including a repetitive pattern are arranged at a predetermined pitch, and more particularly to a pattern defect inspection apparatus suitable for visual inspection of semiconductor circuit patterns integrated on a wafer. .
[0002]
[Prior art]
In the manufacture of a semiconductor integrated circuit (such as an LSI), it is possible to extract defects in the formation pattern for each step of forming a circuit pattern and remove the cause of the occurrence of the defect in the semiconductor integrated circuit that is the final product. This is important for improving the yield of good products.
[0003]
Conventionally, in order to automatically extract defects in a semiconductor circuit pattern, for example, a defect inspection apparatus described in Japanese Patent Application Laid-Open No. 59-192943 by the same inventors as the present invention has already been put into practical use. The principle of such a defect inspection apparatus is as follows. First, a semiconductor wafer as an object to be inspected is fixed on a constant-speed moving table, and the image signal is obtained by scanning the surface of the object to be inspected with a line sensor in a direction orthogonal to the movement while moving the object under constant speed. Enter. In this way, since the same pattern is usually repeated at a constant pitch on the semiconductor wafer, a signal having the same waveform repeatedly appears in the input signal. Therefore, a defective portion can be extracted as a portion having a large signal difference by comparing this input signal with an input signal delayed by a repetition pitch.
[0004]
Since the pattern defect inspection apparatus according to this principle can extract defects at a super-high speed compared with humans, it has already been put into practical use as an indispensable evaluation apparatus in many semiconductor integrated circuit production lines. However, the defect information output from the defect inspection apparatus mainly includes defect coordinates. Therefore, in order to investigate the cause of the defect, a review apparatus is further used based on the list of defect coordinate data output from the defect inspection apparatus. It was necessary to visually reexamine each individual extraction defect with another device called "Semiconductor".
[0005]
[Problems to be solved by the invention]
In the prior art, in order to obtain defect data that the user really wants, a visual re-inspection by a review device has to be performed based on a defect coordinate data list from the defect inspection device. Therefore, in order to investigate the cause of the defect, there is a problem that enormous time and labor are required in addition to the processing time of the defect inspection apparatus. Furthermore, since visual re-inspection takes a lot of time, it is not possible to re-inspect all the defects extracted by the pattern defect inspection device, and the entire defect can be re-inspected only by randomly selected defects. The outbreak situation had to be estimated. For this reason, there is a problem that information on important defects having a low occurrence probability is missed.
[0006]
An object of the present invention is to speed up detailed analysis of detected pattern defects by omitting visual re-inspection by a review device in a semiconductor circuit pattern forming process.
[0007]
[Means for Solving the Problems]
Therefore, in the present invention, a configuration is provided in which a high-speed pattern defect inspection apparatus is provided with means for calculating the image feature quantity of the defect in synchronization with the detection of the defect and means for classifying the defect into a cluster based on the calculated feature quantity. It was.
[0008]
In this way, since the defect analysis can be performed only with the pattern defect inspection apparatus, it is possible to investigate the cause by omitting the visual inspection by the review apparatus if the defect analysis is simple. In addition, if a defect inspection device is selected to select a re-inspection defect based on a review device, it is possible to avoid overlooking a specific defect, and the work of investigating the cause of the defect as a whole is greatly accelerated. Can solve the problem.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
(Example)
The processing for calculating the feature amount of each figure included in the image data from the image data sequence input at high speed and continuously by the raster scanning method almost simultaneously with the input of the image data is performed by the same inventors as the present invention. It is described in Japanese Patent Laid-Open No. 63-217479 and is a known technique. By applying this technique, the pattern defect inspection apparatus can calculate the image feature amount of the defect without reducing the defect detection speed. In addition, a technique for classifying defects into clusters based on image feature amounts of defects included in an image is a so-called clustering technique, and various algorithms are known in the technical field. Therefore, the pattern defect inspection apparatus targeted by the present invention can be easily realized by a combination of known techniques. The present invention is characterized by a defect extraction method in this apparatus.
[0010]
Regarding the classification method of defects into clusters, considering the feature space in which each feature amount of the defect area is assigned to each coordinate axis, the cluster is automatically classified from the dense state when each defect data is expressed as one point in it. A method can also be selected, and the occurrence distribution of each defect cluster in the feature space can be measured in advance as the foresight information, and the defects can be classified into known defect clusters based on the foresight information. The former is effective for evaluating a new semiconductor pattern forming process, and the latter is effective for constantly inspecting the same process.
[0011]
As the feature quantity for classifying the defect, the dimension, area, and perimeter are effective for representing the shape, and the gray value of the defect and the corresponding normal area is effective for indicating the type and occurrence area of the defect. Usually, the average gray value of a region is obtained by calculating the sum of the gray values and dividing the result by the calculated area value. Furthermore, the sum of absolute values and the sum of square values of the difference between the gray values of the defect area and the normal area are considered to be effective in determining the degree of defect.
[0012]
The imaging device described above may be one-dimensionally scanned with a finely focused electron beam or light beam on the surface of the object to be inspected, and the resulting change in electron current intensity or light intensity may be input as a video signal. Then, an object is irradiated with an electron beam or illumination light, an electron beam image or an optical image generated thereby is projected onto the array sensor, and an image signal is input by electronically scanning the array sensor. May be. In any case, there is no change in obtaining a video signal by one-dimensionally scanning the surface pattern of the inspection object.
[0013]
The gray value of the image used for calculating the feature amount of the defect is usually a digital image signal obtained by converting the above-described video signal, but an image signal different from the digital image signal used for defect detection can also be used. For example, a gray value obtained by spatially smoothing or edge enhancement processing of the input image signal may be used. Further, if the imaging means is a pattern defect inspection apparatus that can simultaneously input a plurality of video signals, a video signal different from the video signal used for defect portion extraction can be used. For example, when an electron microscope apparatus that obtains secondary electron signals and reflected electron signals as separate video signals is used as an imaging apparatus, one can be used for defect portion extraction and the other can be used for defect feature amount calculation. Further, if color information can be used like a light inspection apparatus, each color component or a linear combination thereof can be used as grayscale image data for feature amount calculation. If the feature quantity for classification is calculated from such various grayscale image data, a pattern defect inspection apparatus with further improved defect classification accuracy can be provided.
[0014]
It should be noted that a publicly known document “Automatic Wafer Inspection System Uzing Pipelined Image Processing Technique” by the inventors of the present invention, IEE Transaction Transaction, AMI, Vol. 10, No. 1, January 1988 ("An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques", IEEE Trans. PAMI, Vol. 10, NO. 1, January 1988), Describes the concept of defect feature calculation based on dimensions and design patterns, and the classification of defects using it. However, this classification is a means for judging the fatality of each defect and improving the reliability as a defect inspection apparatus, and is insufficient as a means for pursuing the cause of the occurrence of the defect. In the present invention, therefore, a new means for calculating an image feature amount based on the grayscale information of the defect pattern portion and the corresponding normal pattern portion almost simultaneously with the extraction of the defect region, and further, the detection is performed based on the calculated feature amount. A means for automatically classifying the detected defects into clusters in the feature space and a means for displaying the defects classified in the cluster are provided so that the cause of the defect occurrence can be investigated quickly.
[0015]
FIG. 1 shows the first embodiment of the present invention and is a block diagram of each device constituting a pattern defect inspection apparatus. This embodiment is an example in the case where a video signal is obtained by scanning an inspection object with an electron beam. In this embodiment, the inspection object 1 is specifically a semiconductor wafer. The inspection object 1 is placed on a movable sample table 2 and repeatedly scanned in a direction intersecting the moving direction of the sample table 2 by an electron beam 4 in which the surface pattern of the inspection object 1 is narrowed down. The electron flow generated by the electron beam scanning is detected by the semiconductor sensor D1, and is input to the high-speed AD converter 6 as a video signal of the semiconductor wafer surface pattern. In this way, since the object to be inspected is moving at a constant speed, the video signal is input as a raster scan image signal having a constant width and an infinite length.
[0016]
FIG. 2 is a perspective view of a semiconductor wafer surface pattern for explaining image input by scanning with an electron beam. When the object to be inspected is a semiconductor wafer pattern, the same pattern is repeatedly arranged on the wafer as shown by P1, P2, and P3 in FIG. When scanning is performed, the sensor D1 detects a video signal having the same pattern for each repetition pitch. Therefore, as shown in FIG. 1, when the video signal converted into a digital signal by the AD converter 6 is once passed through the delay circuit 7 and then passed through the delay circuit 8 for one repetition pitch, the output signal of the delay circuit 7 S1 and the output signal S2 of the delay circuit 8 are video signals having the same pattern and shifted by one pitch. Therefore, if the output signal S1 and the output signal S2 are precisely compared by the defect detection circuit 9, a defect image signal S3 having a defect area “1” can be generated from the magnitude of the density difference. All of these processes are executed in a pipeline manner in units of pixels in synchronization with the input of the video signal. Therefore, the defect image is output as a raster scan image with a corresponding position delayed from the input image by a predetermined time.
[0017]
At this time, in order to accurately detect the defect area, it is necessary to precisely adjust the positional relationship between the output signal S1 and the output signal S2, and the position shift circuit 10 is used for this purpose. The position shift circuit 10 has a delay circuit corresponding to the delay circuit 8 inside, detects a position shift between the output signal S1 and the output signal S2 in advance, and adjusts the delay amount of the delay circuit 8 optimally. The delay circuit 7 described above is provided for correcting a time delay from when the position shift circuit 10 detects the position shift amount to when the delay circuit 8 is adjusted. As for these defect extraction principles, Japanese Patent Laid-Open No. 59-192943, which is the above-mentioned known example, and the known document “Automatic Wafer Inspection System, Uzing, Pipelined Image Processing Technique”, I・ EE Transactions PMI, Volume 10, Issue 1, January 1988 (“An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques”, IEEE Trans. PAMI, Vol. 10, NO.1, January 1988). As the defect extraction circuit 9, the gradation value fluctuation, the deviation amount of one pixel or less detected by the positional deviation circuit 10, an additional calculation for compensating for the fine shape fluctuation of the pattern, and the defect of the detected defect image Although a lot of processing such as image shaping and noise pattern removal can be put into practice, it is omitted here for the sake of clarity.
[0018]
FIG. 3 is a perspective view showing an input image signal as an image for explaining a defect detection method according to this principle. FIG. 3A shows an input image signal 25 input as an infinitely long raster scan image and a defective portion 27 superimposed thereon. FIG. 3B shows a defect image signal 26 output from the input image signal 25 as shown in FIG. If there is a defect portion 27 in the input image, the detected defect image 28 is output with a slight delay. However, since the input defect image is used as the output signal S2 indicating the reference image when the pitch is repeatedly delayed, the pseudo image is reproduced again. A defect detection image 29 is obtained. Although these two defects cannot be distinguished from each other by themselves, the true defects are always detected in pairs at repeated pitch distances from the configuration of the manufacturing apparatus for forming the pattern. By removing pseudo defects by rule, only true defects can be obtained.
[0019]
FIG. 4 is a perspective view of a semiconductor wafer surface pattern for explaining an image input method using a line sensor. Of course, such pattern defect inspection not only scans an electron beam or light in a one-dimensional direction, but also projects an image of the inspection object onto the line sensor 22 using the optical lens 21 as shown in FIG. An image may be detected by the line sensor 22.
[0020]
The defect image signal S3 that is the output of the defect extraction circuit 9 shown in FIG. 1 is input to the feature amount calculation circuit 11, and the position, size, and area of each defect are calculated in real time from the defect image S3. In the present invention, in addition to these features, an output signal S1 indicating an input image density for each defect area, an output signal S2 indicating a reference image density, an output signal S4 indicating a difference absolute value image density , a defect The function is to calculate the sum of values such as the density of the video signal input from a sensor different from the detection and time-adjusted through the delay adjustment circuit 15 and the design pattern density output from the design pattern generation circuit 16 as a defect feature amount. The quantity calculation circuit 11 is provided.
[0021]
This feature amount calculation circuit 11 calculates defect feature amounts in real time in synchronism with the input of a defect image every time a defect image appears based on defect image data input in a raster scan according to a fixed pixel clock. The contents are as described in Japanese Patent Laid-Open No. 63-217479, which is a well-known example described above.
[0022]
The calculated feature amount is stored in the result memory 12 every time the calculation is completed, and is read into the control computer 13 every time the inspection of one unit area is completed. The control computer 13 is a computer that controls the entire pattern defect inspection apparatus. The sample table control circuit 3 controls the operation of the sample table, the timing generation circuit 14 controls the entire inspection processing execution timing, and the design pattern generation. The pattern data is stored in the circuit 16 to realize the function as an inspection apparatus. Further, the image recognition circuit 18 inputs image data at a position of a specific pattern on the inspection object into an internal image memory under the control of the computer, and performs a correlation operation with a template pattern serving as a reference pattern stored in advance. The position of the specific pattern on the image is precisely measured. The amount of deviation between the position where the specific pattern should exist and the actually measured position is calculated from the position coordinates of the sample stage 2 and the position coordinates of the specific pattern on the inspection object, and is input to the control computer 13.
[0023]
The timing generation circuit 14 deflects the electron beam 4 deflected by the electron beam deflection control circuit 5 based on the information from the control computer 13 and the position information of the sample table 2 from the sample table control circuit 3 that controls the position of the sample table 2. It controls the position, deflection timing, signal input timing of the AD converter 6 and design pattern generation circuit 16, and the like. Actually, the timing signal is also sent from the timing generation circuit 14 to other circuit blocks, but a detailed description is not necessary in the description of the embodiment of the present invention, and is omitted. The defect feature data fetched into the control computer 13 is classified by the software of the control computer, and the classification result is displayed on the display device 17.
[0024]
Next, a calculation method of the feature amount calculation circuit 11 will be described. However, since this method is detailed in the above-mentioned JP-A-63-217479, only its concept will be described here. FIG. 5 shows an image for extracting defect feature amounts. FIG. 5A is an input image, and FIG. 5B is an explanatory diagram in which the input image is simplified for each line.
[0025]
In this method, first, an input image as shown on the left side of FIG. 5A is processed by a simple cyclic filter, and a control image on the right side in which a hole and a concave portion downward are included in a binary figure. Create When such a modification is applied, the figure shape in the control image is simplified, and all figures are the four shapes shown in FIG. 5B when attention is paid only to the image data of two consecutive raster scan lines. Only appears. That is, if one particular line of interest is defined as the J line, the HEAD in which a part of the graphic appears for the first time, the TAIL in which the graphic ends at the J-1 line, and the graphic on the J-1 line are directly connected to the J line. There are four possible forms of BODY-2 in which a plurality of figures on the -1 and J-1 lines are combined into one figure on the J line. Here, one figure on the J-1 line may be branched into a plurality of figures on the J line, but such a figure does not exist at all in the control image subjected to the above-described modification.
[0026]
The feature amount calculation is sequentially executed on the control image in the raster scan order. Monitors the connection status of two consecutive lines of raster scanning. If there is HEAD shown in FIG. 5B, the partial feature amount of the partial image on the J line is stored as the intermediate feature amount of the J line. If there is, what is stored as the intermediate feature amount of the J-1 line is output to the outside as a defect feature amount. If it is BODY-1, the intermediate feature amount of the J-1 line is read, the partial feature amounts on the J line are synthesized, and stored again as the intermediate feature amount of the J line. Further, if BODY-2, the intermediate feature amount of the corresponding graphic on the J-1 line is synthesized, and the partial feature amount on the J line is also synthesized and stored again as the intermediate feature amount of the J line. If this process is performed in synchronization with the input of each line, the defect feature amount calculation synchronized with the input of the image data can be performed almost simultaneously. After the intermediate feature value of the J line is stored, the intermediate feature value of the previous J-1 line need not be stored. Therefore, the storage circuit for the J-1 line does not need to store the next J + 1 line. It can be used as a storage location for intermediate features. Therefore, if there are storage locations for two lines, the feature quantities of all defects can be calculated without increasing the storage locations, regardless of how many lines are provided.
[0027]
FIG. 6 is a block diagram of the feature quantity calculation circuit, showing a more detailed embodiment of the feature quantity calculation circuit 11. The defect image signal S3 is processed by the control image generation circuit 31, and a control image signal S21 is generated. The control signal generation circuit 32 processes the control image signal S21 to generate a control signal S22 for calculating the feature amount. The feature quantity calculation circuits 33a, 33b, 33c, 33d, 33e, and 33f are controlled by the control signal, and calculate the feature quantity of the defect according to each input image data.
[0028]
In the feature amount calculation circuit 11 of FIG. 1, six signals are input as inputs. In FIG. 6, output signals other than the defect image signal S3 are represented by output signals S11, S12, and S13. . The defect coordinate value, X dimension, Y dimension, and area are calculated from the defect image signal S3 by the feature amount calculation circuits 33a, 33b, and 33c, and the feature amount calculation circuits 33d, 33e, and 33 are calculated from the signals of the output signals S11, S12, and S13. In 33f, the total value of the respective image gray values on the defect image signal S3 is calculated. The output signals S11, S12, and S13 correspond to one of the inputs of the feature quantity calculation circuit 11 in FIG. 1, respectively, but those signals obtained by performing a filtering process such as spatial differentiation can also be used. Since these feature amount calculations are executed in synchronization with the scanning of the defect area, all feature amounts relating to the same defect image are output at the same timing. The fatal defect determination circuit 34 determines the size and area and outputs only those that are considered to be fatal defects to the result memory 12 together with other feature amounts. In the pattern defect inspection of a wafer, since a lot of minute pseudo defects that normally do not have fatalities are detected, the fatal defect determination circuit 34 is important in the sense that the result memory 12 does not easily overflow.
[0029]
The feature values that are the sum of the gray values are taken into the control computer, and then divided by the area value to be converted into an easy-to-handle average density value. The defect feature quantities finally arranged by the computer are stored as a defect data list as shown in FIG. FIG. 7 shows an example of the defect feature quantity list. As the first embodiment of the feature quantity of the present invention, the X coordinate, the Y coordinate, the X dimension, the Y dimension, the area, the circumference, the defect shading, the non-defective density, and the non-defective product differentiation. The figure shows the shading, difference shading, and design data. Among these, the defect density is the sum of the density values of the output signal S1 indicating the input image density inside the defect area and divided by the area. The non-defective density is the density value of the output signal S2 indicating the reference image density. The sum total divided by the area, the non-defective product grayscale is the sum of the grayscale images obtained by differentiating the output signal S1 indicating the input image density and calculating the absolute value, and the difference grayscale is the output signal S1 and the output The absolute value of the difference value when the signal S2 is precisely compared is calculated by dividing the sum of the output signal S4 indicating the density of the image by the area, and the design data is such that the inside of a specific pattern is 1. The sum of the binary images generated by the generation circuit 16 inside the defect is divided by the area. The process of summing the values of the grayscale image inside the defect area is a process generally called “volume” calculation, and all the feature quantity calculation processes described here including the volume calculation are the above-mentioned JP-A-63-217479. This is the same method as that described in the publication.
[0030]
Here, the data used as the design pattern may be automatically created from the pattern data used when forming the pattern on the inspection object, or graphic software may be used based on the imaging data of the inspection object. It may be created interactively by using it, or may be obtained by thresholding the gray value of the captured image data of the object to be inspected.
[0031]
FIG. 8 shows an example of the extracted defect image. In FIG. 8, (a) is an input image including a defect, (b) is a reference image to be compared, and (c) is an example of a defect image. In the input image of FIG. 8A, input defect patterns 52, 53, and 54 exist in addition to the circuit pattern 51. When the image grayscale values are different between the inside and the outside of the circuit pattern 55 in the reference image, the internal defect 57 and the external defect 58 can be obtained by using the non-defective product density that is the density of the normal area corresponding to the extracted defect area as the feature amount. Can be identified. Further, if the non-defective product differential density, which is the differential density of the normal area corresponding to the extracted defect area, is used as the feature amount, it is possible to identify the defect 56 at the boundary, the internal defect 57 and the external defect 58. As described above, if the above-described various feature quantities are calculated and used for the extracted defect, cluster classification of various defects becomes possible.
[0032]
FIG. 9 is an explanatory diagram of the defect distribution in the feature space, in which the obtained defects are plotted on the feature space with the feature amounts as coordinate axes. FIG. 9A shows the two-dimensional coordinate axis with the non-defective product density and the defect density. In this way, bright defects on a dark pattern and dark defects on a bright pattern clearly form clusters C1 and C2. FIG. 9B shows a non-defective product differential concentration and defect size as two-dimensional coordinate axes. In this way, a defect on a pattern boundary having a change in brightness and a defect not separated are separated as clusters C4 and C3. I can do it. Although not shown in the figure, if a feature quantity called design data is used, defects inside and outside the area designated as the design pattern can be separated as clusters.
[0033]
Therefore, if the detected defect is classified into clusters according to the feature amount, it is possible to analyze the cause of the defect to some extent without performing visual re-inspection by the review device. FIG. 10 is a flowchart showing a method of defect cluster classification. In the cluster classification, when the occurrence probability distribution of each cluster to be classified in advance is known, the occurrence distribution function for each classification cluster is input as shown in FIG. 10A, and each defect is classified into the class having the highest occurrence probability. By doing so, it becomes feasible. When the occurrence state of each cluster is completely unknown, for example, as shown in FIG. 10B, the cluster can be automatically estimated from the dense state of the occurrence defects in the feature space. This procedure is roughly as follows.
[0034]
(1) The distance on the feature space between arbitrary defects is calculated in advance.
[0035]
(2) As an initial state, it is assumed that all defects constitute one cluster.
[0036]
(3) Initially set a threshold value, and if the distance between the clusters is smaller than a certain threshold value, merge the clusters into one cluster. However, the distance between clusters is the distance between defects that are the closest constituent elements.
[0037]
(4) Increase the threshold value a little.
[0038]
(5) If the threshold exceeds a predetermined upper limit or the number of clusters is smaller than a predetermined lower limit, the process ends. Otherwise, repeat (3).
[0039]
By performing such processing, cluster classification can be performed even if the defect occurrence distribution is unknown. FIG. 11 is an example of an image in which each classified defect is displayed for each cluster in units of wafers and chips.
[0040]
Defects classified into different clusters are likely to have occurred due to different causes of occurrence, so if you perform visual re-inspection at a certain rate for each cluster, re-inspect defects with low occurrence probability without oversight. I can do it. In particular, in the case of semiconductor pattern inspection, such a function is extremely effective because an extremely large number of defects of the same type may occur. Furthermore, even if the cluster classification is automatically performed, if the occurrence distribution function is calculated for each cluster and the cluster classification based on the distribution function is performed for the same inspection after the next time, only the number of defects is obtained. Compared with the case where management is performed, the temporal quality change of the same process can be grasped in more detail. FIG. 12 shows an example of an image when the occurrence probability distribution measuring wafer in which the defect is formed is used. As a method for obtaining the occurrence probability distribution function for each cluster to be classified, as shown in FIG. 12, a test wafer in which a possible defect is intentionally created is automatically inspected, and each cluster divided in a known area is divided. The occurrence probability distribution function of the detected defect may be calculated for each defect. In this way, troublesome visual re-inspection can be omitted, and automatic classification into defects similar to built-in defects can be realized.
[0041]
FIG. 13 shows a second embodiment of the present invention, and is a configuration diagram in which main parts in FIG. 1 are configured via a network. In FIG. 13, reference numeral 41a denotes a defect detection unit that inspects a pattern to calculate a defect feature amount, and 43 denotes a defect classification display unit that performs defect classification and display from the defect feature amount. In this embodiment, these two parts are connected by a local area network, and a defect data list is transferred from the defect detection unit 41a to the defect classification display unit 43 as necessary. Normally, it is necessary to place the defect detection unit in a clean room. However, if the classification display unit is separated in this way, the classification display unit can be placed in another management room, so that the usability can be further improved. Furthermore, a plurality of defect detection units 41b of other pattern defect inspection apparatuses can be combined and processed by the same classification display unit. Further, if the review device 44 is coupled to the same network, the visual inspection candidates selected for each cluster can be sent directly from the classification display unit to the review device 44, and the defect cause investigation work can be further expedited. Can be
[0042]
According to the above embodiment, the following effects can be obtained.
[0043]
(1) Defect classification and result display are possible almost simultaneously with defect inspection. This eliminates the need for a new visual re-inspection by a review device, and speeds up the work of investigating the cause of defects by external defect inspection.
[0044]
(2) Even when visual re-inspection is performed by the review device, re-inspection candidate determination based on the defect cluster classification result can be performed, so that it is less likely to miss a fatal defect with a low occurrence frequency.
[0045]
(3) The defect occurrence frequency for each cluster can be monitored unattended, and the quality variation in the semiconductor pattern forming process can be closely monitored.
[0046]
【The invention's effect】
As described above, according to the present invention, in the semiconductor circuit pattern forming process, the visual re-inspection by the review device can be omitted, and the detailed analysis of the detected pattern defect can be accelerated.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of each device constituting a pattern defect inspection apparatus according to a first embodiment of the present invention.
FIG. 2 is a perspective view of a semiconductor wafer surface pattern for explaining image input by scanning with an electron beam.
FIG. 3 is a perspective view showing an input image signal as an image for explaining a defect detection method;
FIG. 4 is a perspective view of a semiconductor wafer surface pattern for explaining an image input method by a line sensor.
FIG. 5 is an explanatory diagram showing an image for extracting defect feature amounts.
FIG. 6 is a configuration diagram of a feature amount calculation circuit.
FIG. 7 shows an example of a defect feature amount list.
FIG. 8 is a diagram showing an example of an image of an extracted defect.
FIG. 9 is an explanatory diagram of defect distribution in a feature space.
FIG. 10 is a flowchart showing a method of defect cluster classification;
FIG. 11 is a view showing an example of an image in which classified defects are displayed for each cluster.
FIG. 12 is a diagram showing an example of an image when a wafer for occurrence probability distribution measurement in which a defect is made is used.
FIG. 13 is a block diagram showing a second embodiment of the present invention, in which the main part in FIG. 1 is configured via a network.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Test object, 2 ... Sample stand, 3 ... Sample stand control circuit, 4 ... Electron beam, 5 ... Electron beam deflection control circuit, 6 ... AD converter, 7, 8 ... Delay circuit, 9 ... Defect detection circuit, DESCRIPTION OF SYMBOLS 10 ... Position shift circuit 11, 33a, 33b, 33c, 33d, 33e, 33f ... Feature quantity calculation circuit, 12 ... Result memory, 13 ... Control computer, 14 ... Timing generation circuit, 15 ... Delay adjustment circuit, 16 ... Design Pattern generation circuit, 17 ... display device, 18 ... image recognition circuit, 21 ... optical lens, 22 ... line sensor, 25 ... input image signal, 26 ... defect image signal, 27 ... defective portion, 28 ... detected defect image, 29 ... Defect detection image, 31... Control image generation circuit, 32... Control signal generation circuit, 34... Fatal defect determination circuit, 41 a, 41 b .. defect detection unit, 42. ... Road pattern, 52, 53, 54 ... input defect pattern, 55 ... circuit pattern, 56 ... defects, 57 ... internal defects, 58 ... external defects.

Claims (7)

In a pattern defect inspection apparatus for inspecting a pattern of an object to be inspected in which portions including a repetitive pattern are arranged at a predetermined pitch,
A sample stage for fixing the object to be inspected and moving in a direction in which portions including the repetitive pattern are arranged;
An image pickup means for inputting a video signal obtained by scanning the pattern of the inspection object in a one-dimensional direction in a direction intersecting the moving direction while moving the inspection object by the sample stage;
Conversion means for converting the video signal obtained by the imaging means into a multi-value digital signal;
A first digital signal obtained by converting the video signal by the conversion means, and a scanning position obtained by scanning the inspection object by the imaging means at a position shifted by at least the predetermined pitch from the scanning position from which the first digital signal was obtained. Comparing means for comparing the second digital signal obtained by converting the video signal by the converting means and extracting a defective area of the pattern;
As the feature amount of each defect included in the defect area extracted by the comparison means,
Area, dimensions, perimeter of the defect area,
The gray value of the image of the defective area,
The gray value of the image of the normal area corresponding to the defect area,
The gray value of an image obtained by spatial differentiation of an image of a normal area corresponding to the defect area,
The gray value of the image obtained as a difference between the normal area where the defects of the pattern are not extracted and the defective area,
The shade value of the design pattern image corresponding to the defect area,
Calculating means for calculating at least one feature amount of the feature amounts calculated from another sensor image corresponding to the defect region in synchronization with extraction of the defect region;
Classification means for classifying the individual defects according to the calculated feature amount;
A pattern defect inspection apparatus comprising: display means for displaying a result classified by the classification means. The imaging device scans the surface of the inspection object with a narrowed electron beam,
2. The pattern defect inspection apparatus according to claim 1, wherein the intensity of the electron flow obtained as a result is input as a video signal.   The imaging apparatus is characterized in that a surface pattern of the inspection object is imaged on an array sensor, and a signal obtained by electronically scanning the sensor array is imaged as a video signal. The pattern defect inspection apparatus according to 1.   2. The pattern defect inspection apparatus according to claim 1, further comprising means for selecting a defect that is a candidate for reinspection based on a result of the classification means.   The classifying means classifies the individual defects into clusters in a feature space, and automatically determines a defect occurrence probability distribution function for each cluster by inspecting a wafer in which defects are formed. The pattern defect inspection apparatus according to claim 1, further comprising a calculating unit.   2. The pattern defect inspection apparatus according to claim 1, wherein a portion having the defect feature amount calculation means and a portion having the classification result display means are coupled by a communication line. In a pattern defect inspection method for inspecting a defect of a pattern of an object to be inspected in which portions including a repetitive pattern are arranged at a predetermined pitch,
The inspection object is fixed to a sample stage and moved in the direction in which the portions including the repetitive pattern are arranged,
While moving the inspection object by the sample stage, input a video signal obtained by scanning the pattern of the inspection object in a one-dimensional direction in a direction intersecting the moving direction;
Converting the video signal into a first digital signal, converting the video signal into a second digital signal at a position shifted by at least the predetermined pitch from a scanning position where the first digital signal was obtained;
Comparing the first digital signal and the second digital signal;
Extracting defect areas of the pattern;
As the feature amount of each defect included in the extracted defect area, the area, size, circumference length of the defect area,
The gray value of the image of the defective area,
The gray value of the image of the normal area corresponding to the defect area,
The gray value of an image obtained by spatial differentiation of an image of a normal area corresponding to the defect area,
The gray value of the image obtained as a difference between the normal area where the defects of the pattern are not extracted and the defective area,
The shade value of the design pattern image corresponding to the defect area,
Calculating at least one feature amount of the feature amounts calculated from another sensor image corresponding to the defect region in synchronization with the extraction of the defect region;
Classify individual defects according to the calculated feature values;
A pattern defect inspection method comprising the step of displaying the classified results.

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