JP3660763B2 - Inspection pattern inspection method, manufacturing process diagnosis method, and semiconductor substrate manufacturing method - Google Patents

Description

なお、前記第１の統計情報生成回路１７ａは、Ｘ軸およびＹ軸方向についての繰返しパターンの統計情報である濃淡またはエッジ位置の統計画像をＣＰＵにおいて算出することについて説明したが、Ｘ軸またはＹ軸方向のみの繰返しパターンの統計情報である濃淡またはエッジ位置の統計画像をＣＰＵにおいて算出してもよいことは明らかである。それはパターンが繰返される方向の違いによって濃淡またはエッジ位置の統計画像に変化が見られないからである。
【００３０】
図２には、多層に積層されたメモリマット部２１における２次元に繰返される一つのパターン（メモリセル）の濃淡統計画像を示す。
図２（ａ）には、濃淡の標準偏差σ（ｉ，ｊ）×ｋの統計画像を示す。６１は表面層のパターンであるため、ランダムに発生する面荒れやグレインの影響を大きく受けて、濃淡の標準偏差（明るさのばらつき）が大きくなって明かるい画像信号となる。６２は下層のパターンであり、表面層のパターン６１と重なる部分については表面層のパターンで消され、それ以外の領域については下層であるため、ランダムに発生する面荒れやグレインの影響が減衰されて濃淡の標準偏差（明るさのばらつき）が小さくなって暗い画像信号となる。従って、この濃淡の標準偏差σ（ｉ，ｊ）×ｋの濃淡統計画像信号に応じて比較回路１８ａにおけるセル比較差画像に対して欠陥を判定する際または欠陥候補を抽出する際の感度を変えることができる。即ち、表面層のパターン２１は明かるさ（濃淡）のばらつきが大きいことからして感度を低下させ、下層のパターン２２は明かるさ（濃淡）のばらつきが小さいことからして感度を高めて欠陥判定または欠陥候補を抽出すればよい。
図２（ｂ）には、濃淡の平均値ｇ(ｉ,ｊ)の統計画像を示す。６１は表面層のパターンであって、平均的には比較的暗い画像信号として検出される。６２は下層のパターンであり、表面層のパターン６１に比べて平均的に明るい画像信号として検出される。濃淡の平均値ｇ(ｉ,ｊ)の画像は、５〜２０個程度の２次元の繰返しパターンに亘って検出される検出画像信号の平均値を示すもので、欠陥を検査するために検出画像信号ｆ（ｉ，ｊ）と比較するのに適した基準の画像信号を被検査対象のウェーハから得ることができる。従って、メモリマット部２１において隣接したセル（繰返しパターン）から検出される検出画像信号同士を比較するのに比べて、ランダムに発生する面荒れやグレインの影響を軽減して欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
【００３１】
図２（ｃ）には、濃淡の最小値ｍｉｎ（ｉ，ｊ）の統計画像を示す。６１は表面層のパターンであって、図２（ｂ）に示すように平均的には比較的暗い画像信号に対して図２（ａ）に示すように標準偏差（明るさのばらつき）が大きいことからして、最小値の画像は非常に暗く検出される。６２は下層のパターンであり、図２（ｂ）に示すように表面層のパターン６１に比べて平均的に明るい画像信号に対して図２（ａ）に示すように標準偏差（明るさのばらつき）が小さいことからして、最小値ｍｉｎ（ｉ，ｊ）の画像は図２（ｂ）に示す画像信号に比べて僅か暗く検出される。濃淡の最大値ｍａｘ（ｉ，ｊ）の統計画像は、図２（ｂ）に示すように平均的には比較的暗い画像信号に対して図２（ｃ）に示す画像と対称なる関係となる。従って、濃淡（明るさ）の最大値と最小値との差Ｒ（ｉ，ｊ）＝ｍａｘ（ｉ，ｊ）−ｍｉｎ（ｉ，ｊ）の統計画像は、５〜２０個程度の２次元の繰返しパターンから検出される検出画像信号のばらつく（変動する）範囲を示すことになる。また濃淡の最大値と最小値とのメディアン値の統計画像は、ほぼ濃淡の平均値ｇ(ｉ,ｊ)の統計画像と同じことになる。また濃淡の標準偏差の統計画像の代わりに、濃淡（明るさ）の最大値と最小値との差Ｒ（ｉ，ｊ）の統計画像を用いることができる。
また第１の統計情報生成回路１７ａによって生成される多層に積層されたメモリマット部２１における２次元に繰返されるパターン（メモリセル）のエッジ位置の統計画像には、エッジ位置（微分画像信号若しくは２値化画像信号の何方でも良い。）の平均値またはメディアン値ｇ(ｉ,ｊ)に関する画像とエッジ位置のばらつきを示すエッジ位置の標準偏差σ（ｉ，ｊ）に関する画像とエッジ位置のとりうる範囲を示すエッジ位置の最大値と最小値との差Ｒ（ｉ，ｊ）＝ｍａｘ（ｉ，ｊ）−ｍｉｎ（ｉ，ｊ）の画像とがある。これら平均値もしくはメディアン値ｇ（ｉ，ｊ）、標準偏差σ（ｉ，ｊ）、最大値ｍａｘ（ｉ，ｊ）、最小値ｍｉｎ（ｉ，ｊ）、もしくは最大値と最小値との差Ｒ（ｉ，ｊ）等を、エッジ位置の統計画像の各項目（パラメータ）と称する。エッジ位置の最大値と最小値とのメディアン値の統計画像は、ほぼエッジ位置の平均値ｇ(ｉ,ｊ)の統計画像と同じことになる。またエッジ位置の標準偏差の統計画像の代わりに、エッジ位置の最大値と最小値との差Ｒ（ｉ，ｊ）の統計画像を用いることができる。
【００３２】
レジストの塗布むら、ステッパによる露光の解像度、スパッタやＣＶＤによる成膜の膜厚のばらつき、エッチング条件のばらつき等のプロセス条件の変動（例えばウェーハ上の中央部と周辺部との間における変動やロット単位による変動やウェーハの品種に基づく変動等様々の変動要因がある。）に基づいて、図４に示すようにパターンのエッジの出来具合が変化することになる。即ち、図４（ａ）、（ｂ）に示す如く、パターンのエッジがエッチング等のプロセス条件によって明確度（だれ具合）や図４（ｃ）に示すように子細にみると微小な凹凸も含め線幅がウェーハ内で部分的にばらつき現象が生じる。繰返しパターン毎に、図４（ａ）に示すエッジのだれ具合が、図４（ｂ）に示すエッジのだれ具合より小であるように、繰返しパターン毎にだれ具合が大きく異なり、だれ具合を示す微分画像の標準偏差であるパラメータは大きくなる。また繰返しパターン毎に、図４（ｃ）に示すように子細にみると微小な凹凸も含め線幅がばらつき、その結果パターンのエッジ位置を示す微分画像または２値化画像の標準偏差であるパラメータが大きくなる。この他ロット単位や品種に応じてもパターンのエッジのばらつき現象が生じる。
【００３３】
エッジ位置の平均値ｇ(ｉ,ｊ)の画像は、５〜２０個程度の２次元の繰返しパターンに亘って検出される検出画像信号の平均値を示すもので、欠陥を検査するために検出画像信号ｆ（ｉ，ｊ）と比較するのに適した基準の画像信号を被検査対象のウェーハから得ることができる。従って、メモリマット部２１において隣接したセル（繰返しパターン）から検出される検出画像信号同士を比較するのに比べて、プロセス条件の変動によってランダムに発生するパターンのエッジの出来具合の影響を軽減して欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
またエッジ位置の標準偏差σ（ｉ，ｊ）の統計画像信号に応じて比較回路１８ａにおけるセル比較差画像に対して欠陥を判定する際または欠陥候補を抽出する際の感度を変えることによって、プロセス条件の変動によってパターンのエッジの出来具合が変化したとしても欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
【００３４】
第２の統計画像生成回路１７ｂは、Ａ／Ｄ変換器２から出力される濃淡に応じたディジタル画像信号９に対して図３（ａ）に示すように１次元に（例えばＹ軸方向に）パターンが繰返される周辺回路部２２における繰返されるパターンの濃淡（明るさ）統計画像若しくは濃淡（明るさ）統計データからなる濃淡統計情報またはエッジ抽出回路２８から出力されるパターンのエッジ位置を示す信号４２に対して１次元にパターンが繰返される周辺回路部２２における繰返されるパターンのエッジ位置を示す統計画像若しくはパターンのエッジ位置を示す統計データからなるエッジ位置統計情報を生成するものである。この第１の統計情報生成回路１７ｂは、５〜２０個程度の１次元の繰返しパターンに亘って検出される検出画像信号（検出濃淡画像信号または検出エッジ位置画像信号）を順次記憶するラインメモリ４３ｂと、該ラインメモリ４３ｂから対応する位置（ｉ,ｊ＋lＰy'）の検出画像信号ｆ'(ｉ,ｊ＋lＰy')を読み出して平均値もしくはメディアン値ｇ'（ｉ，ｊ）（次に示す（数３）式で示される。）、標準偏差σ'（ｉ，ｊ）（次に示す（数４）式で示される。）、最大値ｍａｘ'（ｉ，ｊ）、最小値ｍｉｎ'（ｉ，ｊ）、もしくは最大値と最小値との差Ｒ'（ｉ，ｊ）＝ｍａｘ'（ｉ，ｊ）−ｍｉｎ'（ｉ，ｊ）を算出するＣＰＵ４４ｂと、該ＣＰＵ４４ｂで算出された平均値もしくはメディアン値ｇ'（ｉ，ｊ）、標準偏差σ'（ｉ，ｊ）、最大値ｍａｘ'（ｉ，ｊ）、最小値ｍｉｎ'（ｉ，ｊ）、もしくは最大値と最小値との差Ｒ'（ｉ，ｊ）等からなる統計情報を記憶するメモリ４５ｂとから構成される。すなわち、前記第２の統計情報生成回路１７ｂは、１次元にパターンが繰返される周辺回路２２において５〜２０個程度の１次元の繰返しパターンから、対応する位置（ｉ,ｊ＋lＰy'）の明るさｆ’(ｉ,ｊ＋lＰy')の平均値もしくはメディアン値ｇ'（ｉ，ｊ）、標準偏差σ'（ｉ，ｊ）、最大値ｍａｘ'（ｉ，ｊ）、最小値ｍｉｎ'（ｉ，ｊ）、もしくは最大値と最小値との差Ｒ'（ｉ，ｊ）＝ｍａｘ'（ｉ，ｊ）−ｍｉｎ'（ｉ，ｊ）を検出するものである。（ｉ，ｊ）は繰返しパターン上の座標を示す。Ｐy'は、図３（ａ）に示すように１次元の繰返しパターンの一軸方向である例えばＹ方向のピッチを示す。このピッチＰy'は、ウェーハの品種によって変化するので、ＣＰＵ４４ｂに対してウェーハの品種に応じたピッチＰy'を登録しておき、ウェーハの品種の情報を入力することによって登録されたピッチＰy'の情報から入力されたウェーハの品種に適合するものを選択することができる。即ち、第２の統計情報生成回路１７ｂは周辺回路部２２におけるパターンの統計情報である濃淡またはエッジ位置の統計画像を生成するものであるため、ＣＰＵ４４ｂは、ＣＡＤシステムにつながった通信ネットワーク、キーボード、ディスク等から構成された入力手段１２で入力された設計情報に基づいて得られるウェーハ４上におけるチップ内の配列データ等の座標に基づいて、周辺回路部２２の領域であると判定すると共に、この判定された周辺回路部２２に対して上記入力手段１２で入力された設計情報に基づいて得られる周辺回路部２２における繰返しパターンのＹ方向のピッチＰy'またはチップ単位のピッチに基づいて、繰返しパターンの統計情報である濃淡またはエッジ位置の統計画像を生成することができる。またＣＰＵ４４ａは、メモリマット部２１の領域である否かを判定することができるので、周辺回路部２２の領域であることも判定することができる。従って、ＣＰＵ４４ｂは、上記ＣＰＵ４４ａから周辺回路部２２の領域である信号５６を受けることによって周辺回路部２２の領域であることを判定すると共に、周辺回路部２２に対して上記入力手段１２で入力された繰返しパターンのＹ方向のピッチＰy'またはチップ単位のピッチを設定することができる。
【００３５】

また、周辺回路部２２についてはチップ単位で繰返されることになるので、第２の統計画像生成回路１７ｂは、Ａ／Ｄ変換器２から出力される濃淡に応じたディジタル画像信号９に対してチップ単位で繰返される周辺回路部２２におけるパターンのチップ単位の濃淡（明るさ）統計画像若しくは濃淡（明るさ）統計データからなる濃淡統計情報またはエッジ抽出回路２８から出力されるパターンのエッジ位置を示す信号４２に対してチップ単位で繰返される周辺回路部２２におけるパターンのチップ単位のエッジ位置を示す統計画像若しくはパターンのエッジ位置を示す統計データからなるエッジ位置統計情報を生成するものであっても良い。この場合、ラインメモリ４３ｂには、チップ単位の画像を数個程度に亘って記憶する必要がある。それはＣＰＵ４４ｂがチップ単位で対応する位置（ｉ,ｊ＋lＰy'）の検出画像信号ｆ'(ｉ,ｊ＋lＰy')を読み出して平均値もしくはメディアン値ｇ'（ｉ，ｊ）、標準偏差σ'（ｉ，ｊ）、最大値ｍａｘ'（ｉ，ｊ）、最小値ｍｉｎ'（ｉ，ｊ）、もしくは最大値と最小値との差Ｒ'（ｉ，ｊ）＝ｍａｘ'（ｉ，ｊ）−ｍｉｎ'（ｉ，ｊ）を算出する必要があるからである。
【００３６】
以上説明したように、第２の統計情報生成回路１７ｂによって周辺回路部２２におけるパターンの統計情報である濃淡またはエッジ位置の統計画像（平均値もしくはメディアン値ｇ'（ｉ，ｊ）、明るさ（濃淡）またはエッジ位置の標準偏差σ'（ｉ，ｊ）、または明るさ（濃淡）またはエッジ位置の最大値と最小値との差Ｒ'（ｉ，ｊ）等）を生成し、この生成された濃淡またはエッジ位置の統計画像をメモリ４５ｂに記憶させることによって得ることができる。そして第２の統計画像生成回路１７ｂからは、上記各統計量に対応して、例えば複数の８ビットディジタル信号で出力するように構成する。
【００３７】
図３（ｂ）（ｃ）には、多層に積層された周辺回路部２２におけるパターンの一部の濃淡統計画像を示す。
図３（ｂ）には、濃淡の標準偏差σ'（ｉ，ｊ）×ｋの統計画像を示す。６３は表面層のパターンであるため、ランダムに発生する面荒れやグレインの影響を大きく受けて、濃淡の標準偏差（明るさのばらつき）が大きくなって明かるい画像信号となる。６５、６６、６７のパターンは濃淡の標準偏差（明るさのばらつき）が中程度で中程度の明るさを有する画像信号となる。６４および６８は下層のパターンであり、表面層のパターン６３と重なる部分については表面層のパターンで消され、それ以外の領域については下層であるため、ランダムに発生する面荒れやグレインの影響が減衰されて濃淡の標準偏差（明るさのばらつき）が小さくなって暗い画像信号となる。従って、この濃淡の標準偏差σ（ｉ，ｊ）×ｋの濃淡統計画像信号に応じて比較回路１８ｂにおける繰返しパターン比較またはチップ比較差画像に対して欠陥を判定する際または欠陥候補を抽出する際の感度を変えることができる。即ち、表面層のパターン２３は明かるさ（濃淡）のばらつきが大きいことからして感度を低下させ、下層のパターン６４および６８は明かるさ（濃淡）のばらつきが小さいことからして感度を高めて欠陥判定または欠陥候補を抽出すればよい。
【００３８】
図３（ｃ）には、濃淡の平均値ｇ'(ｉ,ｊ)の統計画像を示す。６３、６４および６８のパターンは、平均的に明るい画像信号として検出される。６６および６７のパターンは、平均的に中程度の明るい画像信号として検出される。６５のパターンは、平均的に暗い画像信号として検出される。濃淡の平均値ｇ'(ｉ,ｊ)の画像は、５〜２０個程度の１次元の繰返しパターンまたは数チップ単位に亘って検出される検出画像信号の平均値を示すもので、欠陥を検査するために検出画像信号ｆ'（ｉ，ｊ）と比較するのに適した基準の画像信号を被検査対象のウェーハから得ることができる。従って、周辺回路部２２においても隣接した繰返しパターンから検出される検出画像信号同士を比較するのに比べて、ランダムに発生する面荒れやグレインの影響を軽減して欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
周辺回路部２２においても、メモリマット部２１と同様に、濃淡（明るさ）の最大値と最小値との差Ｒ'（ｉ，ｊ）＝ｍａｘ'（ｉ，ｊ）−ｍｉｎ'（ｉ，ｊ）の統計画像は、５〜２０個程度の１次元の繰返しパターンまたは数チップ単位に亘って検出される検出画像信号のばらつく（変動する）範囲を示すことになる。従って濃淡の最大値と最小値とのメディアン値の統計画像は、ほぼ濃淡の平均値ｇ'(ｉ,ｊ)の統計画像と同じことになる。また濃淡の標準偏差の統計画像の代わりに、濃淡（明るさ）の最大値と最小値との差Ｒ'（ｉ，ｊ）の統計画像を用いることができる。
【００３９】
また第２の統計情報生成回路１７ｂによって生成される多層に積層された周辺回路部２２における１次元に繰返されるパターン（メモリセル）のエッジ位置の統計画像には、エッジ位置（微分画像信号若しくは２値化画像信号の何方でも良い。）の平均値またはメディアン値ｇ'(ｉ,ｊ)に関する画像とエッジ位置のばらつきを示すエッジ位置の標準偏差σ'（ｉ，ｊ）に関する画像とエッジ位置のとりうる範囲を示すエッジ位置の最大値と最小値との差Ｒ'（ｉ，ｊ）＝ｍａｘ'（ｉ，ｊ）−ｍｉｎ'（ｉ，ｊ）の画像とがある。エッジ位置の最大値と最小値とのメディアン値の統計画像は、ほぼエッジ位置の平均値ｇ'(ｉ,ｊ)の統計画像と同じことになる。またエッジ位置の標準偏差の統計画像の代わりに、エッジ位置の最大値と最小値との差Ｒ'（ｉ，ｊ）の統計画像を用いることができる。
【００４０】
レジストの塗布むら、ステッパによる露光の解像度、スパッタやＣＶＤによる成膜の膜厚のばらつき、エッチング条件のばらつき等のプロセス条件の変動（例えばウェーハ上の中央部と周辺部との間における変動やロット単位による変動やウェーハの品種に基づく変動等様々の変動要因がある。）に基づいて、図４に示すようにパターンのエッジの出来具合が変化することになる。即ち、図４（ａ）、（ｂ）に示す如く、パターンのエッジがエッチング等のプロセス条件によって明確度（だれ具合）や図４（ｃ）に示すように子細にみると微小な凹凸も含め線幅がウェーハ内で部分的にばらつき現象が生じる。繰返しパターン毎に、図４（ａ）に示すエッジのだれ具合が、図４（ｂ）に示すエッジのだれ具合より小であるように、繰返しパターン毎にだれ具合が大きく異なり、だれ具合を示す微分画像の標準偏差であるパラメータは大きくなる。また繰返しパターン毎に、図４（ｃ）に示すように子細にみると微小な凹凸も含め線幅がばらつき、その結果パターンのエッジ位置を示す微分画像または２値化画像の標準偏差であるパラメータが大きくなる。この他ロット単位や品種に応じてもパターンのエッジのばらつき現象が生じる。
エッジ位置の平均値ｇ'(ｉ,ｊ)の画像は、５〜２０個程度の１次元の繰返しパターンに亘って検出される検出画像信号の平均値を示すもので、欠陥を検査するために検出画像信号ｆ'（ｉ，ｊ）と比較するのに適した基準の画像信号を被検査対象のウェーハから得ることができる。従って、周辺回路部２２において隣接したセル（繰返しパターン）またはチップ単位から検出される検出画像信号同士を比較するのに比べて、プロセス条件の変動によってランダムに発生するパターンのエッジの出来具合の影響を軽減して欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
またエッジ位置の標準偏差σ'（ｉ，ｊ）の統計画像信号に応じて比較回路１８ｂにおけるセル比較またはチップ比較の差画像に対して欠陥を判定する際または欠陥候補を抽出する際の感度を変えることによって、プロセス条件の変動によってパターンのエッジの出来具合が変化したとしても欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
【００４１】
次にパターンの欠陥検査およびパターンの出来具合について定量化することについて説明する。
第１の比較回路１８ａは、例えば図８に示す第１の統計情報である第１の統計画像信号（ｇi,j）１０ａと第１の遅延メモリ３ａから得られる第１の検出画像信号（ｆi,j）１１ａとの間の位置ずれを検出して位置合わせを行う位置合わせ回路４６ａと、欠陥を判定するための比較パラメータが設定された比較パラメータ設定手段４７ａと、上記位置合わせ回路４６ａで位置合わせされた第１の統計画像信号（ｇ'ｉ+Δx,j+Δy）４９ａと第１の遅延メモリ３ａから得られる第１の検出画像信号（ｆ'i,j）５０ａとを比較パラメータ設定手段４７ａで設定された比較パラメータに基づいて比較して特徴量を抽出して欠陥候補または欠陥を抽出処理するＣＰＵ４８ａとから構成される。比較パラメータ設定手段４７ａは、第１の統計情報生成回路１７ａにより生成されたメモリマット部２１における濃淡若しくはエッジ位置の標準偏差σ（ｉ，ｊ）または濃淡若しくはエッジ位置の最大値と最小値との差Ｒ（ｉ，ｊ）に基づいて、ＣＰＵ４８ａにおいて特徴量を抽出して欠陥候補または欠陥を抽出処理するための比較パラメータを設定することができる。また比較パラメータ設定手段４７ａは、プロセス装置（例えばステッパ等の露光装置、エッチング装置、ＣＶＤまたはスパッタ等の成膜装置、レジスト塗布装置等）につながった通信ネットワーク、キーボード、ディスク、ウェーハの品種やロットを読み取る読取装置等から構成された入力手段１２で入力されたプロセス条件（露光条件、エッチング条件、成膜条件、レジスト塗布条件等）やウェーハの品種やロットに応じて設定することもできる。要するに、欠陥候補や欠陥の判定基準をウェーハの品種やロットに応じて変えてやる必要があるからである。またプロセス条件に応じて欠陥候補や欠陥の判定基準を変えることもできるようにした。
【００４２】
以上説明したように、第１の比較回路１８ａにおいて、まず位置合わせ回路４６ａは、例えば図８に示す第１の統計情報である第１の統計画像信号（ｇi,j）１０ａと第１の遅延メモリ３ａから得られる第１の検出画像信号（ｆi,j）１１ａとの間の位置ずれを検出して位置合わせを行う。次にＣＰＵ４８ａは、上記位置合わせ回路４６ａで位置合わせされた第１の統計画像信号（ｇ'ｉ+Δx,j+Δy）４９ａと第１の遅延メモリ３ａから得られる第１の検出画像信号（ｆ'i,j）５０ａとを比較パラメータ設定手段４７ａで設定された比較パラメータに基づいて比較して特徴量（濃淡（明るさ）の不一致量、および２値化画像の不一致の面積や最大長さや不一致の重心座標（位置座標）等）を抽出して発生位置を示す重心座標（位置座標）を含めて欠陥候補または欠陥の信号５１ａを抽出処理する。即ち、第１の統計画像信号（ｇi,j）１０ａは、メモリマット部２１についてのセル比較における平均化された基準画像信号となり、ＣＰＵ４８ａにおいて、ランダムに発生する面荒れやグレインの影響を軽減し、またはプロセス条件の変動によってランダムに発生するパターンのエッジの出来具合の影響を軽減し、欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。また、メモリマット部２１において、標準偏差σ（ｉ，ｊ）の統計画像信号に応じて比較パラメータを設定することによって、比較回路１８ａにおけるセル比較の差画像に対して欠陥を判定する際または欠陥候補を抽出する際感度を変えることが可能となり、パターンから得られる明かるさ（濃淡）のばらつきに合わせて感度を設定して欠陥判定または欠陥候補を抽出することができ、またパターンのエッジの出来具合に合わせて感度を設定し、欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
【００４３】
また第２の比較回路１８ｂにおいて、まず位置合わせ回路４６ｂは、例えば図８に示す第２の統計情報である第２の統計画像信号（ｇi,j）１０ｂと第２の遅延メモリ３ｂから得られる第１の検出画像信号（ｆi,j）１１ｂとの間の位置ずれを検出して位置合わせを行う。次にＣＰＵ４８ｂは、上記位置合わせ回路４６ｂで位置合わせされた第２の統計画像信号（ｇ'ｉ+Δx,j+Δy）４９ｂと第２の遅延メモリ３ｂから得られる第２の検出画像信号（ｆ'i,j）５０ｂとを比較パラメータ設定手段４７ｂで設定された比較パラメータに基づいて比較して特徴量（濃淡（明るさ）の不一致量、および２値化画像の不一致の面積や最大長さや不一致の重心座標（位置座標）等）を抽出して発生位置を示す重心座標（位置座標）を含めて欠陥候補または欠陥の信号５１ｂを抽出処理する。即ち、第２の統計画像信号（ｇi,j）１０ｂは、周辺回路部２２についてのセル比較またはチップ比較における平均化された基準画像信号となり、ＣＰＵ４８ｂにおいて、ランダムに発生する面荒れやグレインの影響を軽減し、またはプロセス条件の変動によってランダムに発生するパターンのエッジの出来具合の影響を軽減し、欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。また、周辺回路部２２において、標準偏差σ'（ｉ，ｊ）の統計画像信号に応じて比較パラメータを設定することによって、比較回路１８ｂにおけるセル比較またはチップ比較の差画像に対して欠陥を判定する際または欠陥候補を抽出する際感度を変えることが可能となり、パターンから得られる明かるさ（濃淡）のばらつきに合わせて感度を設定して欠陥判定または欠陥候補（特徴量で示される場合も含む）を抽出することができ、またパターンのエッジの出来具合に合わせて感度を設定し、欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。
【００４４】
なお、第１の比較回路１８ａおよび第２の比較回路１８ｂは、本発明者らが開発した方式、特開昭６１−２１２７０８号公報記載の技術に示したもの等で差し支えなく、例えば画像の位置合わせ回路４６ａおよび４６ｂや、図１８に示すように、位置合わせされた画像の差画像検出部１３６と該差画像検出部１３６で検出される差画像を閾値Ｖthにより２値化して２次元の不一致を検出する不一致検出部１３７と該不一致検出部１３７で検出された２値化不一致画像からノイズ成分を、図１５に示す位置合わせ、境界部感度制御回路３５より得られるフィルタ選択信号１４０によって選択されたフィルタによって除去するフィルタ部１３８と該フィルタ回路１３８によってノイズ成分が除去された２値化不一致画像から不一致部分（欠陥部または欠陥候補部）の面積や長さ（投影長）、座標などの特徴量を算出する特徴量抽出部１３９とを備えたＣＰＵ４８ａおよび４８ｂで構成してもよい。またＣＰＵ４８ａおよび４８ｂは、差画像検出部１３６、不一致検出部１３７、フィルタ部１３８および特徴量抽出部１３９の各々を回路構成で実現しても良い。そして、第１の比較回路１８ａおよび第２の比較回路１８ｂにおいて、統計画像と検出画像とを比較する場合、検出画像の着目画素の明るさ（濃淡値）が、統計画像の対応画素における平均値の明るさに対して標準偏差のｋ倍（例えばｋ＝３）のレンジ内にあれば正常と判定し、そのレンジ外にあれば欠陥または欠陥候補として判定して出力することができる。
【００４５】
上記の場合は、第１の比較回路１８ａおよび第２の比較回路１８ｂにおいて、欠陥または欠陥候補の有無について判定したが、図６（ｂ）に誇張して示すように、プロセス条件に応じたパターンの出来具合の情報になるレンジからのずれ量ΔＧや平均値からのずれ量ΔＧ’を不一致量（斜線で示す。）として出力してもよい。この場合、検出画像に欠陥が含まれれば欠陥候補の情報となり、検出画像に欠陥が含まれていない場合にはパターンの出来具合を示す情報となる。いずれにしても、欠陥候補の情報であったとしても、ＣＰＵ１９における処理の仕方でパターンの出来具合を示す情報として取り扱うことができる。
また、第１の比較回路１８ａおよび第２の比較回路１８ｂにおいて、上記比較パラメータを種々変えて複数回検査し、これら複数回の検査結果の論理和をとって、最終結果としてもよいことは、後述する照明条件の場合と同様である。
また、第１の比較回路１８ａおよび第２の比較回路１８ｂにおいて、パターンの仕上り具合に応じて、欠陥または欠陥候補を抽出できることは明らかである。
【００４６】
ＣＰＵ１９は、第１の比較器１８ａから比較パラメータの設定で感度が最適化されて得られるメモリマット部２１における発生位置を示す重心座標（位置座標）を含めて欠陥候補（特徴量を示すデータで提供される場合も含む）または欠陥の信号５１ａと、第２の比較器１８ｂから比較パラメータの設定で感度が最適化されて得られる周辺回路部２２における発生位置を示す重心座標（位置座標）を含めて欠陥候補（特徴量を示すデータで提供される場合も含む）または欠陥の信号５１ｂと、第１の統計情報生成回路１７ａから得られるメモリマット部２１における統計情報１０ａと、第２の統計情報生成回路１７ｂから得られる周辺回路部２２における統計情報１０ｂと、プロセス装置（例えばステッパ等の露光装置、エッチング装置、ＣＶＤまたはスパッタ等の成膜装置、レジスト塗布装置等）および上位のＣＡＤシステムにつながった通信ネットワーク、キーボード、ディスク、ウェーハの品種やロットを読み取る読取装置等から構成された入力手段１２で入力されたプロセス条件やウェーハの品種やロットの情報および設計情報に基づいて得られるウェーハ４上におけるチップ内も含む配列データ等の座標情報等とに基づいて欠陥候補については詳細解析すると共にパターンの出来具合を解析するものである。
【００４７】
即ち、ＣＰＵ１９は、第１の比較器１８ａから得られる比較パラメータの設定で感度が最適化されて得られるメモリマット部２１における発生位置を示す重心座標（位置座標）を含めて欠陥候補（特徴量を示すデータで提供される場合も含む）５１ａに対して詳細解析をすることによって、真の欠陥として判定することができる。例えば、第１の比較器１８ａから繰返されるパターンに合わせて規則的に欠陥候補の信号５１ａが発生した場合には、この欠陥候補の信号５１ａをウェーハ４上におけるチップ内も含む配列データ等の座標情報等を用いて消去して真の欠陥を検出することもできる。また第１の比較器１８ａから得られる特徴量（濃淡（明るさ）の不一致量、および２値化画像（エッジ位置を示す画像も含む）の不一致の面積や最大長さや不一致の重心座標（位置座標）等）で示される欠陥候補の信号５１ａに対して、真の欠陥であると判定する判定基準を、プロセス条件やウェーハの品種やロットの情報およびウェーハ４上における配列データ等に応じて変えて最適条件で真の欠陥を検出することができる。欠陥の種類も、図４（ｃ）に示すように欠け欠陥７１と突出欠陥７２と孤立欠陥７３等が存在し、これら欠陥の種類に応じて判定基準を変える必要がある。例えば、不一致の面積によって真の欠陥として判定する場合には、判定基準として面積を欠陥の種類に応じて変える必要がある。
【００４８】
またＣＰＵ１９は、メモリマット部２１と同様に、周辺回路部２２に対しても第２の比較器１８ｂから得られる比較パラメータの設定で感度が最適化されて得られる周辺回路部２２における発生位置を示す重心座標（位置座標）を含めて欠陥候補（特徴量を示すデータで提供される場合も含む）または欠陥の信号５１ｂに対して詳細解析することによって最適条件で真の欠陥を検出することができる。そしてＣＰＵ１９は検査された欠陥情報５７ａを、発生位置を示す重心座標（位置座標）を含めて出力できるように例えば記憶装置１３に記憶することができる。
またＣＰＵ１９は、第１の比較器１８ａおよび第２の比較器１８ｂから得られる特徴量で示される欠陥候補の信号５１ａおよび５１ｂをディスプレイ等の表示手段５２に表示してモニターすることができる。この際、入力手段１２で入力されたプロセス条件やウェーハの品種やロットの情報およびウェーハ４上における配列データ等も併記して表示手段５２に表示することができ、欠陥検査の面でパターンの製造プロセス状態を監視することができる。
なお、第１の比較回路１８ａからはメモリマット部２１の比較結果が得られ、第２の比較回路１８ｂからは周辺回路部２２の比較結果が得られるが、ＣＰＵ１９は、例えば入力手段１２で入力されたウェーハ上の座標情報に基づいてメモリマット部２１であるか、周辺回路部２２であるかを識別して第１の比較回路１８ａからの比較結果と第２の比較回路１８ｂからの比較結果とを選択して最終判定をしても良い。また、ＣＰＵ１９は、上記第１の比較器１８ａによるメモリマット部２１におけるセル比較と上記第２の比較器１８ｂによる周辺回路部２１におけるセル比較またはチップ比較との選択を次のように行ってもよい。すなわち、ＣＰＵ１９は、上記第１の比較器１８ａから得られるセル比較による不一致情報、例えば不一致画素数を定めた範囲の画像ごとに算出し、これがしきい値より大きい場合にはメモリマット部２１の領域ではないと判定できることにより、上記第２の比較器１８ｂから得られる周辺回路部２２についての結果を選択し、不一致画素数がしきい値より小さい場合にはメモリマット部２１の領域であると判定できることにより、上記第１の比較器１８ａから得られる結果を選択することができる。この方法によれば、ＣＰＵ１９において、チップ内の配列情報がなくてもチップ比較とセル比較の選択が可能となる。
【００４９】
またＣＰＵ１９は、遅延メモリ２３ａおよび２３ｃに記憶された第１および第２の統計画像１０ａおよび１０ｂ並びに遅延メモリ２３ａおよび２３ｃに記憶された検出画像信号１１ａおよび１１ｂを、例えば欠陥信号または欠陥候補の信号５１ａおよび５１ｂに基づいて得られる切出し信号２４により切出し回路２５を介して切出して詳細解析を行っても良いことは明らかである。
またＣＰＵ１９において、メモリマット部２１および周辺回路部２２に対してパターンの出来具合を定量化して解析する場合には、第１の統計情報生成回路１７ａから得られるメモリマット部２１における統計情報１０ａと、第２の統計情報生成回路１７ｂから得られる周辺回路部２２における統計情報１０ｂとを用いて行う。そしてＣＰＵ１９はパターンの出来具合を定量化したデータ５７ｂとして出力できるように例えば記憶装置１３に記憶することができる。
即ち、多層パターンにおいて表面にグレインや面荒れを有するパターンが表面層に存在するか下層に存在するかに応じて、このパターンから得られる濃淡画像９において大きくばらつき、その結果例えば図２（ａ）に示すように第１の統計情報生成回路１７ａから得られるメモリマット部２１における濃淡の統計情報１０ａである濃淡の標準偏差σ（ｉ，ｊ）および最小値と最大値との差Ｒ（ｉ，ｊ）のパラメータは大きくなり、また図３（ｂ）に示すように第２の統計情報生成回路１７ｂから得られる周辺回路部２２における濃淡の統計情報１０ｂである濃淡の標準偏差σ'（ｉ，ｊ）および最小値と最大値との差Ｒ'（ｉ，ｊ）のパラメータは大きくなる。
【００５０】
またＣＰＵ１９は、エッジ抽出回路２８から得られるパターンのエッジ位置を示す画像信号４２に基づいて第１の統計情報生成回路１７ａから得られるメモリマット部２１におけるエッジ位置の統計情報１０ａである平均値ｇ（ｉ，ｊ）およびエッジ位置の標準偏差σ（ｉ，ｊ）および最小値と最大値との差Ｒ（ｉ，ｊ）のパラメータにもとづいてメモリマット部のパターンの出来具合を定量化することができ、第２の統計情報生成回路１７ｂから得られる周辺回路部２２におけるエッジ位置の統計情報１０ｂである平均値ｇ'（ｉ，ｊ）（図３（ａ）に示す。）およびエッジ位置の標準偏差σ'（ｉ，ｊ）および最小値と最大値との差Ｒ'（ｉ，ｊ）のパラメータにもとづいて周辺回路部のパターンの出来具合を定量化することができる。即ち、ＣＰＵ１９は、一枚のウェーハ４において、第１および第２の統計情報生成回路１７ａ，１７ｂから得られる中央部におけるエッジ位置の統計情報と周辺部におけるエッジ位置の統計情報とを比較することによって、一枚のウェーハ４内の中央部と周辺部との違いを把握することができる。統計情報が平均値の場合、ウェーハ４内の中央部と周辺部とのパターン幅およびパターンのエッジの傾き（エッチングによるパターンの切れ具合）等の平均的な違いを定量的に把握することができる。
【００５１】
またＣＰＵ１９は、第１および第２の統計情報生成回路１７ａ，１７ｂからウェーハ４のロット単位に得られるエッジ位置の統計情報を比較することによって、ロット単位における違いを把握することができる。統計情報が平均値の場合、ロット単位におけるパターン幅およびパターンのエッジの傾き（エッチングによるパターンの切れ具合）等の平均的な違いを定量的に把握することができる。
またＣＰＵ１９は、第１および第２の統計情報生成回路１７ａ，１７ｂからウェーハ４の品種に応じて得られるエッジ位置の統計情報を比較することによって、ウェーハの品種に応じた違いを把握することができる。統計情報が平均値の場合、ウェーハの品種に応じたパターン幅およびパターンのエッジの傾き（エッチングによるパターンの切れ具合）等の平均的な違いを定量的に把握することができる。
またＣＰＵ１９は、図６（ａ）に示すように、第１および第２の統計情報生成回路１７ａ，１７ｂから得られるエッジ位置の統計情報の内のエッジ位置を示す平均値統計画像（図６（ａ）の右側に示す。）と、入力手段１２を用いて入力されたＣＡＤ情報に基づく理想的な基準画像（設計仕様に基づく基準画像）（図６（ａ）の左側に示す。）とを矢印で示すように局所領域ごとのマッチングをとることによって局所領域ごとのずれ量を求め、このずれ量の総和をパターンが存在する領域に亘ってとることによって、設計値に対するパターンの違い（線幅を変動やエッジのだれ具合の変化等）を定量的に把握することができる。即ち、大きな面積領域でパターンのエッジがだれている場合でも、パターンの変形度合いを定量化して出力することができる。
【００５２】
ところで、実際に製造されるパターンの形状は、設計値と微妙に異なる場合が多い。そこで、ＣＰＵ１９は、ＣＡＤ情報に基づく理想的な基準画像と比較するのではなく、実際に撮像してＡ／Ｄ変換器２から検出され、遅延メモリ２３ｂおよび２３ｄに記憶された検出画像信号から標準の検出画像信号５３を、切出し指定信号２４により切出回路２５において切り出して選びだすことができる。
【００５３】
そして、ＣＰＵ１９は、図６（ｂ）に誇張して示すように、選び出された標準の検出画像信号５３に対して、第１および第２の統計情報生成回路１７ａ，１７ｂから得られるエッジ位置を示す平均値統計画像ｇ（ｉ，ｊ）に対して標準偏差σ（ｉ，ｊ）等を用いて設定された許容値±ΔＥより外れた不一致量（斜線で示す。）を算出することによって、パターンの出来具合（線幅、エッチングによる切れ具合等による変形の度合い）を定量化して把握することができる。なお、上記許容値±ΔＥについては、入力手段１２を用いて任意に設定してもよい。また上記平均値統計画像ｇ（ｉ，ｊ）と標準の検出画像信号５３とは、微分画像信号同士であってもよい。その場合、不一致量として微分画像信号の差信号の積分値となる。
【００５４】
なお、上記の実施の形態では、標準の検出画像信号５３を遅延メモリ２３ｂおよび２３ｄから切出して選び、この選び出された標準の検出画像信号５３に対して、第１および第２の統計情報生成回路１７ａ，１７ｂから得られるエッジ位置を示す平均値統計画像ｇ（ｉ，ｊ）に対して標準偏差σ（ｉ，ｊ）等を用いて設定された許容値±ΔＥより外れた不一致量（斜線で示す。）を算出することによって、パターンの出来具合を定量化して把握するようにしたが、第１および第２の比較器１８ａおよび１８ｂから得られるエッジ位置の不一致量（エッジ位置の統計画像である平均値ｇ（ｉ，ｊ）に対する標準偏差σ（ｉ，ｊ）に基づくレンジからの検出画像ｆ（ｉ，ｊ）におけるエッジ位置のずれ量やエッジ位置の統計画像である平均値ｇ（ｉ，ｊ）からの検出画像ｆ（ｉ，ｊ）におけるエッジ位置のずれ量）を、ＣＰＵ１９において所定のパターンの領域（例えばセル単位）について総計、またはチップ単位で総計、またはウェーハ単位で総計することによって、所定のパターンの領域（例えばセル単位）またはチップ単位またはウェーハ単位でパターンの出来具合を定量化して把握することができ、その結果この定量化されたパターンの出来具合の情報を、露光やエッチングや成膜やレジスト塗布等のプロセス条件の尺度として用いることができる。
【００５５】
また上記した如く、第１および第２の統計情報生成回路１７ａ，１７ｂから得られるエッジ位置の統計情報（平均値および標準偏差）は、直接露光やエッチングや成膜やレジスト塗布等のプロセス条件の尺度として用いることができる。
【００５６】
当然ＣＰＵ１９において得られるパターンの出来具合を定量化したデータ５７ｂに対して、入力手段１２で入力されたプロセス条件やウェーハの品種やロットの情報および設計情報に基づいて得られるウェーハ４上におけるチップ内も含む配列データ等の座標情報等を付与して出力できるように例えば記憶装置１３に記憶することもできることは明らかである。
【００５７】
次に、図１に示す実施の形態と異なる実施の形態を図７を用いて説明する。この実施の形態においては、第１の比較器１８ａにおいて第１の遅延メモリ３ａから得られる検出画像信号１１ａと遅延メモリ５４ａで繰返しパターンのピッチＰx，Ｐyの整数倍遅延させた検出画像信号１１ｂとをセル比較し、位置合わせ回路４６ａで位置合わせされた検出画像信号５０ａと検出画像信号５０ｃとに対して比較パラメータ設定手段４７ａで設定された比較パラメータに基づいて特徴量を抽出して欠陥候補または欠陥を抽出処理し、第２の比較器１８ｂにおいて第２の遅延メモリ３ｂから得られる検出画像信号１１ｂと遅延メモリ５４ｂで繰返しパターンのピッチＰy'の整数倍またはチップのピッチ遅延させた検出画像信号１１ｄとをセル比較またはチップ比較し、位置合わせ回路４６ｂで位置合わせされた検出画像信号５０ｂと検出画像信号５０ｄとに対して比較パラメータ設定手段４７ｂで設定された比較パラメータに基づいて特徴量を抽出して欠陥候補または欠陥を抽出処理することにある。そして、第１の統計情報生成回路１７ａから得られる第１の統計情報１０ａを第１の比較器１８ａの比較パラメータ設定手段４７ａに入力し、第２の統計情報生成回路１７ｂから得られる第２の統計情報１０ｂを第２の比較器１８ｂの比較パラメータ設定手段４７ｂに入力したことにある。この実施の形態の場合、第１および第２の比較器１８ａおよび１８ｂにおいて検出画像信号同士を比較して差画像を抽出し、この抽出された差画像に対して欠陥候補または欠陥を抽出処理する際の判定基準（比較パラメータ）に各々第１の統計情報生成回路１７ａから得られる第１の統計情報１０ａおよび第２の統計情報生成回路１７ｂから得られる第２の統計情報１０ｂを用いることにある。
【００５８】
ところで、第１の比較器１８ａにおいて判定基準（比較パラメータ）として、第１の統計情報生成回路１７ａから得られる第１の統計情報１０ａである例えばばらつきを示す標準偏差σ（ｉ，ｊ）や最大値と最小値の差Ｒ（ｉ，ｊ）が用いられ、第２の比較器１８ｂにおいて判定基準（比較パラメータ）として、第２の統計情報生成回路１７ｂから得られる第２の統計情報１０ｂである例えばばらつきを示す標準偏差σ'（ｉ，ｊ）や最大値と最小値の差Ｒ'（ｉ，ｊ）が用いられ、多層パターンにおいて表面にグレインや面荒れを有するパターンが表面層に存在するか下層に存在するかに応じて、このパターンから得られる濃淡検出画像９において大きくばらついたとしても、またプロセス条件の変動によってパターンの出来具合に変化が生じたとしても、第１および第２の比較器１８ａおよび１８ｂにおいて欠陥判定または欠陥候補の抽出を高信頼度で実現することができる。なお、ＣＰＵ１９における演算処理は、図１に示す実施の形態と同様とする。
【００５９】
また上記比較パラメータを種々変えて複数回検査し、これら複数回の検査結果の論理和をとって、最終結果としてもよいことは、次に説明する照明条件の場合と同様である。
【００６０】
以上説明したように、統計情報生成回路１７ａ、１７ｂで生成された統計情報は様々な形態で使用することができる。
統計情報または統計画像は、例えば基準または標準の検出画像、比較パラメータの設定、詳細解析するためのパラメータ、パターンの出来具合を定量化するためのパラメータ、ウェーハ内、ロット単位およびウェーハの品種に応じた変化の指標として用いることができる。
なお、上記説明した実施の形態では、照明として、明視野照明を採用したが、これに限るものでなく、暗視野照明、輪帯照明などの顕微鏡照明として使用できるものならば、差し支えない。また、電子線による照明でも適用できることは言うまでもない。
ただし、例えば、パターンエッジは明視野照明では暗く観察されるが、暗視野照明では明るく観察されるなど、見え方の違いは存在するため、統計画像において、その認識が異なってくる。従って、主に何を比較するかがその照明によって異なるものとなる。
これらの照明条件を種々変えて、複数回検査し、これら複数回の検査結果の論理和を取って最終結果としても差し支えない。或いは、論理積をとって確実に欠陥として識別し、例えばこの欠陥分布や個数によってプロセス診断してもよい。この場合、不一致部の目視確認を行うレビューは不要として作業の簡素化、簡易化を図ることもできる。
【００６１】
次に上記構成の検査装置の動作について説明をする。即ち、図１において、対物レンズ６で収束させた照明光で、ステージ５を走査して被検査パターンの半導体ウエハ４の対象領域について等速度で移動させつつ、イメージセンサ１により前記半導体ウエハ４上に形成された被検査パターン、すなわちチップ２０内のメモリマット部２１および周辺回路部２２の明るさ情報（濃淡画像信号）を検出する。そして、前記対象領域と前記対象領域の間は高速に移動させる。
すなわち、等速移動と高速移動の繰り返しに検査を行うものである。もちろん、ステップ＆リピート型の検査でも差し支えない。そして、Ａ／Ｄ変換器２は、イメージセンサ１の出力（濃淡画像信号）をディジタル画像信号９に変換する。このディジタル画像信号９は１０ビット構成である。
次いで、ディジタル画像信号９またはパターンのエッジを示す信号４１に対して、第１の統計画像生成回路１７ａによりメモリマット部２１における統計画像等の統計情報を生成する。第１の比較器１８ａはメモリマット部２１における特徴量で示される欠陥または欠陥候補の信号（データ）を抽出する。またディジタル画像信号９またはパターンのエッジを示す信号４１に対して、第２の統計画像生成回路１７ｂにより周辺回路部２２における統計画像等の統計情報を生成する。第２の比較器１８ｂは周辺回路部２２における特徴量で示される欠陥または欠陥候補の信号（データ）を抽出する。ＣＰＵ１９は、第１および第２の比較器１８ａ、１８ｂで抽出された欠陥または欠陥候補の信号（データ）に基づいて詳細解析して真の欠陥の情報を算出し、また第１および第２の統計画像生成回路１７ａ、１７ｂから得られる統計画像等の統計情報に基づいてパターンの出来具合を定量化して把握する。その結果、ＣＰＵ１９からは、真の欠陥の情報とパターンの出来具合を定量化した情報とを得ることが出来る。
【００６２】
またＣＰＵ１９から、統計画像そのものを出力し、これをプロセスと対応づけること、またはこれと素子の電気特性データの相関をとり、プロセスの改善に役立たせることもできる。
ここで、電気特性データとは、メモリ素子のアクセス時間等をさすものであり、統計画像と電気特性の結果の良否データと相関をとって、プロセス改善に役立たせることもできる。ここで、例えばパターンのエッジの位置の標準偏差は、パターンのエッジのばらつきを表すので、露光装置やエッチング装置の状態モニターとして活用できる。設計データを利用して、どの層がパターンエッジばらつきが大きいかを調べれば、その特定層と関係するプロセス装置まで特定することができる。
【００６３】
また、本発明に係るパターンの検査装置は、図１、図７および図１７に示すように、遅延メモリ（画像格納メモリ）２３ａ〜２３ｄを有し、ＣＰＵ１９において切り出し回路２５を切り出し信号２４により駆動することにより、特徴量で示される欠陥または欠陥候補の抽出に用いられた２枚の画像のいずれかまたは両方を欠陥または欠陥候補の抽出と同時に１部を切り出して入力して記憶し、この記憶した画像を用いて欠陥または欠陥候補の有無以外の特徴量で示される欠陥寸法や欠陥の明るさなどの詳細情報を得ることも可能である。具体的には、検査中または検査後に、格納された画像データをＣＰＵ１９により読み出し、ＣＰＵ１９上で画像解析を行う。ＣＰＵ１９における画像解析は、第１および第２の比較回路１８ａ、１８ｂから得られる正常部を示す統計画像と欠陥部を有する検出画像の差画像（不一致）に基づく特徴量（濃淡差画像に基づく明るさの不一致量、差画像に対して２値化処理された不一致の２次元の面積、その形状（例えば円形度、長さ）、正常部に対する欠陥部の明るさの大小、不一致内部の明るさのばらつき等）の抽出に対して多岐にわたって詳細解析をすることができる。さらに、ＣＰＵ１９は、不一致（特徴量で示される欠陥または欠陥候補）に対応する正常部のパターンの状態評価、即ちパターンの形状、見え方を評価し、欠陥部のパターンの見え方と対応をとることにより、欠陥がパターンに与えた影響を把握することができる。例えば、切出し回路２５によって切り出された欠陥部を有する検出画像において、切出し回路２５によって切り出された正常部である統計画像と同様にパターンのエッジが見えれば、膜厚が変化したような欠陥（ウオータマークなど）と判断できる。例えば切出し回路２５によって切り出された欠陥部を有する検出画像において、パターンエッジが無くなっていれば、パターン自体の損傷など、形状的な欠陥（エッチング不良など）と判断できる。従って、ＣＰＵ１９は、欠陥の分類が可能になる。勿論、ニューラルネットワーク等の技術を用いて、パターンの特徴や欠陥の特徴により分類しても良い。更には、欠陥が生じた位置なども、パターンの形状から判断できる。例えば、セルの位置座標情報がなくても、パターンの繰返し性を評価すれば、欠陥がマット内に生じたのかそれ以外かの区別ができる。ここでは、特に欠陥画像とこれに対応する正常画像の両方を検査中同時にメモリに格納できるので、解析がより有効に行える。
【００６４】
さらに、第１および第２の比較回路１８ａ、１８ｂにおける比較パラメータの設定並びにＣＰＵ１９において解析する際の解析パラメータの決定などの条件出しにも活用できる。即ち第１および第２の比較回路１８ａ、１８ｂにおいて統計画像における濃淡平均値画像１０ａ、１０ｂと濃淡検出画像１１ａ、１１ｂとの比較によって差画像（絶対値）を得、この得られた差画像に対して統計画像の濃淡標準偏差または濃淡最大値と濃淡最小値との差に応じて設定された欠陥または欠陥候補の抽出マージン（比較パラメータ）に基づいて欠陥または欠陥候補を抽出し、ＣＰＵ１９はこの抽出された結果に基づいて上記欠陥または欠陥候補の抽出マージン（比較パラメータ）が適正であるか否かを判定し、適正でない場合には入力手段１２等を用いて上記欠陥または欠陥候補の抽出マージン（比較パラメータ）を修正することによってウェーハに対する適正な欠陥または欠陥候補の抽出マージン（比較パラメータ）を得る。
この手法は、特に光学系の条件設定にもこれは有効である。光学系の照明条件であるσ値や拡散の度合い、照明波長、倍率などを変更し、これらの変更に応じて得られる第１及び第２の統計情報生成回路１７ａ、１７ｂから得られる統計画像の変化または第１及び第２の比較回路１８ａ、１８ｂから統計画像と検出画像との比較により得られる差画像に対して設定されたマージン（比較パラメータ）に基づいて得られる欠陥または欠陥候補の抽出結果を、ＣＰＵ１９において評価解析することにより、最適な光学系条件を設定することができる。
【００６５】
ウェーハ４上のパターンの光学画像を検出する光学系の具体的な一実施の形態を図２１（平面図）、図２２（正面図）、図２３に示す。これらの図において、対物レンズ２０９（６）として無限遠補正系のものを用い、長焦点距離（例えばｆ＝２００ｍｍ）の第２対物レンズ（チューブレンズともいう）３０３を合わせて用いる。イメージセンサ１に対応する輪帯状の照明（明視野照明）用ニリアイメージセンサ２１２ａ及び暗視野照明用リニアイメージセンサ３０８は、ＴＤＩ（Time Delay Integration）時間遅延積分型イメージセンサで構成する。本構成において、対物レンズ２０９と第２対物レンズ３０３との間に、偏光ビームスプリッタＰＢＳ（Polarization Beam Spritter）２０８ａとλ／４板（１／４波長板）２５１とを設置してある。対物レンズ２０９と第２対物レンズ３０３の間は平行光であるため、これらの素子の挿入は収差の劣化を招かない。偏光ビームスプリッタＰＢＳ２０８ａとλ／４板（１／４波長板）２５１の効用は、図２３に示す通りであり、円偏光または楕円偏光３３４が、対物レンズ２０９を介してウエーハ４に照射される。ウエーハ４からの反射光は、λ／４板に達し、Ｐ偏光３３３になり、ＰＢＳ２０８ａをそのまま透過し、イメージセンサ２１２ａに達する。図２１において、輪帯状照明用フィルタ２０５は、照明の輪帯の度合いを設定するものである。またＮＤフィルタ２１４により照明光の強度を設定し、色フィルタ、或いは拡散板３１６により照明波長や拡散性を設定している。またこの構成例では照明波長の切り替えのために、ランプ自体を２種類変更できる。ズームレンズ２１３は、光学倍率を設定する。このような構成において、光学系の照明条件であるσ値や拡散の度合い、照明波長、倍率などを上記した画像記憶と解析により、最適な条件を設定できる。
後述する電子線を用いた装置の場合は、電子線のビーム径や加速電圧などを最適化できる。
【００６６】
またこれらと別に、図１９に示すように画像ファイリングシステムとしても活用できる。特に、ＣＰＵ１９は、検査中に第１およ第２の比較回路１７ａ、１７ｂの特徴量抽出部１３９から欠陥メモリ１４１に所望の欠陥画像が得られるので、記憶装置１４７（１３）への欠陥画像のファイリングも実時間で実施できる。即ち、ＣＰＵ１９は、例えば切出し回路２５で切り出された欠陥部の検出画像（ｆ（ｉ，ｊ）、ｆ'（ｉ，ｊ））１１ａ、１１ｂや統計画像（ｇ（ｉ，ｊ）、ｇ'（ｉ，ｊ））１０ａ、１０ｂなど種々の画像を一次格納するメモリ１２３を介して記憶装置１４７（１３）のデータベース上にファイリングできるため、ＬＳＩの電気的不良が発生したときに、当該画像データを検索、確認し、不良事象との対応をとることにより、不良要因の解析、分析などの不良解析や歩留まり向上支援システムとして有用である。電気的不良との対応がとれた画像データの分類を行い、これと新たに発生した外観不良との照合により、外観不良が電気的な不良の要因となるかどうかが即座にわかる。従って、欠陥発生と同時に不良対策を実施でき、歩留まり向上に効果がある。画像データには、欠陥の寸法や座標などの情報も付加しておくと、検索に便利である。また欠陥検出後に個々の欠陥をレビューし、欠陥の形態や発生原因をオペレータが入力し、この入力されたカテゴリーデータを画像データに付加しても良い。
【００６７】
またＣＰＵ１９において、切り出し回路２５を切出し信号（欠陥または欠陥候補の信号）２４により駆動することによって、図２０に示すように切出し信号（欠陥または欠陥候補の信号）２４として指定した寸法範囲内の欠陥や指定した位置範囲内の欠陥としてユーザが指示することにより、所望の欠陥の画像を格納することができる。具体的には欠陥または欠陥候補の抽出に用いた２枚の画像のいずれかまたは両方を欠陥または欠陥候補の抽出と同時に一部をメモリ１２３に記憶する際、第１およ第２の比較回路１８ａ、１８ｂの特徴量抽出部１３９から得られる欠陥または欠陥候補の有無信号１４３、或いは欠陥または欠陥候補の特徴量の一つである座標信号１４４、或いは欠陥または欠陥候補の特徴量の一つである寸法信号１４５、或いは欠陥または欠陥候補の特徴量の一つである面積１４６など、或いはいずれかの組合せを欠陥信号の判定ロジック１４２において論理的な組み合わせを行い、必要な信号に基づき画像を記憶することを制御する。これらの信号は、検出画像信号と同期していることは言うまでもない。
【００６８】
以上説明した画像ファイリングシステムは、外部へデータを送信する機能をもっており、外部データベースへのデータ転送も可能とすれば、より大きなライン全体の全体解析システムのデータベースへのデータ格納も可能となる。
次に、第１およ第２の比較回路１８ａ、１８ｂの位置合わせ回路４６ａ、４６ｂにおいて行う高精度な位置ずれ量の算出と位置合わせについて図８および図９を参照して説明する。図８は本発明の一実施形態に係る被検査パターンの画像位置合わせ方法の略示説明図、図９は図８の画像位置合わせ方法の二つの画像のサンプリング位置関係略示説明図である。前記位置ずれ量の検出は下記のものが考えられる。
（ａ）線形補間方式（濃淡の差を最小にする方式）
（ｂ）二次関数補間方式（微分値の差を最小にする方式）
（ｃ）正則化補間方式（微分値の差を小さくなる拘束条件付きの濃淡の差最小方式）
方式（ａ）は、対象である二枚の画像の濃淡の二乗誤差を最小にして一致させるものである。方式（ｂ）は、微分画像に対して線形補間の適用を狙ったものである。また、方式（ｃ）は、方式（ｂ）を拘束条件として方式（ａ）を満たすもので、微分値の差の二乗和に対し、正則化パラメータγを重みとして与えている。前記パラメータγ＝０のときは、方式（ａ）と同じ結果を与える。いずれの方式も、繰返し演算などが不要であり、一回で実現可能なものである。
【００６９】
上記（ａ）線形補間方式を説明する。
画像のアライアメントは、図８に示すようにピクセルアライアメント及びサブピクセルアライメントにより、統計画像と基準画像とを用いて行なわれる。
前記ピクセルアライアメントは、比較する二枚の画像（例えば検出画像ｆi,jと統計画像ｇi,j）の一方を画素の単位でずらしながら濃淡差（基準画像の各画素の値と統計画像の対応画素の値の差）を演算し、濃淡差が最小となる位置ずれ量を求めるものである。画像の位置ずれ検出の範囲は、例えば最大±３画素とし、またパターンの設計ルールに応じて可変とする。得られた位置ずれ量だけ片方の画像位置をずらせることにより、二枚の画像の位置合わせを行なうものである。
【００７０】
まず、ピクセルアライアメントを説明する。
図８の（Ａ）枠内に記載されている下記（数５）式を用いて説明する。
【００７１】
【数５】

【００７２】
ピクセルアライメント用位置ずれ検出８１は、上記（数５）式のＳ（Δｘ、Δｙ）をｍｉｎとするΔｘ、Δｙを検出するものである。
ただし、最小となる位置は画素単位でしか求められないため、真の位置が求めたΔｘ、Δｙのどちらの近くにあるかにより、オフセットとして加える。
【００７３】
下記の式に基づき、Δｘ、Δｙに１を加えたりもしくは、そのままにする。
すなわち、
Ｓ（１、０）＋Ｓ（１、−１）＋Ｓ（０、−１）が最小ならば、Δｘ＋＋、
Ｓ（−１、０）＋Ｓ（−１、−１）＋Ｓ（０、−１）が最小ならばそのまま、
Ｓ（−１、０）＋Ｓ（−１、１）＋Ｓ（０、１）が最小ならば、Δｙ＋＋、
Ｓ（１、０）＋Ｓ（１、１）＋Ｓ（０、１）が最小ならば、Δｘ＋＋、Δｙ＋＋、
なお、Δｘ＋＋は、Δｘ＝Δｘ＋１の意である。
このように遅延メモリ８２および８３の各々で遅延された二つの画像に対して位置合わせ、ピクセルアライメント８４により、検出画像ｆをつねに得られた位置ずれ量だけ片方の画像の位置をずらせることにより、二枚の画像の位置合わせが行なわれる。すなわち、検出画像ｆを常に右上移動して、新たな画像ｆ′を求めることになり、移動方向を４種類(右下移動、左上移動、左下移動、右上移動）から１種類に特定することができる。これはハードウエアの簡単化につながるものである。
【００７４】
前記サブピクセルアライメントは、画素より小さい単位の位置ずれ量を求め、二枚の画像を高精度に位置合わせするものである。前記画素単位アライアメント８４及び当該サブピクセルアライメント８８は、いずれも例えば２５６ライン毎に一括して行なわれている。
サブピクセルアライメントは、位置ずれ検出部８５と遅延メモリ８６および８７と位置合わせ部８８とから構成される。
【００７５】
まず、前記位置ずれ検出部８５を図８の（Ｂ）枠を用いて説明する。
前記位置ずれ検出部８５は、線形補間に基づき画像ｆ′、ｇ′を求める。ただし、位置ずれ量α、βはｆ′、ｇ′との差の二乗誤差が最も小さくなるものを位置ずれ量として検出している。すなわち、位置ずれ検出の規範は、二つの補間画像の濃淡を一致させることである。
つぎに、位置合わせ部８８では、図８の（Ｃ）枠を用いて説明する。この位置ずれ量α、βに基づくＳと、統計画像ｆ、基準画像ｇとのとのコンボリューション（畳み込み和）により、画像を補間して新たな画像ｆ′、ｇ′を得ている。図示〇内に×が有る記号はコンボリューションを表すものである。
このようにして元の画像ｆと新たな画像ｆ′とのサンプリング位置との関係が図９に示されている。サンプリング位置の違いが位置ずれ量α、βに相当している。
【００７６】
上記方式の特徴は、位置合わせすべき二枚の画像の濃淡が、二乗の誤差最小の意味でよく一致するように位置ずれ量α、βを求めるのであって、必ずしも画像の位置ずれ量の真値を求めているのではない。しかし、位置合わせ後の比較において、正常部の濃淡の違いを小さくでき、比較検査においては都合のよい方式であると考えられる。
また、位置ずれ量α、βの算出は、繰返し演算することなく解析的に行うことができ、ハードウエア化するのに適しているという特長がある。
【００７７】
次に、方式（ｂ）の二次関数補間方式について説明する。
本方式は、微分画像に対して線形補間の適用を目的とするものである。
まず、下記（数６）式、（数７）式の微分型の補間式を仮定する。
【００７８】
【数６】

【００７９】
【数７】

【００８０】
上記（数６）式、（数７）式で示される微分型の補間式のとる値が、（数８）式で示されるＳが最小となるように、位置ずれ量α、βを求める。
【００８１】
【数８】

【００８２】
上式において、下記（数９）式、（数１０）式、（数１１）式に示すＣ₁、Ｃ₂、Ｃ₃を定める。
【００８３】
【数９】

【００８４】
【数１０】

【００８５】
【数１１】

【００８６】
上記（数９）式、（数１０）式、（数１１）式のＣ₁、Ｃ₂、Ｃ₃を用いると、（数１２）式、（数１３）式で示される位置ずれ量α、βがえられる。
【００８７】
【数１２】

【００８８】
【数１３】

【００８９】
次に、方式（Ｃ）の正則化補間方式について説明する。
下記（数１４）式で示されるＳ、すなわち微分値の差が最小となるという拘束条件付きで、濃淡の差を最小にする位置ずれ量α、βを求める。
【００９０】
【数１４】

【００９１】
下記（数１５）式、（数１６）式、（数１７）式、（数１８）式、（数１９）式、（数２０）式で示されるＣ₁、Ｃ₂、Ｃ₃、Ｃ₄、Ｃ₅、Ｃ₆を定める。
【００９２】
【数１５】

【００９３】
【数１６】

【００９４】
【数１７】

【００９５】
【数１８】

【００９６】
【数１９】

【００９７】
【数２０】

【００９８】
このＣ₁、Ｃ₂、Ｃ₃、Ｃ₄、Ｃ₅、Ｃ₆を用い、正則化パラメータをγとすると、上記（数１４）式は下記（数２１）式で表される。
【００９９】
【数２１】

【０１００】
この（数２１）式より下記（数２２）式、（数２３）式で示されるα、βが得られる。
【０１０１】
【数２２】

【０１０２】
【数２３】

【０１０３】
なお、上式において、正則化パラメータγを０とすると、従来の線形補間と一致する。
【０１０４】
また、サブピクセルアライメントの位置合わせの方式には、下記の方式が考えられる。
（ａ）′線形補間方式（濃淡の差を最小にする方式）
（ｂ）′共一次内挿方式
（ｃ）′二次関数補間方式
（ｄ）′三次たたみ込み方式（スプライン補間）方式
（ａ）′線形補間方式による（数２４Ａ）式で表される新たな画像ｆ′ijは、位置ずれ量α、βに基ずく下記の（数２４Ｂ）式で表されるＳijと元の画像ｆijとのコンボリューションにより得ることができる。
【０１０５】
【数２４】

【０１０６】
同様にして、（数２５Ａ）式で表される新たな画像ｇ′i+△x、j+△yは、位置ずれ量α、βに基ずく下記の（数２５Ｂ）式で表されるＳ′ijと元の画像ｇi+△x、j+△yとのコンボリューションにより得ることができる。
【０１０７】
【数２５】

【０１０８】
また、（ｂ）′共一次内挿方式による（数２６Ａ）式で表される新たな画像ｆ′ijは、位置ずれ量α、βに基ずく下記の（数２６Ｂ）式で表されるＳijと元の画像ｆijとのコンボリューションにより得ることができる。
【０１０９】
【数２６】

【０１１０】
同様にして、（数２７Ａ）式で表される新たな画像ｇ′i+△x、j+△yは、位置ずれ量α、βに基ずく下記の（数２７Ｂ）式で表されるＳ′ijと元の画像ｇi+△x、j+△yとのコンボリューションにより得ることができる。
【０１１１】
【数２７】

【０１１２】
（ｃ）′二次関数補間方式は下記の（数２８）式、（数２９）式の補間式を微分して得られる。
【０１１３】
【数２８】

【０１１４】
【数２９】

【０１１５】
上式を４×４のコンボルーションで表現すると、下記の（数３０）式、（数３１）式で表される。
【０１１６】
【数３０】

【０１１７】
【数３１】

【０１１８】
（ｄ）′三次たたみ込み方式（スプライン補間）方式は、新たな画像ｆ′ijは下記の（数３２Ａ）式で表され、位置ずれ量α、βに（数３２Ｂ）式で表されるＳijと元の画像ｆijとのコンボリューションにより得られる。
【０１１９】
【数３２】

【０１２０】
（数３２Ｂ）式において、ｈ（ｔ）＝ｓｉｎ（πｔ）／πｔとおき、近似式で展開すると、ｈ（ｔ）は下記の（数３３）式で表される。
【０１２１】
【数３３】

【０１２２】
また、（数３２Ｂ）式において、ｘ₁＝１＋α、ｘ₂＝α、ｘ₃＝１−α、ｘ₄＝２−α、ｙ₁＝１＋β、ｙ₂＝β、ｙ₃＝１−β、ｙ₄＝２−βである。
同様にして、（数３４Ａ）式で表される新たな画像ｇ′i+△x、j+△yは、位置ずれ量α、βに基ずく下記の（数３４Ｂ）式で表されるＳ′ijと元の画像ｇi+△x、j+△yとのコンボリューションにより得ることができる。
【０１２３】
【数３４】

【０１２４】
上式において、ｘ₁＝１＋（１−α）、ｘ₂＝（1−α）、ｘ₃＝１−（1−α）、ｘ₄＝２−（1−α）、ｙ₁＝１＋（１−β）、ｙ₂＝１−β、ｙ₃＝１−（１−β）、ｙ₄＝２−（１−β）である。
これらの方式の中で、（ｄ）′三次たたみ込み方式（スプライン補間）方式は、平滑効果か最も小さく、方向性がないと考えられるものである。ここでは、いずれの方式も併用できるように、４×４画素の畳み込み（コンボルーション）により実現する。（数３５）式、（数３６）式においてコンボルーションのウエイトの例を示すものである。
【０１２５】
【数３５】

【０１２６】
【数３６】

【０１２７】
ただし、これらの位置合わせは、チップ比較において特に必要となるもので、セル比較においては固定量のずれ補正でも構わない。
【０１２８】
いずれにせよ、画像の位置合わせにおいて、位置ずれ検出は、画像を線形補間、あるいは微分画像を線形補間し、この補間画像間のそれぞれの不一致量、あるいは不一致量の線形結合が最小になるように、画像のずれ量を画素未満の分解能で求め、位置合わせはこの検出した位置ずれ量に基づき、画像を線形補間、あるいは畳み込み補間することにより、得ることができる。これにより、きわめて高精度に画像を位置合わせすることができ、本発明で意図した目的がより高感度に実現できることになる。
また、上記実施の形態は、画像の位置ずれ検出と位置合わせとからなる１或いは複数の画像の位置合わせ方法において、位置ずれ検出を、各画像を線形補間もしくは各画像の微分画像を線形補間し、これらの補間画像間のそれぞれの不一致量もしくは当該不一致量の線形結合が最小になるように当該画像を用いたずれ量算出用データを布線論理で求め、ずれ量算出用データから算出すべきずれ量を画素未満単位の分解能でプログラム論理により求め、前記位置合わせを、当該位置ずれ量に基づき前記各画像を線形補間もしくは２次補間もしくは畳み込み補間することを布線論理により行なうこともできる。これは、例えば（数８）式において、ΣＣ２Ｃ３なる統計量をハードウェア、即ち布線論理で求める。こののち、α等をプログラム論理により求める。このとき、α等を求める際、エラー処理などを柔軟に行うことができる。
【０１２９】
また、位置ずれ検出を、各画像を線形補間もしくは各画像の微分画像を線形補間し、これらの補間画像間のそれぞれの不一致量もしくは当該不一致量の線形結合が最小になるように当該画像を用いたずれ量算出用データを布線論理で求め、ずれ量算出用データから算出すべきずれ量を画素未満単位の分解能でプログラム論理により求め、前記位置合わせを、当該位置ずれ量に基づき、実施例のように畳み込み演算により布線論理により行なうこともできる。上記した実施例では、画像の位置合わせは（数２４Ａ）式、（数２６Ａ）式、（数３２Ａ）式に例を示すように、すべて畳み込み演算により実現できている。
また、これらを応用して、画像ごとの歪みを表示することにより、ステージの走行状態や電子線を走査する場合には、その走査状態などの装置状態をモニターすることもできる。
上記実施の形態においては、第１の統計画像生成回路１７ａ及び第２の統計画像生成回路１７ｂから８ビット構成で出力する場合について説明したが、１０ビット構成で出力しても差し支えない。
【０１３０】
また、画像を連続的に検出し、比較する方式において、一方の画像は連続したものが得られるが、もう一方の画像は細分化した領域毎（例えば２５６×２５６画素）に行うピクセルアライメント時に不連続になることがある。図１６にその原因の一例を示す。パターンの密度が小さく、パターン情報不足のため、位置ずれ量の検出が不正確になる場合や、光学系の振動、或いはステージ系の振動、電子線の場合は帯電など、種々の原因で画像歪みが生じて、画像が不連続になる。不連続になると、これに続くサブピクセルアライメント、画素補間及び微分等の画像処理により、細分化した領域の画像の境界が不定値になる。このため、比較において不一致が生じ、誤検出が発生する。画像が連続ならば、微分等を施しても不一致は生じない。また、ピクセルアライメント後に従来の画素単位の比較のみを行うのならば、不一致は生じない。
また、細分化した領域より大きな範囲で、画素補間や微分などを実施し、細分化した領域内では正常な値同士を比較する手法も考えられるが、これは回路規模の増大を招く。
【０１３１】
これを解決するため、
１）画像が不連続かどうか検出する
２）不連続ならば、境界の前後（境界部）で感度を落とす
３）或いは不連続ならば、境界の前後は非検査領域とする
４）或いは常時、境界の前後で感度を落とす
５）或いは常時、境界の前後は非検査領域とする
６）感度低下は２枚の画像の差を２値化した２値画像の縮小（シュリンク）処理を行う
７）或いは感度低下は濃淡差の２値化しきい値を大きくすることにより行う
などを採用する。
【０１３２】
上記１）は、ピクセルアライメント用位置ずれ検出量のΔｘ，Δｙ（（数５）式のＳ（Δｘ，Δｙ）をｍｉｎとするΔｘ，Δｙ）が各画素間で同一値になるかどうかをチェックするものである。更に、下記オフセットが同一値かどうかチェックするものである。
下記の式に基づき、Δｘ、Δｙに１を加えたりもしくは、そのままにする。
すなわち、
Ｓ（１、０）＋Ｓ（１、−１）＋Ｓ（０、−１）が最小ならば、Δｘ＋＋、
Ｓ（−１、０）＋Ｓ（−１、−１）＋Ｓ（０、−１）が最小ならばそのまま、
Ｓ（−１、０）＋Ｓ（−１、１）＋Ｓ（０、１）が最小ならば、Δｙ＋＋、
Ｓ（１、０）＋Ｓ（１、１）＋Ｓ（０、１）が最小ならば、Δｘ＋＋、Δｙ＋＋、
なお、Δｘ＋＋は、Δｘ＝Δｘ＋１の意である。
実際には、Δｘ，Δｙそれぞれにｘ，ｙのオフセットを加えた後の値が、画像間で同一かどうかチェックする。
【０１３３】
次に、位置合わせされた画像に対し、画素より小さい単位の位置ずれ量を求め、二枚の画像を高精度に位置合わせする前述したサブピクセルアライメントが実施される。画像が不連続の場合、画像の境界の画素の値が不確定になり、その後の処理に悪い影響を与える。例えば、サブピクセルアライメント後に微分を行い、微分値を比較する場合、微分値は境界の画素で異常な値を有することになる。サブピクセルアライメント後に境界１画素が不確定だったものが、１次微分後は境界２画素で不確定になるほど、欠陥検出に悪影響がある。Ｓｏｂｅｌなど各種フィルタでは、いずれも境界が不確定になる。そのため、後に続く処理に応じて異常な境界部を決め、この境界部で発生する誤検出を防止する。これには、上記２）〜７）を実施する。
勿論、微分処理などは位置合わせの前に実施し、欠陥判定も対応画素の比較のみならば、画像が不連続であっても、境界での誤検出はない。しかし、通常は位置合わせ後に各種の処理を実行することが回路規模の点で多く、境界の処理が必要である。
上記より、画像の境界は必要最小限にすることが必要である。これは、１枚の画像のもつ歪みを許容できる範囲で画像を大きくとることにより、また位置合わせ時にデータ量が膨大にならないように決められる。
【０１３４】
また、電子ビームを用いて検出した画像について、複数画像の位置合わせを着目画像のみならず過去の複数画像も直接、或いはこれらの位置ずれ情報を用いて行うことが可能である。これを図１５に示す。図１５において、２７は遅延メモリ、２８は微分回路によって構成されるエッジ位置抽出回路、２９は２値化回路、３０は不一致検出回路、３１は遅延回路、３２は位置合わせ回路、３３は欠陥判定回路、３４は状態記憶回路、３５は位置合わせ、感度制御回路をそれぞれ示す。状態検出回路は着目画像より時間的に前の画像の位置合わせの状態、即ち画像間の不一致画素数や位置ずれ量などの状態を記憶するもので、着目画像の位置あわせの時に、これらの情報を加味して位置合わせするものである。これにより、着目画像にパターン情報がなく、位置合わせ精度が不足すると考えられるときに位置合わせ精度を確保することができる。この実施の形態では、エッジ位置抽出回路２８と２値化回路２９とを用いてパターンのエッジ位置を２値化画像信号で示す場合であるが、鎖線で示すようにＡ／Ｄ変換器２から直接得られるデジタル濃淡画像信号をそのまま使用してもよいことは言うまでもない。
【０１３５】
図１７に、境界処理の一実施の形態を示す。同図において、（ａ）は画像（ここでは連続した２枚の差画像）、（ｂ）は境界信号（境界の前後３画素）、（ｃ）および（ｄ）は縮小フィルタの種類（２種類）と適用のタイミングを示している。縮小フィルタＡは、境界部以外の領域を対象に差画像の２値化画像に対して、このサイズ以上の不一致を出力するものである。具体的には、２値化画像に対しこれら２×２画素のＡＮＤを求めるものである。同様に縮小フィルタＢは、境界部の領域を対象に差画像の２値化画像に対して、このサイズ以上の不一致を出力するものである。ここでは、縮小フィルタＢを縮小フィルタＡよりサイズを大きくすることで、境界部の感度を低下させている。勿論、画像が不連続でない場合は、縮小フィルタＢは、縮小フィルタＡと同じものでよいし、何れもなくすことも可能である。図１７に示した処理は、欠陥判定回路３３（ＣＰＵ４８）の内部で行われる。
【０１３６】
図１８に欠陥判定回路３３の一実施の形態を示す。同図において、位置合わせされた画像の差を検出し、２値化後、フィルタを通し、最後に不一致の特徴（座標、寸法、面積など）を算出する。１３６は差検出回路、１３７は２値化回路、１３８はフィルタＡ及びフィルタＢの何れかが実行可能であるフィルタ回路、１３９は特徴量抽出（不一致座標、寸法、面積など）回路である。更に特徴量抽出回路１３９で抽出された特徴量に対して判定基準である比較パラメータに基づいて判定する欠陥または欠陥候補の判定回路を有することになる。
ここで、２値化の閾値Ｖｔｈは、設定した値でもよいが、位置合わせ、境界部感度制御回路３５により制御しても良い。即ち上記したように、感度低下を濃淡差の２値化閾値を境界信号に同期して境界部で大きくすることにより行っても良い。１３８に入力されている位置合わせ、境界部感度制御回路３５からの信号は、フィルタの選択信号である。
【０１３７】
さらには、本構成によれば、境界信号に同期して、境界部において閾値を例えば２５５とし（８ビット階調の場合の最大値）、不一致が完全に出力されるようにして、境界部を非検査領域とすることもできる。
なお、ここでは、イメージセンサの両端にあたる画像の両端でも、画像の値が不確定になるが、これは従来通り画像の両端をマスク、或いは使用しないことにより、誤検出を防止することができる。
【０１３８】
［実施の形態 ２］
また、上記図１に示す［発明の実施の形態 １］においては、被検査パターンの欠陥検査画像処理装置を、すなわち、Ａ／Ｄ変換器２からＣＰＵ１９までの各機器を、ステージ５、対物レンズ６、照明光源７、ハーフミラー８、イメージセンサ１からなる光学顕微鏡系から構成される装置に適用した場合について説明したが、走査型電子顕微鏡系に適用することもできることはいうまでもない。
ただし、本発明に係る被検査パターンの欠陥検査画像処理装置、すなわち、図１に示すＡ／Ｄ変換器２からＣＰＵ１９までを、走査型電子顕微鏡系に適用した場合、イメージセンサ１の代わりに、シンチレータ等のディテクタで構成されることになる。
【０１３９】
図１０を参照して走査型電子顕微鏡に適用した場合を説明する。図１０は、本発明の他の一実施形態に係る被検査パターンの欠陥検査装置の略示説明図である。図１０は、被検査パターンの欠陥検査画像処理装置に走査型電子顕微鏡を用いた場合の電子光学系の略示説明図である。
図１０において、１０１は電子線を発射する電子源、１０２は電子源から放出された電子線、１０３、１０４は電子線を集束する対物レンズを構成する電極、１０５は電子線を偏向させる偏向器、１０６は被検査パターンを有するウェーハ、１０８はウェーハからでる二次電子、１０９は二次電子検出器、１１０は装置構成各機器を制御する表示・制御機器である。
図１０に示す如く、電子源１０１から放出された電子線１０２は、２つの電極１０３、１０４からなる対物レンズによって試料であるウェーハ１０６上に集束される。この対物レンズを構成する２つの電極１０３、１０４のうち、電子源１０１側に位置する第１の電極１０３の電圧をウェーハ１０６側に位置するアース電位にある第２の電極１０４に対して正側の電圧とし、この電圧を調整して、第１の電極１０３と第２の電極１０４との間の電界を調節することで、対物レンズのレンズ作用が調節される。これにより、対物レンズのレンズ主面が第２の電極１０４の下側に形成される。
【０１４０】
さらに、前記電子線１０２は、第１の電極１０３に囲繞されることによって、第１の電極１０３と同電位に保たれている空間内において、静電型または磁界型の偏向器１０５により偏向され、ウェーハ１０６上で２次元的に走査される。
【０１４１】
前記電子線１０２の照射によってウェーハ１０６から発生した２次電子または反射電子は、電子線１０２の対称の位置で、チルト軸に垂直な面内に配置された２組の２次電子検出器または反射電子検出器１０８によって検出され、この検出信号を映像信号として表示制御装置１１０内の表示部においてウェーハ１０６の画像が得られる。
上記構成は、本発明者らによる特開平４−５１４４１号公報記載の荷電粒子線観察装置と同一の構成である。
ここで、静電型の対物レンズとした場合には、磁界型レンズの場合のように励磁コイルを巻く必要がないため、レンズ自体を小型化できる。たとえば、従来の磁界型レンズの大きさが直径１００〜１５０ｍｍであるのに対し、静電型対物レンズでは直径１０ｍｍ以下にすることもできる。
しかし、このように走査型電子顕微鏡に本発明へ適用した場合は、画像検出過程において画像歪みなどが生じやすいという問題に対応する必要がある。
従って、メモリマット部２１のような小さな繰返しパターンの集合を対象にした場合でも、画像の位置合わせを確実に行うことが重要である。
【０１４２】
そこで、図１０に示すように、新たに反射電子検出器１１１、ここではアニュラー型のものを備え、反射電子と２次電子を分離検出し、反射電子により検出した画像を用いて複数画像の位置合わせを行うことができる。ここで反射電子による画像では、１次電子によるパターンのチャージアップなどの影響を受けがたく、あたかも光と同じように扱って得た画像といえる。反射電子検出器は、アニュラー型のものが対称性がよく、各種パターンの検査には適している訳であるが、勿論どのような形状のものでも差し支えない。
また、電子ビームを用いて画像を連続的に検出する際、マット部の複数の繰返しパターンについては電子ビームのスキャン方向の繰返しパターンの画像を用いることにすれば、より画像歪みは低減できるものである。
また、図１に示す実施の形態と図１０に示す電子線検出器を組み合わせて、光を用いて検出した画像により欠陥検出、ここでは欠陥座標の算出を行い、電子ビームを用いて検出した画像より欠陥部を含む周辺の画像を用いて、欠陥の有無以外の欠陥の特徴量（例えば欠陥の寸法や欠陥の背景に対する明るさなど）に基づく欠陥の詳細情報を得ることも可能であり、これは高精度検査に有益である。
【０１４３】
なお、上記発明の実施の形態では、統計画像を求める際に、画像ヒストグラムの変換等による階調変換を行っていないが、ヒストグラムイコライゼイション等を前処理として実施しても差し支えない。これは、電子ビームによるチャージアップ等の対策に有効である。
【０１４４】
上記発明の実施の形態によれば、場所によるパターンの明るさの違いに影響されることなく、欠陥を高感度に検出することができる。したがって、メモリマット部２１など暗い領域も高感度に検査をすることができ、さらにその内部の明るさがばらつきの大きいパターンにおいても高感度に検査できる。
また、周辺回路部２２なども最適な検査をすることができる。しかも、画像の濃淡差を検出するだけでなく、画像のもつ各種情報をきわめて的確な形で比較でき、有効である。従って、従来に比べ、信頼性の高い検査を実現することができる。
また、画像に歪みがあっても高精度に画像の位置合わせができるし、パターン密度が低いときにも同様の効果が期待できる。
以上、本発明に係る実施の形態について、主に光学顕微鏡や走査型電子顕微鏡を用いた画像検出に基づく画像の統計画像の生成、比較検査方法について述べたが、他の赤外線やＸ線により得られた画像検出に用いた場合にも、同様に有効であることはいうまでもない。
【０１４５】
［実施の形態 ３］
次に、図１１を参照して、本発明の半導体の製造プロセスにおける欠陥発生原因を解析への応用を説明する。図１１は、本発明に係る画像処理装置の半導体製造プロセスへ適用図である。
本実施の形態は、第１の比較回路１８ａと第２の比較回路１８ｂからの比較結果およびＣＰＵ１９から出力される特徴量情報５１や欠陥（異物も含まれる）の情報５７ａや統計情報に基づくパターンの出来具合の情報５７ｂを入力して、半導体の製造プロセスにおける欠陥発生原因を解析し、この解析された欠陥発生原因を取り除くことによって、良品の半導体チップを高歩留まりで生産することについて説明する。
図１１において、３８０は半導体の製造ライン、３８１は半導体ウェーハ４ａの搬送経路、３８２は半導体製造工程の内、絶縁膜を形成するＣＶＤ成膜工程を実行するＣＶＤ装置、３８３は半導体製造工程の内、配線膜を形成するスパッタリング工程を実行するスパッタリング装置、３８４は半導体製造工程の内、レジスト塗布、露光、現像等を行う露光工程を実行する露光装置、３８５は半導体製造工程の内、パターニングをするエッチング工程を実行するエッチング装置であり、このように半導体ウェーハは様々な製造工程を経て製造される。
【０１４６】
また、３９１は比較回路１８およびＣＰＵ１９から得られる特徴量情報５１や欠陥の情報５７ａや統計情報に基づくパターンの出来具合の情報５７ｂを入力するインターフェース、３９２は解析等の処理を実行するＣＰＵ、３９３は解析等のプログラムを格納したメモリ、３９４、３９５、３９６、３９７は制御回路、３９８は欠陥発生原因等の解析結果を出力する印刷装置等の出力装置、３９９は各種データを表示する表示装置、４００はデータを各装置間に移送するバスライン、４０１はキーボード、ディスク等からなる入力装置、４０２は、図示しないが検査画像処理装置からは得られない欠陥を発生させた欠陥発生原因又は欠陥発生要因との因果関係の履歴データまたはデータベースを記憶させる外部記憶装置、４０３は、情報４１０を製造ラインへ提供するインターフェース、４１０は解析された欠陥発生原因または欠陥発生要因に関する情報および製造プロセス条件を制御するための情報である。
また、３９０は、比較器１８ａ、１８ｂおよびＣＰＵ１９（図１を参照）に示される装置から出力される特徴量情報５１や欠陥（異物も含まれる）の情報５７ａや統計情報に基づくパターンの出来具合の情報５７ｂを入力して、製造ライン３８０における欠陥発生原因または欠陥発生要因および製造プロセス条件を制御するための制御情報を解析する解析用コンピュータである。
前記製造ライン３８０は、半導体を製造する各プロセス装置３８２、３８３、３８４、３８５とからなっている。
【０１４７】
解析用コンピュータ３９０は、図示しない比較器１８ａ、１８ｂおよびＣＰＵ１９から出力される特徴量情報５１や欠陥の情報５７ａや統計情報に基づくパターンの出来具合の情報５７ｂを入力するインターフェース３９１と、解析等の処理を実行するＣＰＵ３９２と、解析プログラム等を格納したメモリ３９３と、制御回路３９４、３９５、３９６、３９７と、欠陥発生原因等の解析結果および製造プロセス条件を制御するために解析された制御情報を出力する印刷装置等の出力装置３９８と、各種データを表示する表示装置３９９と、製造ライン３８０に関するデータおよび前記製造ライン３８０に流される半導体ウェーハ４ａに関するデータ等を入力する入力装置４０１と、前記半導体ウェーハ４ａ上に発生した欠陥と欠陥発生原因または欠陥発生要因との因果関係の履歴データまたはデータベースおよびパターンの出来具合と製造プロセス条件との対応関係の履歴データまたはデータベースを記憶した外部記憶装置４０２と、前記ＣＰＵ３９２によって解析された欠陥発生原因または欠陥発生要因に関する情報および製造プロセス条件を制御するための情報４１０を前記製造ライン３８０へ提供するインターフェース４０３とおよびこれらを接続するバスライン４００で構成されている。
【０１４８】
したがって、解析用コンピュータ３９０におけるＣＰＵ３９２は、入力された特徴量情報５１や欠陥の情報５７ａや統計情報に基づくパターンの出来具合の情報５７ｂと、外部記憶装置４０２に記憶された半導体ウェーハ４ａ上に発生した欠陥と、各プロセス装置３８２、３８３、３８４、３８５からなる製造ライン３８０において欠陥を発生させた欠陥発生原因または欠陥発生要因との因果関係の履歴データまたはデータベースおよびパターンの出来具合と各プロセス装置３８２、３８３、３８４、３８５の製造プロセス条件との対応関係の履歴データまたはデータベースに基づいて、各プロセス装置３８２、３８３、３８４、３８５からなる製造ライン３８０における欠陥を発生させた欠陥発生原因または欠陥発生要因および製造プロセス条件を制御するための制御情報を解析し、この解析された欠陥発生原因または欠陥発生要因に関する情報および製造プロセス条件を制御するための情報４１０を各プロセス装置３８２、３８３、３８４、３８５へ提供する。
【０１４９】
この欠陥発生原因または欠陥発生要因に関する情報および製造プロセス条件を制御するための情報４１０が提供された各プロセス装置３８２、３８３、３８４、３８５は、洗浄も含めて各種プロセス条件を制御して欠陥発生原因または欠陥発生要因を取り除くことによって良品の半導体ウェーハ４ａを、次の工場へ送り出すことができる。その結果、半導体を高歩留まりで製造することができる。なお、欠陥検査が行われる半導体ウェーハ４ａは、上記製造ライン３８０において、欠陥を発生しやすい個所の前後工程から、半導体ウェーハ４ａ単位、またはロット単位でサンプリングされる。
また、解析用コンピュータ３９０におけるＣＰＵ３９２は、図示しない例えば専用の異物検査装置（図１及び図７で示す被検査パターン検査装置でも異物についても欠陥として検出することも可能である。）で検出された異物信号に基づいてＣＰＵ１９から得られて入力された異物情報と、外部記憶装置４０２に記憶された半導体ウェーハ１ａ上に発生した異物と各プロセス装置３８２、３８３、３８４、３８５からなる製造ライン３８０において異物を発生させた異物発生原因または異物発生要因との因果関係の履歴データまたはデータベースとに基づいて、前記各プロセス装置３８２、３８３、３８４、３８５からなる製造ライン３８０における異物を発生させた異物発生原因または異物発生要因を解析する。
【０１５０】
前記解析された異物発生原因または異物発生要因に関する情報４１０を前記製造ライン３８０の各プロセス装置３８２、３８３、３８４、３８５へ提供する。この異物発生原因または異物発生要因に関する情報４１０が提供された各プロセス装置３８２、３８３、３８４、３８５は、洗浄も含めて各種プロセス条件を制御して異物発生原因または異物発生要因を取り除くことによって欠陥のない良品の半導体ウェーハ４ａを次工程へ送り出すことができ、その結果半導体を高歩留まりで製造することができる。
【０１５１】
【発明の効果】
本発明によれば、面荒れ、グレイン等が生じる多層の被検査パターンの表面の状態に影響されることなく被検査パターンを高感度で、且つ高信頼度で検査することができる効果を奏する。
また本発明によれば、半導体メモリを構成するマット部における繰返し被検査パターンを、チップ全体の感度に律束されることなく、高感度で、且つ高信頼度で検査することができる効果を奏する。
また本発明によれば、繰返される被検査パターンに生じる欠陥等について詳細解析ができるようにして真の欠陥について高信頼度で検査することができる。
【０１５２】
また本発明によれば、繰返される被検査パターンについて出来具合を定量的に把握することができる効果を奏する。
【０１５３】
また本発明によれば、繰返される被検査パターンについて出来具合を定量的に把握して被検査パターンを製造する製造プロセス（ステッパの解像度やエッチングの良否など）を診断し、その結果を製造プロセスにフィードバックすることができる効果を奏する。
また本発明によれば、半導体ウェーハ等の半導体基板において、面荒れ、グレイン等が生じる多層の被検査パターンの表面の状態に影響されることなく被検査パターンを高感度で、且つ高信頼度で検査して高信頼性を有する半導体基板を製造することができる効果を奏する。
また本発明によれば、１または複数の画像に対して高精度に位置合わせができ、その結果繰返される被検査パターンにおける欠陥等の特徴量を忠実に抽出することができる効果を奏する。
また本発明によれば、電子線ビームを用いて繰返される被検査パターンについて歪みや明るさの違いなどの各種の誤差に影響されることなく、高感度で、且つ高信頼度で検査することができる効果を奏する。
【図面の簡単な説明】
【図１】本発明に係る被検査パターンの検査装置の一実施の形態を示す構成図である。
【図２】図１に示す第１の統計情報生成回路で得られるメモリマット部における濃淡統計画像の略示説明図である。
【図３】図１に示す第２の統計情報生成回路で得られる周辺回路部における濃淡統計画像の略示説明図である。
【図４】図１に示す第１および第２の統計情報生成回路で得られるパターンのエッジ位置の統計画像がパターンの出来具合を示すことを説明するための図である。
【図５】図１に示すエッジ位置抽出回路でパターンのエッジ位置を抽出するための信号波形の関係を説明するための図である。
【図６】統計画像と基準画像または検出画像との比較に基づくマッチングについての略示説明図である。
【図７】本発明に係る被検査パターンの検査装置の他の一実施の形態を示す構成図である。
【図８】本発明に係る画像の位置合わせ方法の略示説明図である。
【図９】図８に示す画像の位置合わせ方法における二つの画像のサンプリング位置関係略示説明図である。
【図１０】本発明に係る被検査パターンの検査装置の更に他の一実施の形態を示す構成図である。
【図１１】本発明に係る製造プロセス解析システムの一実施の形態を示す構成図である。
【図１２】本発明に係る被検査パターンのメモリチップにおけるメモリマット部と周辺回路部の略示説明図である。
【図１３】図１２に示すメモリチップにおけるメモリマット部と周辺回路部における明るさのヒストグラムである。
【図１４】図１２に示すメモリマット部にグレインがある場合の被検査パターンの略示説明図である。
【図１５】画像の位置合わせ回路の別の一実施の形態を示す図である。
【図１６】画像が不連続になる要因の説明図である。
【図１７】画像の境界処理の一実施の形態を説明するための図である。
【図１８】図１および図７に示す比較回路におけるＣＰＵおよび図１５に示す欠陥判定回路の具体的構成の一実施の形態を示す図である。
【図１９】図１および図７に示す詳細解析を行うＣＰＵと異なる他の一実施の形態の概略構成を示す図である。
【図２０】欠陥または欠陥候補の信号として指定した寸法範囲内の欠陥または欠陥候補や指定した位置範囲内の欠陥または欠陥候補としてユーザが指示することにより、所望の欠陥または欠陥候補の画像を格納するための一実施の形態を示す構成図である。
【図２１】被検査パターンの光学画像を検出する光学系の一実施の形態の平面図である。
【図２２】図２２の正面図である。
【図２３】図２１および図２２に示す光学系における偏光の関係を説明するための図である。
【符号の説明】
１…イメージセンサ、 ２…Ａ／Ｄ変換器、 ３ａ…第１の遅延メモリ、 ３ｂ…第１の遅延メモリ、 ４、４ａ…半導体ウェーハ、 ５…Ｘ、Ｙ、Ｚ、θステージ、 ６…対物レンズ、 ７…照明光源、 ８…ハーフミラ、 ９…デジタル画像信号、 １０ａ、１０ｂ…統計情報（統計画像信号）、 １１ａ、１１ｂ…検出画像信号、 １２…入力手段、 １３…記憶装置、 １７ａ…第１の統計情報生成回路、 １７ｂ…第２の統計情報生成回路、 １８ａ…第１の比較回路、 １８ｂ…第２の比較回路、 １９…ＣＰＵ、 ２０…チップ、 ２１…メモリマット部、 ２２…周辺回路部、 ２３ａ〜２３ｄ…遅延メモリ、 ２５…切出し回路、 ２８…エッジ位置抽出回路、 ２９…２値化回路、 ３０…不一致検出回路、 ３１…遅延回路、 ３２…位置合わせ回路、 ３３…欠陥判定回路、 ３４…状態記憶回路、 ３５…位置合わせ、感度制御回路、 ４３ａ、４３ｂ…画像メモリ、 ４４ａ、４４ｂ…ＣＰＵ、 ４５ａ、４５ｂ…メモリ、 ４６ａ、４６ｂ…位置合わせ回路、 ４７ａ、４７ｂ…比較パラメータ設定手段、４８ａ、４８ｂ…ＣＰＵ、 ５１ａ、５１ｂ…欠陥または欠陥候補の信号、 ５２…表示手段、 ５７ａ…欠陥の情報、 ５７ｂ…パターンのでき具合の情報、
１０１…電子源、 １０２…電子線、 １０３…第１の電極、 １０４…第２の電極、 １０５…偏向器、 １０６…半導体ウェーハ、１０８…二次電子、 １０９…二次電子検出器、 １１０…表示・制御装置、 １１１…反射電子検出器、
１２３…メモリ、 １３６…差検出回路、 １３７…２値化回路、 １３８…フィルタ回路、 １３９…特徴量抽出回路、 １４１…欠陥メモリ、 １４７…記憶装置、
３８０…半導体の製造ライン、 ３８１…半導体ウェーハ１ａの搬送経路、 ３８２…絶縁膜を形成する実行するＣＶＤ装置、 ３８３…配線膜を形成するスパッタリング装置、 ３８４…露光工程を実行する露光装置、 ３８５…エッチング工程を実行するエッチング装置、 ３９１…インターフェース、 ３９２…解析等の処理を実行するＣＰＵ、 ３９３…解析等のプログラムを格納したメモリ、 ３９４、３９５、３９６、３９７…制御回路、 ３９８…印刷装置等の出力装置、 ３９９…各種データを表示する表示装置、 ４００…データを各装置間に移送するバスライン、 ４０１…キーボード、ディスク等からなる入力装置、 ４０２…データベースを記憶させる外部記憶装置、 ４０３…インターフェース、 ４１０…欠陥発生に関する情報、[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an appearance inspection for detecting a defect in a pattern to be inspected, and more particularly to a method for inspecting a pattern to be inspected in a semiconductor wafer, a liquid crystal display, or the like. In particular, the present invention relates to a manufacturing process diagnosis method and a manufacturing method of a semiconductor substrate such as a semiconductor wafer that are optimal for evaluating a manufacturing process by using these.
[0002]
[Prior art]
Conventionally, this type of inspection apparatus detects an image of a pattern to be inspected by an image sensor such as a line sensor while moving the pattern to be inspected as in the technique described in Japanese Patent Application Laid-Open No. 55-74409. The inconsistency is recognized as a defect by comparing the density of the image signal and the image signal delayed by a predetermined time.
[0003]
[Problems to be solved by the invention]
By the way, in a pattern to be inspected such as a semiconductor wafer, the pattern is formed of various materials and is laminated in multiple layers. In such a multilayer pattern, for example, the surface of a certain layer may be normal, but the surface may be rough. In the conventional inspection method described above, the inspection performance is regulated by such a normal but rough pattern, and a pattern without rough surface should be able to be inspected with high sensitivity. In some cases, the inspection has to be performed with the sensitivity lowered according to the pattern, and the above-described erroneous detection is likely to occur.
Further, as described above, the sensitivity is lowered due to the rough surface, but when the pattern is grained, the sensitivity is also lowered. In addition, the rough layer and the grained layer do not always appear on the surface, and the surface layer or the lower layer is not constant, so that it looks complicated. This is a problem that is not considered in the conventional technology.
[0004]
In addition, when an electron beam or the like is used as well as when using ordinary light, there is a problem that a fine defect cannot be detected because the distortion of the image is particularly large and the alignment error is large. Further, since secondary electrons and the like are unstable, the brightness of detected images also tends to be unstable. As described above, there is a problem that erroneous detection is likely to occur because there is a difference between images even in a normal pattern.
Furthermore, the conventional inspection method simply determines whether or not there is a defect, and there is a big problem here. In other words, although it cannot be said that the resolution of the stepper etc. and the quality of the etching are defective, the normal part is not suitable for direct quantitative evaluation of the state of the pattern that is somewhat problematic. It was. In other words, the traditional method is to detect only fatal defects, easy-to-understand defects, or epidermal defects that are exposed on the surface, and this alone enables the detection of potential defects and the state of the process objectively. However, there is a problem that it cannot be quantitatively determined.
Further, since the conventional inspection method cannot be directly quantitatively evaluated as described above, there is a problem that it is not suitable for evaluation of a manufacturing process for manufacturing, for example, a semiconductor wafer.
[0005]
An object of the present invention is to solve the above-mentioned problems, and can inspect a pattern to be inspected with high sensitivity and high reliability without being affected by the surface state of a multilayer inspected pattern in which surface roughness, grain, or the like occurs. An object of the present invention is to provide an inspection method for a pattern to be inspected.
Another object of the present invention is to provide a method for inspecting a pattern to be inspected so that a repetitive pattern to be inspected in a mat portion constituting a semiconductor memory can be inspected with high sensitivity and high reliability.
Another object of the present invention is to provide a method for inspecting a pattern to be inspected so that a detailed analysis can be performed with respect to a defect or the like occurring in a repeated pattern to be inspected so that a true defect can be inspected with high reliability. is there.
[0006]
Another object of the present invention is to provide a method for inspecting a pattern to be inspected so that the condition of the pattern to be inspected repeatedly can be quantitatively grasped.
Another object of the present invention is to provide a manufacturing process diagnosing method capable of diagnosing a manufacturing process for manufacturing a pattern to be inspected by quantitatively grasping the result of the pattern to be inspected repeatedly.
Another object of the present invention is to inspect a pattern to be inspected with high sensitivity and high reliability without being affected by the state of the surface of the multilayer inspected pattern in which surface roughness, grain, etc. occur in a semiconductor substrate. Another object of the present invention is to provide a method of manufacturing a semiconductor substrate that can manufacture a highly reliable semiconductor substrate.
[0007]
Another object of the present invention is to provide a method for aligning images that can be accurately aligned with respect to one or a plurality of images.
Another object of the present invention is that a pattern to be inspected that is repeated using an electron beam can be inspected with high sensitivity and high reliability without being affected by various errors such as distortion and brightness differences. An object of the present invention is to provide an inspection method for a pattern to be inspected.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the repeated pattern to be inspected from the detected image signal, and generates this information. A method for inspecting a pattern to be inspected, characterized in that the degree of completion of the pattern to be inspected is quantified using the statistical information.
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the repeated pattern to be inspected from the detected image signal, and uses the generated statistical information A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in the pattern to be inspected is extracted.
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the pattern to be tested repeated from the detected image signal, and generates the statistical information and the detection A defect inspection method for extracting a defect or a defect candidate existing in a pattern to be inspected by comparing with the image signal thus obtained.
[0009]
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the pattern to be tested repeated from the detected image signal, and generates the statistical information and the detection The method for inspecting a pattern to be inspected is characterized in that a feature amount of the pattern to be inspected is extracted by comparing with the image signal thus obtained. Further, the present invention is characterized in that a detailed analysis is performed on the basis of the extracted feature amount to grasp a true defect or a pattern to be inspected.
In the inspection method for a pattern to be inspected, the statistical information is a statistical image signal. Further, the present invention is characterized in that, in the inspection pattern inspection method, the detected image signal is a grayscale image signal of the inspection pattern, and is a statistical grayscale image signal of the inspection pattern repeated as the statistical information. And Further, the present invention is an image signal indicating an edge position of the pattern to be inspected as the detected image signal in the inspection method of the pattern to be inspected, and the statistical edge position of the pattern to be inspected repeated as the statistical information. The statistical image signal shown in FIG.
The present invention also detects an image signal from a repeated pattern to be inspected, generates a statistical image signal indicated by the average value or median value of the pattern to be tested repeated from the detected image signal, and generates the generated statistics A pattern to be inspected, wherein a defect or a defect candidate (including a case indicated by a feature amount) existing in the pattern to be inspected is extracted by comparing the image signal with the detected image signal as a reference image signal. This is an inspection method.
[0010]
The present invention also detects an image signal from a repeated pattern to be inspected, generates a statistical image signal indicated by the average value or median value of the pattern to be tested repeated from the detected image signal, and generates the generated statistics A method for inspecting a pattern to be inspected, wherein a feature amount of a pattern to be inspected is extracted by comparing an image signal as a reference image signal with the detected image signal. Further, the present invention is characterized in that a detailed analysis is performed on the basis of the extracted feature amount to grasp a true defect or a pattern to be inspected.
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the pattern to be tested repeated from the detected image signal, and detects the repeated pattern to be inspected. A defect or a defect candidate existing in a pattern to be inspected by performing a determination process on a difference image obtained by comparing the image signals of the image based on a determination criterion obtained based on the generated statistical information This is a method for inspecting a pattern to be inspected.
In the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged, and this is indicated by a statistic of the pattern to be inspected repeated in the mat portion from the detected image signal. It is characterized by generating statistical information and quantifying the condition of the pattern to be inspected in the mat portion using the generated statistical information in the mat portion so that the conditions and states of the manufacturing process can be grasped or diagnosed. A method for inspecting a pattern to be inspected.
[0011]
In the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged, and this is indicated by a statistic of the pattern to be inspected repeated in the mat portion from the detected image signal. Generate statistical information and statistical information indicated by the statistic of the repeated pattern to be inspected in the peripheral circuit unit, and use the statistical information in the generated mat unit to quantify the degree of the pattern to be inspected in the mat unit, The pattern to be inspected is characterized by quantifying the condition of the pattern to be inspected in the peripheral circuit part using the generated statistical information in the peripheral circuit part and grasping or diagnosing the conditions and state of the manufacturing process. This is an inspection method.
In the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged, and this is indicated by a statistic of the pattern to be inspected repeated in the mat portion from the detected image signal. Statistical information is generated, and a defect or a defect candidate (including a case indicated by a feature amount) existing in a pattern to be inspected in the mat portion is extracted using the generated statistical information in the mat portion. This is an inspection method for a pattern to be inspected.
[0012]
In the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged, and this is indicated by a statistic of the pattern to be inspected repeated in the mat portion from the detected image signal. The statistical information and the statistical information indicated by the statistic of the inspected pattern repeated in the peripheral circuit unit are generated, and the defect or the defect candidate existing in the inspected pattern in the mat unit is generated using the generated statistical information in the mat unit. And the defect or the defect candidate (including the case indicated by the feature amount) existing in the pattern to be inspected in the peripheral circuit unit is extracted using the generated statistical information in the peripheral circuit unit. This is an inspection method for a pattern to be inspected.
Further, the invention is characterized in that the inspection pattern inspection method is applied to an inspection pattern in which a plurality of chips formed to be the same are arranged. The present invention is also characterized in that, in the inspection pattern inspection method, a statistical image is generated for each of the mat portion and the peripheral circuit portion. Further, the present invention is characterized in that, in the inspection method of the pattern to be inspected, the comparison between the statistical image and the detected image extracts a feature amount (a mismatch amount or a mismatch item) based on the mismatch (difference). . In the inspection method of the pattern to be inspected, the comparison between the statistical image and the detected image is to detect a feature amount (a mismatch amount or a mismatch item) based on a difference (mismatch) in a pattern edge position. It is characterized by.
[0013]
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the repeated pattern to be inspected from the detected image signal, and uses the generated statistical information A manufacturing process diagnosis method characterized by quantifying the degree of the pattern to be inspected and diagnosing the suitability of the manufacturing process for manufacturing the pattern to be inspected based on the quantified condition of the pattern to be inspected. .
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the repeated pattern to be inspected from the detected image signal, and uses the generated statistical information Manufacturing characterized by extracting information on a defect or defect candidate existing in a pattern to be inspected and diagnosing the suitability of a manufacturing process for manufacturing the pattern to be inspected based on the extracted information on the defect or defect candidate This is a process diagnostic method.
According to the present invention, in the manufacturing process diagnosis method, the manufacturing process diagnosis item is at least one of pattern resolution, film thickness, and edge definition.
[0014]
Further, the present invention detects an image signal from a semiconductor substrate on which a repeated pattern to be inspected is formed, and generates statistical information indicated by a statistic of the pattern to be inspected repeated from the detected image signal. Quantifying the condition of the pattern to be inspected using statistical information, and manufacturing a semiconductor substrate by diagnosing the suitability of the manufacturing process condition of the pattern to be inspected based on the qualification of the pattern to be inspected A method for manufacturing a semiconductor substrate.
Further, the present invention detects an image signal from a semiconductor substrate on which a repeated pattern to be inspected is formed, and generates statistical information indicated by a statistic of the pattern to be inspected repeated from the detected image signal. The statistical information is used to extract information on defects or defect candidates existing in the pattern to be inspected, and based on the extracted information on the defects or defect candidates, diagnosis is performed on the suitability of the manufacturing process conditions of the pattern to be inspected, and the semiconductor substrate is obtained. A method for manufacturing a semiconductor substrate, comprising: manufacturing a semiconductor substrate.
Also, the present invention linearly interpolates each image to be aligned or linearly interpolates a differential image of each image, and performs the interpolation so that the amount of inconsistency between these interpolated images or the linear combination of the amount of inconsistency is minimized. An image shift amount is obtained with a resolution of a unit of less than a pixel, and the images are aligned by performing linear interpolation, quadratic interpolation, or higher-order convolution interpolation on each image based on the obtained positional shift amount. An image alignment method characterized by the above.
[0015]
In addition, the present invention linearly interpolates each image to be aligned or linearly interpolates a differential image of each image, and the images are arranged so that the amount of inconsistency between these interpolated images or the linear combination of the amounts of inconsistency is minimized. The amount of deviation calculation data using is calculated by the wiring logic, and the amount of deviation to be calculated from the obtained amount of deviation calculation data is obtained by the program logic with a resolution of less than a pixel unit, and the obtained position deviation amount is calculated. The image registration method is characterized in that linear interpolation, quadratic interpolation, or high-order convolution interpolation is performed on each image based on the wiring logic to perform alignment of the image.
In addition, the present invention linearly interpolates each image to be aligned or linearly interpolates a differential image of each image, and the images are arranged so that the amount of inconsistency between these interpolated images or the linear combination of the amounts of inconsistency is minimized. The amount of deviation calculation data using is calculated by the wiring logic, and the amount of deviation to be calculated from the obtained amount of deviation calculation data is obtained by the program logic with a resolution of less than a pixel unit, and the obtained position deviation amount is calculated. The image alignment method is characterized in that the image alignment is performed by using a wiring logic based on a convolution operation for each image.
The present invention also detects an image signal from a repeated inspection pattern, generates a statistical image signal of the inspection pattern repeated from the detected image signal, and uses the generated statistical image signal as a reference image signal. A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate (including a case indicated by a feature amount) existing in a pattern to be inspected is extracted by aligning and comparing with a detected image signal. is there.
[0016]
The present invention also detects an image signal from a repeated inspection pattern, generates a statistical image signal of the inspection pattern repeated from the detected image signal, and uses the generated statistical image signal as a reference image signal. A method for inspecting a pattern to be inspected, wherein a feature amount of the pattern to be inspected is extracted by aligning and comparing with a detected image signal. Further, the present invention is characterized in that a detailed analysis is performed on the basis of the extracted feature amount to grasp a true defect or a pattern to be inspected.
Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the pattern to be tested repeated from the detected image signal, and detects the repeated pattern to be inspected. A defect or a defect candidate present in a pattern to be inspected by performing determination processing based on a determination criterion obtained based on the generated statistical information on a difference image obtained by aligning and comparing two image signals This is a method for inspecting a pattern to be inspected characterized by extracting.
Further, the present invention is an inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating an electron beam onto a sample having the pattern to be inspected, which is generated from the sample by scanning the electron beam. The reflected electrons and the secondary electrons are separated to selectively detect the reflected electrons, an electron beam image is created based on the detected reflected electrons, and a pattern to be inspected using the created electron beam image of the reflected electrons This is a method for inspecting a pattern to be inspected.
[0017]
Further, the present invention is an inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating a sample having a pattern to be inspected, which separately detects reflected electrons and secondary electrons, An inspection method for a pattern to be inspected, wherein a plurality of images are aligned using an image detected by reflected electrons.
The present invention is also an inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating an electron beam onto a sample on which the pattern to be inspected is repeatedly formed, which is formed in the scanning direction of the electron beam. An inspection pattern inspection method comprising inspecting an inspection pattern using an electron beam image obtained from the repeated pattern.
The present invention is also a method for inspecting a pattern to be inspected formed on a sample, comprising: a first inspection step for inspecting a pattern to be inspected based on an optical image detected from the pattern to be inspected; A second inspection step of obtaining a peripheral electron beam image including the inspected portion by scanning and irradiating the inspection pattern with an electron beam, and obtaining detailed information on the inspected portion based on the electron beam image This is a method for inspecting a pattern to be inspected.
[0018]
Further, the present invention is a method for continuously detecting an image signal for a repeated pattern to be inspected, and inspecting the pattern to be inspected based on the continuously detected image signal. A method for inspecting a pattern to be inspected, characterized by determining the continuity of an image using not only the positional deviation information of the past image but also controlling the inspection sensitivity at the boundary portion of the discontinuous image based on this. .
Further, the present invention is a method for continuously detecting an image signal for a repeated pattern to be inspected, and inspecting the pattern to be inspected based on the continuously detected image signal. A method for inspecting a pattern to be inspected characterized in that the continuity of an image is determined using not only the positional deviation information of the past image but also the boundary portion of the discontinuous image as a non-inspection area based on this. .
[0019]
As described above, according to the above configuration, the pattern to be inspected can be inspected with high sensitivity and high reliability without being affected by the surface state of the multilayer inspected pattern in which surface roughness, grain, or the like occurs. Can do.
Moreover, according to the said structure, the repeated test pattern in the mat | matte part which comprises a semiconductor memory can be test | inspected with high sensitivity and high reliability.
Moreover, according to the said structure, a detailed defect can be analyzed about the defect etc. which arise in the to-be-inspected pattern repeated, and a true defect can be test | inspected with high reliability.
[0020]
Moreover, according to the said structure, a completion condition can be grasped | ascertained quantitatively about the to-be-inspected pattern to be repeated.
Moreover, according to the said structure, the manufacturing process which manufactures a to-be-inspected pattern can be diagnosed by grasping | ascertaining a quantitative condition about the to-be-inspected pattern to be repeated.
[0021]
Further, according to the above configuration, the pattern to be inspected can be highly sensitive and reliable without being affected by the surface state of the multi-layer inspected pattern in which surface roughness, grain, or the like occurs in a semiconductor substrate such as a semiconductor wafer. A semiconductor substrate having high reliability can be manufactured by inspection.
Moreover, according to the said structure, it can align with high precision with respect to one or several image. As a result, it is possible to faithfully extract feature quantities such as defects in the pattern to be inspected repeatedly.
Further, according to the above configuration, the pattern to be inspected repeated using the electron beam can be inspected with high sensitivity and high reliability without being affected by various errors such as distortion and brightness difference. it can.
[0022]
The effects obtained by the present invention will be described in detail from the functional aspect.
For example, in a pattern to be inspected in which a plurality of chips having a memory mat portion and a peripheral circuit portion are arranged, in order to quantitatively represent the finish of each pattern and extract the feature amount of a defect or defect candidate using this, Inspecting the defects or defect candidates that occur with high sensitivity without the inspection sensitivity of the entire chip being limited by the poorly finished layers of these multi-layer patterns, that is, layers with rough patterns or grains. Can do.
Also, using statistical information that quantitatively expresses the finish of the pattern, regarding the resolution of the stepper etc. and the quality of the etching, it is possible to determine the degree of each pattern that does not become a defect but is at the limit as a normal part. Quantitative evaluation can be performed accurately and directly. Needless to say, this statistical information can be used to grasp the details in a multilayer pattern in detail and directly quantitatively.
In addition, the manufacturing process itself can be quantitatively grasped by using a statistical image and an inspection method using the statistical image.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the present invention will be described with reference to the drawings.
First, an embodiment of a pattern to be inspected according to the present invention will be described.
FIG. 12 is a diagram for schematically illustrating a memory mat portion and a peripheral circuit portion in a semiconductor memory chip formed on a semiconductor wafer as one embodiment of a pattern to be inspected. FIG. 2 is a diagram showing a histogram of brightness (shading) in a memory mat portion and a peripheral circuit portion in the semiconductor memory chip shown. FIG. FIG. 14 is a schematic diagram of a pattern to be inspected in which there is a grain in the memory mat portion of FIG.
As shown in FIG. 12, a large number of memory chips 20 are arranged on the semiconductor wafer 4. The memory chip 20 can be roughly divided into a memory mat portion 21 and a peripheral circuit portion 22. The memory mat portion 21 is a set of small repetitive patterns, and the peripheral circuit portion 22 is a set of patterns and the like repeated in a uniaxial direction as shown in FIG. The memory mat portion 21 and the peripheral circuit portion 22 are formed of various materials and laminated in multiple layers.
[0024]
FIG. 13 shows the brightness distribution in the memory mat portion 21 and the peripheral circuit portion 22 of FIG. 12, that is, the frequency with respect to the density of the memory chip having a maximum of 1024 bits in the 10-bit configuration, as a histogram. The memory mat portion 21 has a high pattern density and is generally dark. On the other hand, the peripheral circuit portion 22 has a low pattern density and is generally bright.
Therefore, it is difficult for the memory mat portion 21 to detect a minute defect, and the peripheral circuit portion 22 tends to erroneously detect a normal portion as a minute defect.
Further, as shown in FIG. 15, in the specific layer of the pattern in the memory mat portion 21, a large number of minute protrusions called grains are formed on the surface of the pattern, and this causes a difference in brightness. The pattern in which the grain is generated becomes a surface layer or a lower layer and the position thereof is not constant, and the density (brightness) of an image signal obtained by imaging from the pattern is not uniform. Similarly, regarding the roughness of the surface of the pattern, the shading (brightness) of the image signal obtained by imaging from the pattern is not uniform.
[0025]
Next, an embodiment of a method for inspecting a pattern to be inspected, a method for diagnosing a manufacturing process and a method for manufacturing a semiconductor substrate according to the present invention will be described.
[0026]
[Embodiment 1]
A first embodiment of a method for inspecting a pattern to be inspected, a method for diagnosing a manufacturing process, and a method for manufacturing a semiconductor substrate according to the present invention will be described. FIG. 1 is a block diagram showing a first embodiment of an inspection pattern inspection apparatus according to the present invention. FIG. 2 is a schematic explanatory diagram of a grayscale statistical image in the grayscale (brightness) statistical information generated in the first embodiment in the memory mat portion of the pattern to be inspected, and FIG. 3 is a peripheral circuit portion of the pattern to be inspected. FIG. 3 is a schematic explanatory diagram of a grayscale statistical image in the grayscale (brightness) statistical information generated in the first embodiment. FIG. 4 is a schematic explanatory view of the pattern edge of the pattern to be inspected for explaining the statistical image of the pattern edge in the statistical information related to the pattern edge generated in the second embodiment. FIG. 5 is a schematic explanatory view of local area matching for quantitatively grasping (inspecting) the line width and the degree of droop of a pattern using a statistical image of pattern edges. FIG. 6 is a block diagram showing a second embodiment of the inspection apparatus for a pattern to be inspected according to the present invention.
[0027]
In the first embodiment, a semiconductor wafer will be described as an example of a pattern to be inspected. In FIG. 1, reference numeral 1 denotes an image sensor, which outputs a grayscale image signal corresponding to the brightness of reflected light from the semiconductor wafer 4 that is the pattern to be inspected, that is, the grayscale. Reference numeral 2 denotes an A / D converter that converts a grayscale image signal obtained from the image sensor 1 into a digital image signal 9, 3a denotes a first delay memory that delays the digital image signal (digital grayscale image signal) 9, and 3b denotes a digital image. This is a second delay memory for delaying the signal (digital grayscale image signal) 9. That is, the first delay memory 3a delays the digital image signal (digital grayscale image signal) 9 until the first statistical information generation circuit 17a can generate statistical information with about 5 to 20 two-dimensional repeating patterns. Is. Further, the second delay memory 3b is configured to generate a digital image signal (digital gray level) until the second statistical information generation circuit 17b can generate statistical information over about 5 to 20 one-dimensional repetitive patterns or several chip units. (Image signal) 9 is delayed. 4 is a semiconductor wafer having a pattern to be inspected, 5 is a stage in which the semiconductor wafer 4 having a pattern to be inspected is placed, moving in the X, Y, Z, and θ directions (rotation), and 6 is an objective lens for the semiconductor wafer 4. , 7 is an illumination light source that illuminates the semiconductor wafer 4 of the pattern to be inspected, and 8 is a half mirror that reflects the illumination light and irradiates the semiconductor wafer 4 through the objective lens 6 and transmits the reflected light from the semiconductor wafer 4. . Reference numeral 9 denotes a digital image signal obtained by converting a grayscale image signal by an A / D converter. In this way, the illumination light from the illumination light source 7 is reflected, and the semiconductor wafer 4 is configured to be subjected to, for example, bright field illumination through the objective lens 6. For example, the digital image signal 28 (shown in FIG. 5 (b)) obtained from the A / D converter 2 is subjected to differential processing, and the differential processing is performed on the differential signal (FIG. 5 (c)). The differentiated differential signal waveform 42a is output.) 42a is output as it is, or this differential signal is binarized with a predetermined threshold value (shown in FIG. 5D or FIG. 5E). Fig. 5 (d) shows a binarized signal waveform obtained by binarizing the differentiated signal waveform 42a with a predetermined positive threshold, and Fig. 5 (e) shows 2 with a predetermined positive and negative threshold with respect to the differentiated signal waveform 42a. This is an edge extraction circuit for extracting a signal 42 (42a or 42b) indicating the edge position of the pattern by outputting the binary signal 42b. That is, from the pattern shown in FIG. 5A, the digital image signal 9 shown in FIG. 5B is output from the A / D converter 2 by, for example, bright field illumination. The edge extraction circuit 28 performs differential processing on the digital image signal 9 to show the edge position information of the pattern that changes most steeply in the digital image signal 9 as shown in the differential signal 42a (FIG. 5C). ) Is obtained. Further, the edge extraction circuit 28 further binarizes the differential signal 42a with a predetermined threshold value, thereby obtaining a binarized signal 42b (FIG. 5D or FIG. 5E) indicating the edge position information of the pattern. Is obtained). Reference numeral 41 denotes an electronic switch circuit which switches between the first and second digital image signals 9 corresponding to the shade obtained from the A / D converter 2 and the signal 42 indicating the edge position of the pattern obtained from the edge extraction circuit 28. Are applied to the statistical information generation circuits 17a and 17b and the delay memories 3a and 3b. That is, in the defect inspection, when the signal to be handled is only the digital image signal 9 corresponding to the light and shade, the edge extraction circuit 28 and the electronic switch circuit 41 become unnecessary. In the defect inspection, when the signal to be handled is only the signal 42 indicating the edge position of the pattern, the electronic switch circuit 41 becomes unnecessary. On the contrary, by inputting a selection signal to the electronic switch circuit 41, it is possible to select one of the digital image signal 9 corresponding to the density and the signal 42 indicating the edge position of the pattern as a signal to be handled in the defect inspection.
[0028]
The first statistical information generation circuit 17a repeats a pattern in the memory mat unit 21 in which a pattern (memory cell) is repeated two-dimensionally with respect to the digital image signal 9 corresponding to the light and shade output from the A / D converter 2. A pattern (memory cell) is two-dimensionally displayed with respect to a gray level (brightness) statistical image or gray level statistical information including gray level (brightness) statistical data or a signal 42 indicating the edge position of the pattern output from the edge extraction circuit 28. Edge position statistical information including a statistical image indicating the edge position of the repeated pattern in the repeated memory mat portion 21 or statistical data indicating the edge position of the pattern is generated. The first statistical information generating circuit 17a includes a line memory 43a for sequentially storing detected image signals (detected grayscale image signals or detected edge position image signals) detected from about 5 to 20 two-dimensional repetitive patterns; The detected image signal f (i + kPx, j + lPy) at the corresponding position (i + kPx, j + lPy) is read from the line memory 43a, and the average value or median value g (i, j) (shown by the following (Equation 1)). ), Standard deviation σ (i, j) (shown by the following equation (2)), maximum value max (i, j), minimum value min (i, j), or maximum and minimum values Difference R (i, j) = max (i, j) −min (i, j), average value or median value g (i, j) calculated by CPU 44a, standard deviation σ ( i, j), maximum value max (i , J), a minimum value min (i, j), or a memory 45a for storing statistical information including a difference R (i, j) between the maximum value and the minimum value. The average value or median value g (i, j), standard deviation σ (i, j), maximum value max (i, j), minimum value min (i, j), or difference R between the maximum value and the minimum value (I, j) and the like are referred to as items (parameters) of a gray-scale statistical image. That is, the first statistical information generation circuit 17a has a corresponding position (i + kPx, j + lPy) from about 5 to 20 two-dimensional repetitive patterns in the memory mat portion 21 where the patterns (memory cells) are repetitively two-dimensionally. Brightness (shading) or average value or median value g (i, j) of edge position f (i + kPx, j + lPy), brightness (shading) or standard deviation σ (i, j) of edge position, brightness (shading) ) Or the maximum value max (i, j) of the edge position, the brightness (shading) or the minimum value min (i, j) of the edge position, or the difference between the maximum value and the minimum value of the brightness (shading) or edge position R (i, j) = max (i, j) −min (i, j) is detected. (I, j) indicates coordinates on the repetitive pattern. Px represents the pitch in the X direction of the repetitive pattern in the memory mat portion 21, and Py represents the pitch in the Y direction of the repetitive pattern in the memory mat portion 21. Since these pitches Px and Py vary depending on the type of wafer, the pitches Px and Py corresponding to the type of wafer are registered in the CPU 44a, and information on the type of wafer is input by the input means 12. It is possible to select one that matches the input wafer type from the registered pitch Px and Py information. That is, since the first statistical information generation circuit 17a generates a statistical image of grayscale or edge positions, which is statistical information of a repetitive pattern in the memory mat unit 21, the CPU 44a is connected to a keyboard, a disk, and a CAD system. Based on coordinates such as array data in the chip on the wafer 4 obtained based on design information input by the input means 12 configured from a communication network or the like, it is determined that the area is the memory mat portion 21; Based on the pitches Px and Py in the X direction and Y direction of the repetitive pattern in the memory mat portion 21 obtained based on the design information input by the input means 12 for the determined memory mat portion 21, the repetitive pattern Statistical image of gray level or edge position that is statistical information can be generated Further, the CPU 44a reads the detected image signal f (i + kPx, j + lPy) at the corresponding position (i + kPx, j + lPy) from the line memory 43a and applies statistical processing. At this time, at the corresponding position (i + kPx, j + lPy) Unless the detected image signal f (i + kPx, j + lPy) is read, the detected image signal f (i + kPx, j + lPy) at the corresponding position (i + kPx, j + lPy) is calculated, and the calculated mismatched amount is not significantly different. By performing a process that considers a match (a process of determining a very rough match), it is possible to determine whether or not it is an area of the memory mat portion 21 by looking at two-dimensional repeatability. Therefore, in the CPU 44a, it is possible to determine the area of the memory mat portion 21 by adding the matching determination process. The pitches Px and Py in the X direction and Y direction of the repetitive pattern input by the input means 12 can be set for the memory mat portion 21.
[0029]
As described above, the first statistical information generation circuit 17a uses the statistical image (average value or median value g (i, j), brightness (lightness) which is statistical information of the repetitive pattern in the memory mat unit 21 by the first statistical information generation circuit 17a. Density) or standard deviation σ (i, j) of edge position or brightness (darkness) or difference R (i, j) between the maximum value and the minimum value of edge position, etc. Alternatively, it can be obtained by storing the statistical image of the edge position in the memory 45a. The first statistical image generation circuit 17a is configured to output, for example, a plurality of 8-bit digital signals corresponding to the respective statistics.

The first statistical information generation circuit 17a has been described with respect to the calculation of the statistical image of the shading or edge position, which is the statistical information of the repetitive pattern in the X-axis and Y-axis directions, by the CPU. It is clear that the CPU may calculate a grayscale or edge position statistical image, which is statistical information of a repetitive pattern only in the axial direction. This is because there is no change in the grayscale or edge position statistical image due to the difference in the direction in which the pattern is repeated.
[0030]
FIG. 2 shows a grayscale statistical image of one pattern (memory cell) repeated two-dimensionally in the memory mat portions 21 stacked in multiple layers.
FIG. 2A shows a statistical image having a standard deviation σ (i, j) × k of shading. Since 61 is a pattern of the surface layer, it is greatly affected by randomly generated surface roughness and grains, and the standard deviation of the light and shade (brightness variation) becomes large, resulting in a bright image signal. 62 is a lower layer pattern. The portion overlapping the surface layer pattern 61 is erased by the surface layer pattern, and the other regions are the lower layer, so that the effects of randomly generated surface roughness and grains are attenuated. As a result, the standard deviation of the light and shade (brightness variation) becomes small, resulting in a dark image signal. Therefore, the sensitivity at the time of determining a defect with respect to the cell comparison difference image in the comparison circuit 18a or extracting the defect candidate is changed in accordance with the grayscale statistical image signal of the grayscale standard deviation σ (i, j) × k. be able to. That is, since the surface layer pattern 21 has a large variation in lightness (lightness / darkness), the sensitivity is lowered, and since the pattern 22 in the lower layer has a small variation in lightness (lightness / darkness), the sensitivity is increased. What is necessary is just to extract a defect determination or a defect candidate.
FIG. 2 (b) shows a statistical image of the average value g (i, j) of light and shade. Reference numeral 61 denotes a surface layer pattern, which is detected as a relatively dark image signal on average. Reference numeral 62 denotes a lower layer pattern, which is detected as an average brighter image signal than the surface layer pattern 61. The image of the grayscale average value g (i, j) indicates the average value of the detected image signal detected over about 5 to 20 two-dimensional repetitive patterns, and the detected image for inspecting the defect. A reference image signal suitable for comparison with the signal f (i, j) can be obtained from the wafer to be inspected. Therefore, compared with comparison between detected image signals detected from adjacent cells (repeated patterns) in the memory mat unit 21, the influence of randomly generated surface roughness and grains is reduced, and defect determination or defect candidate detection is performed. Extraction can be realized with high reliability.
[0031]
FIG. 2 (c) shows a statistical image of the minimum value min (i, j). Reference numeral 61 denotes a surface layer pattern, which has a large standard deviation (brightness variation) as shown in FIG. 2A with respect to a relatively dark image signal on average as shown in FIG. 2B. Therefore, the minimum value image is detected very darkly. Reference numeral 62 denotes a lower layer pattern. As shown in FIG. 2B, the standard deviation (brightness variation) as shown in FIG. 2A with respect to an image signal brighter than the surface layer pattern 61 on the average. ) Is small, the image of the minimum value min (i, j) is detected slightly darker than the image signal shown in FIG. As shown in FIG. 2B, the statistical image having the maximum density max (i, j) has a symmetrical relationship with the image shown in FIG. 2C with respect to a relatively dark image signal on average. . Therefore, the statistical image of the difference R (i, j) = max (i, j) −min (i, j) between the maximum value and the minimum value of light and shade (brightness) is about 5 to 20 two-dimensional images. This indicates a range in which the detected image signal detected from the repetitive pattern varies (fluctuates). The statistical image of the median value between the maximum value and the minimum value of light and shade is almost the same as the statistical image of the average value g (i, j) of light and shade. Further, a statistical image of the difference R (i, j) between the maximum value and the minimum value of the light and shade (brightness) can be used instead of the statistical image of the light and shade standard deviation.
Further, the statistical image of the edge position of the two-dimensionally repeated pattern (memory cell) in the memory mat unit 21 stacked in multiple layers generated by the first statistical information generation circuit 17a includes an edge position (differential image signal or 2). Any one of the valued image signals may be used.) The image regarding the standard value σ (i, j) of the edge position indicating the variation of the average value or median value g (i, j) and the edge position and the edge position can be taken. There is an image with a difference R (i, j) = max (i, j) −min (i, j) between the maximum value and the minimum value of the edge position indicating the range. The average value or median value g (i, j), standard deviation σ (i, j), maximum value max (i, j), minimum value min (i, j), or difference R between the maximum value and the minimum value (I, j) etc. are referred to as each item (parameter) of the statistical image of the edge position. The statistical image of the median value between the maximum value and the minimum value of the edge position is almost the same as the statistical image of the average value g (i, j) of the edge position. Instead of the statistical image of the standard deviation of the edge position, a statistical image of the difference R (i, j) between the maximum value and the minimum value of the edge position can be used.
[0032]
Variations in process conditions such as resist application unevenness, stepper exposure resolution, spatter and CVD film thickness variations, and etching conditions variations (for example, variations or lots between the central and peripheral portions of the wafer) There are various fluctuation factors such as fluctuations depending on the unit and fluctuations based on the type of wafer.) As shown in FIG. 4, the pattern edge quality changes. That is, as shown in FIGS. 4 (a) and 4 (b), the edge of the pattern includes the degree of clarity (how much) depending on the process conditions such as etching, and minute irregularities as shown in FIG. 4 (c). The line width partially varies within the wafer. For each repetitive pattern, the degree of drooping of the edge shown in FIG. 4 (a) is smaller than that of the edge shown in FIG. 4 (b). The parameter that is the standard deviation of the differential image is increased. In addition, as shown in FIG. 4 (c), the line width varies for each repetitive pattern including fine irregularities, and as a result, a parameter that is a standard deviation of the differential image or binarized image indicating the edge position of the pattern. Becomes larger. Variations in the pattern edge also occur depending on the lot unit or product type.
[0033]
The image of the average value g (i, j) of the edge position indicates the average value of the detected image signal detected over about 5 to 20 two-dimensional repetitive patterns, and is detected to inspect the defect. A reference image signal suitable for comparison with the image signal f (i, j) can be obtained from the wafer to be inspected. Therefore, compared with comparison between detected image signals detected from adjacent cells (repeated patterns) in the memory mat unit 21, the influence of the edge condition of the pattern that is randomly generated due to variation in process conditions is reduced. Thus, defect determination or defect candidate extraction can be realized with high reliability.
Further, the process is performed by changing the sensitivity at the time of determining a defect with respect to the cell comparison difference image or extracting the defect candidate in the comparison circuit 18a in accordance with the statistical image signal of the standard deviation σ (i, j) of the edge position. Even if the condition of the pattern edge changes due to a change in conditions, defect determination or defect candidate extraction can be realized with high reliability.
[0034]
As shown in FIG. 3A, the second statistical image generation circuit 17b performs one-dimensional (for example, in the Y-axis direction) on the digital image signal 9 corresponding to the light and shade output from the A / D converter 2. In the peripheral circuit unit 22 where the pattern is repeated, the light / dark statistical information consisting of the light / dark (brightness) statistical image or light / dark (brightness) statistical data of the repeated pattern, or the signal 42 indicating the edge position of the pattern output from the edge extraction circuit 28 In contrast, edge position statistical information including a statistical image indicating the edge position of the repeated pattern in the peripheral circuit unit 22 where the pattern is repeated one-dimensionally or statistical data indicating the edge position of the pattern is generated. The first statistical information generation circuit 17b sequentially stores detected image signals (detected grayscale image signals or detected edge position image signals) detected over about 5 to 20 one-dimensional repetitive patterns. Then, the detected image signal f ′ (i, j + lPy ′) at the corresponding position (i, j + lPy ′) is read from the line memory 43b, and the average value or median value g ′ (i, j) (the following (Expression 3) ), Standard deviation σ ′ (i, j) (shown by the following equation (4)), maximum value max ′ (i, j), minimum value min ′ (i, j) ), Or a CPU 44b for calculating a difference R ′ (i, j) = max ′ (i, j) −min ′ (i, j) between the maximum value and the minimum value, and an average value or median calculated by the CPU 44b Value g ′ (i, j), standard deviation σ ′ (i, j), maximum value max ′ ( i, j), a minimum value min ′ (i, j), or a memory 45b that stores statistical information including a difference R ′ (i, j) between the maximum value and the minimum value. In other words, the second statistical information generation circuit 17b determines the brightness f of the corresponding position (i, j + 1Py ′) from about 5 to 20 one-dimensional repetitive patterns in the peripheral circuit 22 in which the one-dimensional pattern is repeated. Average value or median value g ′ (i, j), standard deviation σ ′ (i, j), maximum value max ′ (i, j), minimum value min ′ (i, j) of “(i, j + lPy ′)” Alternatively, the difference R ′ (i, j) = max ′ (i, j) −min ′ (i, j) between the maximum value and the minimum value is detected. (I, j) indicates coordinates on the repetitive pattern. Py ′ indicates, for example, the pitch in the Y direction, which is a uniaxial direction of the one-dimensional repetitive pattern, as shown in FIG. Since this pitch Py ′ varies depending on the type of wafer, the pitch Py ′ corresponding to the type of wafer is registered in the CPU 44b, and the pitch Py ′ registered by inputting information on the type of wafer is registered. It is possible to select one that matches the wafer type input from the information. That is, since the second statistical information generation circuit 17b generates a statistical image of grayscale or edge position, which is statistical information on the pattern in the peripheral circuit unit 22, the CPU 44b has a communication network, keyboard, Based on the coordinates such as the arrangement data in the chip on the wafer 4 obtained based on the design information input from the input means 12 constituted by a disk or the like, it is determined that the area is the peripheral circuit section 22 and this Based on the pitch Py ′ in the Y direction of the repetitive pattern in the peripheral circuit section 22 obtained based on the design information input from the input means 12 with respect to the determined peripheral circuit section 22, or the repetitive pattern based on the pitch in chip units. It is possible to generate a statistical image of grayscale or edge position, which is the statistical information. Further, since the CPU 44a can determine whether or not it is an area of the memory mat section 21, it can also determine that it is an area of the peripheral circuit section 22. Accordingly, the CPU 44b determines that the area is the peripheral circuit section 22 by receiving the signal 56 which is the area of the peripheral circuit section 22 from the CPU 44a, and inputs the input to the peripheral circuit section 22 through the input means 12. The pitch Py ′ in the Y direction of the repeated pattern or the pitch in units of chips can be set.
[0035]

Further, since the peripheral circuit unit 22 is repeated in units of chips, the second statistical image generation circuit 17b performs chip processing on the digital image signal 9 corresponding to the light and shade output from the A / D converter 2. The signal indicating the edge position of the pattern output from the edge extraction circuit 28 or the density statistical information composed of the density (brightness) statistical image or the density (brightness) statistical data of the pattern in the peripheral circuit unit 22 repeated in units. 42 may generate edge position statistical information including a statistical image indicating the edge position of the pattern in the peripheral circuit unit 22 repeated in units of chips with respect to 42 or statistical data indicating the edge position of the pattern. In this case, it is necessary to store several images in units of chips in the line memory 43b. That is, the CPU 44b reads the detected image signal f ′ (i, j + lPy ′) at the corresponding position (i, j + lPy ′) on a chip basis, and calculates the average value or median value g ′ (i, j), standard deviation σ ′ (i, j), maximum value max ′ (i, j), minimum value min ′ (i, j), or the difference between the maximum value and the minimum value R ′ (i, j) = max ′ (i, j) −min ′ This is because it is necessary to calculate (i, j).
[0036]
As described above, the second statistical information generation circuit 17b uses the statistical image (average value or median value g ′ (i, j), brightness (brightness), which is the statistical information of the pattern in the peripheral circuit unit 22, by the second statistical information generation circuit 17b. Density) or standard deviation σ ′ (i, j) of edge position or brightness (lightness) or difference R ′ (i, j) between maximum value and minimum value of edge position, etc. Further, it is possible to obtain the statistical image of the shade or edge position by storing it in the memory 45b. The second statistical image generation circuit 17b is configured to output, for example, a plurality of 8-bit digital signals corresponding to the statistics.
[0037]
FIGS. 3B and 3C show grayscale statistical images of a part of the pattern in the peripheral circuit section 22 stacked in multiple layers.
FIG. 3B shows a statistical image having a standard deviation σ ′ (i, j) × k of shading. Since 63 is a pattern of the surface layer, it is greatly affected by randomly generated surface roughness and grain, and the standard deviation of the light and shade (brightness variation) becomes large, resulting in a bright image signal. The patterns 65, 66, and 67 are image signals having medium brightness with a medium standard deviation (brightness variation). Reference numerals 64 and 68 are lower layer patterns. The portion overlapping the surface layer pattern 63 is erased by the surface layer pattern, and the other regions are the lower layer. Therefore, random surface roughness and grain are affected. As a result of attenuation, the standard deviation of light and shade (brightness variation) is reduced, resulting in a dark image signal. Therefore, when the defect is determined for the repeated pattern comparison or the chip comparison difference image in the comparison circuit 18b in accordance with the grayscale statistical image signal of the grayscale standard deviation σ (i, j) × k, or when defect candidates are extracted. Can change the sensitivity. That is, the surface layer pattern 23 has a large variation in brightness (lightness / darkness) to reduce the sensitivity, and the lower layer patterns 64 and 68 have a small variation in brightness (lightness / darkness) to reduce the sensitivity. What is necessary is just to raise a defect determination or a defect candidate.
[0038]
FIG. 3C shows a statistical image of the average density g ′ (i, j). The patterns 63, 64 and 68 are detected as bright image signals on average. The patterns 66 and 67 are detected as average average bright image signals. The 65 patterns are detected as dark image signals on average. The image of the grayscale average value g ′ (i, j) indicates the average value of the detected image signal detected over about 5 to 20 one-dimensional repetitive patterns or several chip units. Therefore, a reference image signal suitable for comparison with the detected image signal f ′ (i, j) can be obtained from the wafer to be inspected. Therefore, in the peripheral circuit unit 22 as well, detection of defects or extraction of defect candidates can be performed by reducing the influence of randomly generated surface roughness and grains as compared with detection image signals detected from adjacent repeated patterns. It can be realized with high reliability.
Also in the peripheral circuit unit 22, as in the memory mat unit 21, the difference R ′ (i, j) = max ′ (i, j) −min ′ (i, j) The statistical image of j) shows a range (fluctuation) of detected image signals detected over about 5 to 20 one-dimensional repetitive patterns or several chips. Therefore, the statistical image of the median value between the maximum value and the minimum value of light and shade is almost the same as the statistical image of the average value g ′ (i, j) of light and shade. Further, a statistical image of the difference R ′ (i, j) between the maximum value and the minimum value of the light and shade (brightness) can be used instead of the statistical image of the light and shade standard deviation.
[0039]
The statistical image of the edge position of the one-dimensionally repeated pattern (memory cell) in the peripheral circuit unit 22 stacked in multiple layers generated by the second statistical information generation circuit 17b includes an edge position (differential image signal or 2). Any one of the valued image signals may be used.) An image relating to the average value or median value g ′ (i, j) of the image and the edge position standard deviation σ ′ (i, j) indicating the variation of the edge position There is an image having a difference R ′ (i, j) = max ′ (i, j) −min ′ (i, j) between the maximum value and the minimum value of the edge position indicating a possible range. The statistical image of the median value between the maximum value and the minimum value of the edge position is almost the same as the statistical image of the average value g ′ (i, j) of the edge position. Further, instead of the statistical image of the standard deviation of the edge position, a statistical image of the difference R ′ (i, j) between the maximum value and the minimum value of the edge position can be used.
[0040]
Variations in process conditions such as resist application unevenness, stepper exposure resolution, spatter and CVD film thickness variations, and etching conditions variations (for example, variations or lots between the central and peripheral portions of the wafer) There are various fluctuation factors such as fluctuations depending on the unit and fluctuations based on the type of wafer.) As shown in FIG. 4, the pattern edge quality changes. That is, as shown in FIGS. 4 (a) and 4 (b), the edge of the pattern includes the degree of clarity (how much) depending on the process conditions such as etching, and minute irregularities as shown in FIG. 4 (c). The line width partially varies within the wafer. For each repetitive pattern, the degree of drooping of the edge shown in FIG. 4 (a) is smaller than that of the edge shown in FIG. 4 (b). The parameter that is the standard deviation of the differential image is increased. In addition, as shown in FIG. 4 (c), the line width varies for each repetitive pattern including fine irregularities, and as a result, a parameter that is a standard deviation of the differential image or binarized image indicating the edge position of the pattern. Becomes larger. Variations in the pattern edge also occur depending on the lot unit or product type.
The image of the average value g ′ (i, j) of the edge position indicates the average value of the detected image signal detected over about 5 to 20 one-dimensional repetitive patterns. A reference image signal suitable for comparison with the detected image signal f ′ (i, j) can be obtained from the wafer to be inspected. Accordingly, compared with comparison between detected image signals detected from adjacent cells (repeated patterns) or chip units in the peripheral circuit unit 22, the influence of the edge condition of the pattern that is randomly generated due to variations in process conditions. Thus, defect determination or defect candidate extraction can be realized with high reliability.
Further, the sensitivity at the time of determining a defect or extracting a defect candidate from the difference image of the cell comparison or chip comparison in the comparison circuit 18b according to the statistical image signal of the standard deviation σ ′ (i, j) of the edge position is set. By changing it, it is possible to achieve defect determination or defect candidate extraction with high reliability even if the pattern edge changes due to variations in process conditions.
[0041]
Next, quantification of pattern defect inspection and pattern completion will be described.
The first comparison circuit 18a, for example, a first statistical image signal (gi, j) 10a, which is the first statistical information shown in FIG. 8, and a first detected image signal (fi) obtained from the first delay memory 3a. , j) A positioning circuit 46a that performs positioning by detecting a positional deviation with respect to 11a, comparison parameter setting means 47a in which a comparison parameter for determining a defect is set, and the positioning circuit 46a performs positioning. The first statistical image signal (g′i + Δx, j + Δy) 49a and the first detected image signal (f′i, j) 50a obtained from the first delay memory 3a are set as comparison parameters. The CPU 48a is configured to extract a defect candidate or defect by extracting a feature amount based on a comparison parameter set by the means 47a. The comparison parameter setting means 47a is a standard deviation σ (i, j) of the shading or edge position in the memory mat portion 21 generated by the first statistical information generating circuit 17a or the maximum and minimum values of the shading or edge position. Based on the difference R (i, j), the CPU 48a can extract a feature amount and set a comparison parameter for extracting defect candidates or defects. The comparison parameter setting means 47a includes a communication network, keyboard, disk, wafer type and lot connected to a process apparatus (for example, an exposure apparatus such as a stepper, an etching apparatus, a film forming apparatus such as CVD or sputtering, a resist coating apparatus). It is also possible to set according to the process conditions (exposure conditions, etching conditions, film forming conditions, resist coating conditions, etc.) input by the input means 12 constituted by a reading device or the like, and the wafer type and lot. In short, it is necessary to change the defect candidate and the defect criterion according to the type and lot of the wafer. In addition, defect candidates and defect criteria can be changed according to process conditions.
[0042]
As described above, in the first comparison circuit 18a, the alignment circuit 46a first includes, for example, the first statistical image signal (gi, j) 10a that is the first statistical information shown in FIG. Alignment is performed by detecting a misalignment with the first detected image signal (fi, j) 11a obtained from the memory 3a. Next, the CPU 48a detects the first statistical image signal (g′i + Δx, j + Δy) 49a aligned by the alignment circuit 46a and the first detected image signal (from the first delay memory 3a). f′i, j) 50a are compared based on the comparison parameter set by the comparison parameter setting means 47a, and the feature amount (a mismatch amount of light and shade (brightness) and a mismatched area or maximum length of the binarized image) are compared. A defect candidate or defect signal 51a is extracted, including the center of gravity coordinates (position coordinates), etc., which do not match, and the center of gravity coordinates (position coordinates) indicating the generation position. In other words, the first statistical image signal (gi, j) 10a becomes an averaged reference image signal in the cell comparison for the memory mat unit 21, and the CPU 48a reduces the influence of randomly generated surface roughness and grains. Alternatively, it is possible to reduce the influence of the edge condition of the pattern that randomly occurs due to the process condition variation, and to realize defect determination or defect candidate extraction with high reliability. Further, in the memory mat unit 21, a comparison parameter is set according to the statistical image signal of the standard deviation σ (i, j), thereby determining a defect with respect to the difference image of the cell comparison in the comparison circuit 18a or the defect It is possible to change the sensitivity when extracting candidates, and it is possible to set the sensitivity according to the variation in lightness (shading) obtained from the pattern and extract defect determination or defect candidates. Sensitivity is set according to the degree of completion, and defect determination or defect candidate extraction can be realized with high reliability.
[0043]
In the second comparison circuit 18b, first, the alignment circuit 46b is obtained from the second statistical image signal (gi, j) 10b, which is the second statistical information shown in FIG. 8, for example, and the second delay memory 3b. Alignment is performed by detecting a positional deviation from the first detected image signal (fi, j) 11b. Next, the CPU 48b uses the second statistical image signal (g′i + Δx, j + Δy) 49b aligned by the alignment circuit 46b and the second detected image signal (second delay image 3b obtained from the second delay memory 3b). f′i, j) 50b based on the comparison parameter set by the comparison parameter setting means 47b, and the feature amount (the mismatch amount of light and shade (brightness) and the mismatched area and maximum length of the binarized image) A defect candidate or defect signal 51b is extracted and extracted, including the centroid coordinates (position coordinates) and the like indicating the occurrence position. That is, the second statistical image signal (gi, j) 10b becomes an averaged reference image signal in the cell comparison or chip comparison for the peripheral circuit unit 22, and the CPU 48b has the effect of surface roughness and grains that are randomly generated. It is possible to reduce the influence of the edge condition of the pattern that randomly occurs due to the process condition variation, and to realize defect determination or defect candidate extraction with high reliability. Further, in the peripheral circuit unit 22, by setting a comparison parameter in accordance with the statistical image signal of the standard deviation σ ′ (i, j), a defect is determined for the difference image of the cell comparison or chip comparison in the comparison circuit 18b. Or when extracting defect candidates, it is possible to change the sensitivity, set the sensitivity according to the variation in brightness (shading) obtained from the pattern, and determine the defect or indicate the defect candidate (feature value) In addition, the sensitivity can be set in accordance with the degree of the edge of the pattern, and defect determination or defect candidate extraction can be realized with high reliability.
[0044]
The first comparison circuit 18a and the second comparison circuit 18b may be of a method developed by the present inventors, such as that shown in the technique described in Japanese Patent Laid-Open No. Sho 61-212708, for example, the position of an image. As shown in FIG. 18, the alignment image 46a and 46b, or the difference image detection unit 136 of the aligned image and the difference image detected by the difference image detection unit 136 are binarized by the threshold value Vth, thereby two-dimensional mismatch. The noise component is selected by the filter selection signal 140 obtained from the alignment / boundary sensitivity control circuit 35 shown in FIG. 15 from the mismatch detection unit 137 that detects the noise and the binarized mismatch image detected by the mismatch detection unit 137. The filter unit 138 removed by the filter and the binarized mismatched image from which the noise component has been removed by the filter circuit 138 May be composed of CPU48a and 48b and a feature amount extraction unit 139 for calculating the area or length (projected length), the feature quantity such as coordinates of the defect candidate parts). Further, the CPUs 48a and 48b may realize each of the difference image detection unit 136, the mismatch detection unit 137, the filter unit 138, and the feature amount extraction unit 139 with a circuit configuration. When the first comparison circuit 18a and the second comparison circuit 18b compare the statistical image with the detected image, the brightness (gradation value) of the target pixel of the detected image is the average value of the corresponding pixels of the statistical image. If it is in the range of k times the standard deviation (for example, k = 3), it is determined to be normal, and if it is outside that range, it can be determined as a defect or a defect candidate and output.
[0045]
In the above case, the first comparison circuit 18a and the second comparison circuit 18b determine whether there is a defect or a defect candidate, but as shown in an exaggerated manner in FIG. The deviation amount ΔG from the range or the deviation amount ΔG ′ from the average value, which is information on the degree of completion, may be output as a mismatch amount (indicated by hatching). In this case, if the detected image includes a defect, the information becomes defect candidate information, and if the detected image does not include a defect, the information indicates the pattern quality. In any case, even if it is information on a defect candidate, it can be handled as information indicating the degree of completion of the pattern in the manner of processing in the CPU 19.
Further, in the first comparison circuit 18a and the second comparison circuit 18b, the comparison parameter may be variously changed and inspected a plurality of times, and a logical sum of these inspection results may be taken as a final result. This is the same as in the case of illumination conditions described later.
In addition, it is obvious that the first comparison circuit 18a and the second comparison circuit 18b can extract defects or defect candidates according to the pattern finish.
[0046]
The CPU 19 is data indicating defect candidates (feature quantities) including the barycentric coordinates (position coordinates) indicating the generation position in the memory mat portion 21 obtained by optimizing the sensitivity by setting the comparison parameter from the first comparator 18a. Or the defect signal 51a and the barycentric coordinates (position coordinates) indicating the generation position in the peripheral circuit unit 22 obtained by optimizing the sensitivity by setting the comparison parameter from the second comparator 18b. Including a defect candidate (including a case where it is provided as data indicating a feature amount) or a defect signal 51b, statistical information 10a in the memory mat unit 21 obtained from the first statistical information generation circuit 17a, and second statistics Statistical information 10b in the peripheral circuit unit 22 obtained from the information generation circuit 17b, a process device (for example, an exposure device such as a stepper, an etching device, C D or sputtering film forming apparatus, resist coating apparatus, etc.) and a communication network connected to a higher-level CAD system, keyboard, disk, input device 12 comprising a reading device for reading the type and lot of the wafer, etc. Based on the process conditions, wafer type, lot information, and design information, the defect candidate is analyzed in detail and the pattern quality is determined based on coordinate information such as array data including the inside of the chip on the wafer 4. To analyze.
[0047]
That is, the CPU 19 includes defect candidates (features) including the barycentric coordinates (position coordinates) indicating the generation position in the memory mat unit 21 obtained by optimizing the sensitivity by setting the comparison parameter obtained from the first comparator 18a. It is possible to determine as a true defect by performing a detailed analysis on 51a (including the case where it is provided by data indicating the above). For example, when the defect candidate signal 51a is regularly generated in accordance with the pattern repeated from the first comparator 18a, the coordinates of the array data and the like including the defect candidate signal 51a in the chip on the wafer 4 are also included. It is also possible to detect true defects by erasing using information or the like. In addition, the feature amount (grayscale (brightness) mismatch amount) obtained from the first comparator 18a, the mismatched area, maximum length, and mismatched barycentric coordinates (position of the binarized image (including the image showing the edge position)) For the defect candidate signal 51a indicated by (coordinates) etc., the judgment criteria for determining a true defect are changed according to the process conditions, wafer type and lot information, arrangement data on the wafer 4, etc. True defects can be detected under optimum conditions. As shown in FIG. 4C, the defect type includes a chip defect 71, a protruding defect 72, an isolated defect 73, and the like, and it is necessary to change the determination standard according to the type of the defect. For example, when determining as a true defect based on the mismatched area, it is necessary to change the area according to the type of defect as a determination criterion.
[0048]
Similarly to the memory mat unit 21, the CPU 19 determines the generation position in the peripheral circuit unit 22 obtained by optimizing the sensitivity by setting the comparison parameter obtained from the second comparator 18b for the peripheral circuit unit 22. It is possible to detect a true defect under optimum conditions by performing detailed analysis on a defect candidate (including a case where it is provided by data indicating a feature amount) including a barycentric coordinate (position coordinate) to be shown or a defect signal 51b. it can. The CPU 19 can store the inspected defect information 57a in, for example, the storage device 13 so that it can be output including the barycentric coordinates (position coordinates) indicating the generation position.
Further, the CPU 19 can monitor the defect candidate signals 51a and 51b indicated by the feature values obtained from the first comparator 18a and the second comparator 18b on the display means 52 such as a display. At this time, the process conditions, wafer type and lot information inputted by the input means 12 and the arrangement data on the wafer 4 can be written together and displayed on the display means 52, and the pattern is manufactured in terms of defect inspection. Process status can be monitored.
The comparison result of the memory mat unit 21 is obtained from the first comparison circuit 18a, and the comparison result of the peripheral circuit unit 22 is obtained from the second comparison circuit 18b. On the basis of the coordinate information on the wafer thus identified, the memory mat portion 21 or the peripheral circuit portion 22 is identified, and the comparison result from the first comparison circuit 18a and the comparison result from the second comparison circuit 18b. The final determination may be made by selecting. Further, the CPU 19 may select the cell comparison in the memory mat portion 21 by the first comparator 18a and the cell comparison or chip comparison in the peripheral circuit portion 21 by the second comparator 18b as follows. Good. That is, the CPU 19 calculates mismatch information by cell comparison obtained from the first comparator 18a, for example, for each image in a range in which the number of mismatch pixels is determined. Since it can be determined that the area is not an area, the result of the peripheral circuit section 22 obtained from the second comparator 18b is selected. If the number of mismatched pixels is smaller than the threshold value, the area of the memory mat section 21 is determined. By being able to determine, the result obtained from the first comparator 18a can be selected. According to this method, the CPU 19 can select the chip comparison and the cell comparison without the arrangement information in the chip.
[0049]
Further, the CPU 19 uses the first and second statistical images 10a and 10b stored in the delay memories 23a and 23c and the detected image signals 11a and 11b stored in the delay memories 23a and 23c as, for example, a defect signal or a defect candidate signal. It is obvious that detailed analysis may be performed by cutting out via the cutting circuit 25 by the cutting signal 24 obtained based on 51a and 51b.
Further, when the CPU 19 quantifies and analyzes the pattern completion with respect to the memory mat unit 21 and the peripheral circuit unit 22, the statistical information 10a in the memory mat unit 21 obtained from the first statistical information generation circuit 17a The statistical information 10b in the peripheral circuit unit 22 obtained from the second statistical information generation circuit 17b is used. And CPU19 can memorize | store in the memory | storage device 13, for example so that it can output as the data 57b which quantified the quality of the pattern.
That is, in the multi-layer pattern, the grayscale image 9 obtained from this pattern varies greatly depending on whether a pattern having grain or surface roughness on the surface is present in the surface layer or in the lower layer, and as a result, for example, FIG. As shown in FIG. 8, the gray standard deviation σ (i, j), which is the gray statistical information 10a obtained from the first statistical information generation circuit 17a, and the difference R (i, j) between the minimum value and the maximum value. The parameter j) becomes large, and as shown in FIG. 3B, the gray standard deviation σ ′ (i, i, which is the gray statistical information 10b in the peripheral circuit unit 22 obtained from the second statistical information generation circuit 17b. j) and the parameter of the difference R ′ (i, j) between the minimum value and the maximum value is increased.
[0050]
The CPU 19 also calculates an average value g which is the edge position statistical information 10a in the memory mat unit 21 obtained from the first statistical information generation circuit 17a based on the image signal 42 indicating the edge position of the pattern obtained from the edge extraction circuit 28. Quantifying the pattern quality of the memory mat portion based on parameters of (i, j), standard deviation σ (i, j) of edge position and difference R (i, j) between minimum and maximum values The average value g ′ (i, j) (shown in FIG. 3A) and the edge position statistical information 10b in the peripheral circuit section 22 obtained from the second statistical information generation circuit 17b. Based on the standard deviation σ ′ (i, j) and the parameters of the difference R ′ (i, j) between the minimum value and the maximum value, the degree of the pattern of the peripheral circuit portion can be quantified. That is, the CPU 19 compares the statistical information on the edge position in the central portion and the statistical information on the edge position in the peripheral portion obtained from the first and second statistical information generation circuits 17a and 17b in one wafer 4. Thus, the difference between the central portion and the peripheral portion in one wafer 4 can be grasped. When the statistical information is an average value, it is possible to quantitatively grasp the average difference such as the pattern width between the central portion and the peripheral portion in the wafer 4 and the inclination of the edge of the pattern (the degree of pattern cutting by etching). .
[0051]
Further, the CPU 19 can grasp the difference in the lot unit by comparing the statistical information of the edge position obtained in the lot unit of the wafer 4 from the first and second statistical information generation circuits 17a and 17b. When the statistical information is an average value, it is possible to quantitatively grasp an average difference such as a pattern width and a pattern edge inclination in a lot unit (pattern cutting condition by etching).
Further, the CPU 19 can grasp the difference according to the type of wafer by comparing the statistical information of the edge position obtained according to the type of the wafer 4 from the first and second statistical information generation circuits 17a and 17b. it can. When the statistical information is an average value, it is possible to quantitatively grasp an average difference such as a pattern width corresponding to the type of wafer and an inclination of a pattern edge (pattern cutting condition by etching).
Further, as shown in FIG. 6A, the CPU 19 obtains an average value statistical image (FIG. 6 (FIG. 6)) indicating the edge position in the statistical information of the edge positions obtained from the first and second statistical information generation circuits 17a and 17b. a) and an ideal reference image (reference image based on design specifications) based on CAD information input using the input means 12 (shown on the left side of FIG. 6A). As shown by the arrows, the amount of deviation for each local region is obtained by matching for each local region, and the difference between the design values (line width) is obtained by taking the sum of the amount of deviation over the region where the pattern exists. Fluctuations, changes in the amount of dripping of edges, etc.) can be quantitatively grasped. That is, even when the edge of the pattern is steep in a large area, the degree of pattern deformation can be quantified and output.
[0052]
By the way, the shape of a pattern actually manufactured often differs slightly from a design value. Therefore, the CPU 19 does not compare with the ideal reference image based on the CAD information, but actually picks up the image from the A / D converter 2 and detects it from the detected image signals stored in the delay memories 23b and 23d. The detected image signal 53 can be selected by being cut out by the cut-out circuit 25 by the cut-out designation signal 24.
[0053]
Then, as exaggeratedly shown in FIG. 6B, the CPU 19 obtains edge positions obtained from the first and second statistical information generation circuits 17a and 17b with respect to the selected standard detection image signal 53. Is calculated by calculating a discrepancy amount (indicated by hatching) that deviates from an allowable value ± ΔE set using a standard deviation σ (i, j) or the like with respect to the average value statistical image g (i, j) indicating. It is possible to quantify and understand the degree of pattern completion (line width, degree of deformation due to etching, etc.). The allowable value ± ΔE may be arbitrarily set using the input unit 12. The average statistical image g (i, j) and the standard detected image signal 53 may be differential image signals. In that case, the difference value is an integral value of the difference signal of the differential image signal.
[0054]
In the above embodiment, the standard detection image signal 53 is selected by cutting out from the delay memories 23b and 23d, and the first and second statistical information generations are performed on the selected standard detection image signal 53. A mismatch amount (slashed line) deviating from an allowable value ± ΔE set using a standard deviation σ (i, j) or the like with respect to an average value statistical image g (i, j) indicating edge positions obtained from the circuits 17a and 17b. In this case, the degree of pattern completion is quantified and grasped, but the amount of mismatch of the edge positions (statistic image of the edge position) obtained from the first and second comparators 18a and 18b is calculated. A deviation value of the edge position in the detected image f (i, j) from a range based on the standard deviation σ (i, j) with respect to the average value g (i, j) and an average value g ( i The CPU 19 calculates the total amount of the predetermined pattern area (for example, cell unit), the unit of chip unit, or the unit of wafer in the detected image f (i, j) from j). It is possible to quantify and grasp the pattern performance in a predetermined pattern area (for example, cell unit) or chip unit or wafer unit. As a result, information on the quantified pattern performance can be obtained by exposure or etching. It can be used as a measure of process conditions such as film formation and resist coating.
[0055]
Further, as described above, the edge position statistical information (average value and standard deviation) obtained from the first and second statistical information generation circuits 17a and 17b is used for process conditions such as direct exposure, etching, film formation, and resist coating. It can be used as a scale.
[0056]
Naturally, in the chip 57 on the wafer 4 obtained based on the process conditions, wafer type, lot information and design information inputted by the input means 12 with respect to the data 57b obtained by quantifying the pattern quality obtained in the CPU 19. It is obvious that the data can be stored in, for example, the storage device 13 so that coordinate information such as array data including the data can be output.
[0057]
Next, an embodiment different from the embodiment shown in FIG. 1 will be described with reference to FIG. In this embodiment, the detected image signal 11a obtained from the first delay memory 3a in the first comparator 18a and the detected image signal 11b delayed by an integral multiple of the pitches Px and Py of the repetitive pattern in the delay memory 54a, Of the detected image signal 50a and the detected image signal 50c aligned by the alignment circuit 46a and extracting a feature amount based on the comparison parameter set by the comparison parameter setting means 47a to detect a defect candidate or Defects are extracted and detected image signal 11b obtained from second delay memory 3b in second comparator 18b and detected image signal delayed by an integral multiple of repeat pattern pitch Py 'or chip pitch in delay memory 54b. 11d and cell comparison or chip comparison, and the detected image signal 50b aligned by the alignment circuit 46b The feature parameter is extracted based on the comparison parameter set by the comparison parameter setting unit 47b for the detected image signal 50d and the defect candidate or the defect is extracted. Then, the first statistical information 10a obtained from the first statistical information generation circuit 17a is input to the comparison parameter setting means 47a of the first comparator 18a, and the second statistical information 10b obtained from the second statistical information generation circuit 17b. The statistical information 10b is input to the comparison parameter setting means 47b of the second comparator 18b. In the case of this embodiment, the first and second comparators 18a and 18b compare detected image signals with each other to extract a difference image, and extract defect candidates or defects from the extracted difference image. The first statistical information 10a obtained from the first statistical information generation circuit 17a and the second statistical information 10b obtained from the second statistical information generation circuit 17b are respectively used as determination criteria (comparison parameters). .
[0058]
By the way, as the determination criterion (comparison parameter) in the first comparator 18a, the first statistical information 10a obtained from the first statistical information generation circuit 17a is, for example, a standard deviation σ (i, j) indicating variation or the maximum The difference R (i, j) between the value and the minimum value is used, and is the second statistical information 10b obtained from the second statistical information generation circuit 17b as a determination criterion (comparison parameter) in the second comparator 18b. For example, a standard deviation σ ′ (i, j) indicating variation and a difference R ′ (i, j) between the maximum value and the minimum value are used, and a pattern having grain or surface roughness on the surface exists in the surface layer in the multilayer pattern. Even if there is a large variation in the density detection image 9 obtained from this pattern, depending on whether it exists in the lower layer or not, there is a change in the quality of the pattern due to variations in process conditions. As well, it is possible to realize the extraction of defect determination or defect candidates in high reliability in the first and second comparators 18a and 18b. The arithmetic processing in the CPU 19 is the same as that in the embodiment shown in FIG.
[0059]
In addition, as in the case of the illumination condition described below, it is also possible to inspect a plurality of times with various comparison parameters and take a logical sum of the results of the plurality of inspections to obtain a final result.
[0060]
As described above, the statistical information generated by the statistical information generation circuits 17a and 17b can be used in various forms.
Statistical information or statistical images are based on, for example, reference or standard detection images, setting of comparison parameters, parameters for detailed analysis, parameters for quantifying the pattern quality, within wafer, lot unit and wafer type It can be used as an indicator of changes.
In the embodiment described above, bright field illumination is adopted as illumination. However, the present invention is not limited to this, and any illumination that can be used as microscope illumination such as dark field illumination or annular illumination may be used. Needless to say, it can also be applied to illumination with an electron beam.
However, for example, the pattern edge is observed dark in bright field illumination but brightly observed in dark field illumination, and thus there are differences in appearance, so that recognition is different in the statistical image. Therefore, what is mainly compared depends on the illumination.
Various changes may be made to these illumination conditions, and inspection may be performed a plurality of times, and a logical sum of these inspection results may be obtained as a final result. Alternatively, a logical product may be taken and identified as a defect, and the process diagnosis may be made based on the defect distribution and the number of defects, for example. In this case, the review for visually confirming the inconsistent portion is unnecessary, and the work can be simplified and simplified.
[0061]
Next, the operation of the inspection apparatus having the above configuration will be described. That is, in FIG. 1, the stage 5 is scanned with illumination light converged by the objective lens 6 to move the target area of the semiconductor wafer 4 of the pattern to be inspected on the semiconductor wafer 4 by the image sensor 1. , That is, brightness information (grayscale image signal) of the memory mat portion 21 and the peripheral circuit portion 22 in the chip 20 is detected. And it moves at high speed between the said object area | region and the said object area | region.
That is, the inspection is performed repeatedly between constant speed movement and high speed movement. Of course, step-and-repeat inspection is also acceptable. The A / D converter 2 converts the output (grayscale image signal) of the image sensor 1 into a digital image signal 9. The digital image signal 9 has a 10-bit configuration.
Next, statistical information such as a statistical image in the memory mat unit 21 is generated by the first statistical image generation circuit 17a with respect to the digital image signal 9 or the signal 41 indicating the edge of the pattern. The first comparator 18a extracts a defect or defect candidate signal (data) indicated by a feature value in the memory mat unit 21. Further, statistical information such as a statistical image in the peripheral circuit unit 22 is generated by the second statistical image generation circuit 17b for the digital image signal 9 or the signal 41 indicating the edge of the pattern. The second comparator 18b extracts a defect or defect candidate signal (data) indicated by the feature value in the peripheral circuit section 22. The CPU 19 calculates the true defect information by performing detailed analysis on the basis of the defect or defect candidate signal (data) extracted by the first and second comparators 18a and 18b. Based on statistical information such as statistical images obtained from the statistical image generation circuits 17a and 17b, the degree of pattern completion is quantified and grasped. As a result, the CPU 19 can obtain true defect information and information obtained by quantifying the pattern quality.
[0062]
Further, the CPU 19 can output the statistical image itself and associate it with the process, or correlate this with the electrical characteristic data of the element, which can be used for improving the process.
Here, the electrical characteristic data refers to the access time or the like of the memory element, and can be used for improving the process by correlating the statistical image with the quality data of the electrical characteristic result. Here, for example, the standard deviation of the position of the edge of the pattern represents the variation of the edge of the pattern, and can be used as a state monitor of the exposure apparatus or the etching apparatus. By examining which layer has a large pattern edge variation using the design data, it is possible to identify the process apparatus related to the specific layer.
[0063]
The pattern inspection apparatus according to the present invention has delay memories (image storage memories) 23a to 23d as shown in FIGS. 1, 7, and 17, and the cut-out circuit 25 is driven by the cut-out signal 24 in the CPU 19. As a result, one or both of the two images used to extract the defect or defect candidate indicated by the feature amount are cut out and input simultaneously with the defect or defect candidate extraction, and stored. It is also possible to obtain detailed information such as the defect size and the brightness of the defect indicated by the feature amount other than the presence or absence of the defect or defect candidate using the obtained image. Specifically, the stored image data is read out by the CPU 19 during or after the inspection, and image analysis is performed on the CPU 19. The image analysis in the CPU 19 is performed by using a feature amount (brightness based on a density difference image) based on a difference image (mismatch) between a statistical image indicating a normal portion obtained from the first and second comparison circuits 18a and 18b and a detected image having a defect portion. Mismatch amount, two-dimensional non-matching area binarized on the difference image, its shape (eg, circularity, length), brightness of the defective part relative to the normal part, brightness inside the mismatch A wide variety of detailed analyzes can be performed on the extraction of the variation of Further, the CPU 19 evaluates the state of the pattern of the normal portion corresponding to the mismatch (defect or defect candidate indicated by the feature amount), that is, evaluates the shape and appearance of the pattern, and takes correspondence with the appearance of the pattern of the defective portion. Thus, it is possible to grasp the influence of the defect on the pattern. For example, in a detection image having a defect portion cut out by the cutting circuit 25, if the edge of the pattern is seen in the same manner as the statistical image that is a normal portion cut out by the cutting circuit 25, a defect with a changed film thickness (water Mark). For example, in a detection image having a defect portion cut out by the cut-out circuit 25, if there is no pattern edge, it can be determined as a shape defect (such as defective etching) such as damage to the pattern itself. Therefore, the CPU 19 can classify defects. Of course, it may be classified according to pattern features and defect features using a technique such as a neural network. Furthermore, the position where the defect has occurred can also be determined from the shape of the pattern. For example, even if there is no cell position coordinate information, it is possible to distinguish whether a defect has occurred in the mat or not by evaluating the repeatability of the pattern. Here, both the defect image and the corresponding normal image can be stored in the memory at the same time during the inspection, so that the analysis can be performed more effectively.
[0064]
Further, it can be used for setting the comparison parameters in the first and second comparison circuits 18a and 18b and for determining the conditions such as the determination of the analysis parameters when the CPU 19 performs the analysis. That is, the first and second comparison circuits 18a and 18b obtain a difference image (absolute value) by comparing the grayscale average value images 10a and 10b in the statistical image with the grayscale detection images 11a and 11b. On the other hand, the defect or defect candidate is extracted on the basis of the defect or defect candidate extraction margin (comparison parameter) set according to the difference between the gray standard deviation or the maximum gray value and the minimum gray value of the statistical image. Based on the extracted result, it is determined whether or not the defect or defect candidate extraction margin (comparison parameter) is appropriate. If not, the input means 12 or the like is used to extract the defect or defect candidate. By correcting (comparison parameter), an appropriate margin or defect candidate extraction margin (comparison parameter) for the wafer is obtained.
This method is particularly effective for setting the conditions of the optical system. The σ value that is the illumination condition of the optical system, the degree of diffusion, the illumination wavelength, the magnification, etc. are changed, and the statistical image obtained from the first and second statistical information generation circuits 17a, 17b obtained in accordance with these changes. Extraction result of defect or defect candidate obtained based on margin (comparison parameter) set for difference image obtained by change or comparison between statistical image and detection image from first and second comparison circuits 18a, 18b The CPU 19 can evaluate and analyze the optimal optical system conditions.
[0065]
A specific embodiment of an optical system for detecting an optical image of a pattern on the wafer 4 is shown in FIG. 21 (plan view), FIG. 22 (front view), and FIG. In these drawings, an objective lens 209 (6) having an infinity correction system is used, and a second objective lens (also referred to as a tube lens) 303 having a long focal length (for example, f = 200 mm) is also used. The ring-shaped illumination (bright field illumination) nilia image sensor 212a and dark field illumination linear image sensor 308 corresponding to the image sensor 1 are configured by a TDI (Time Delay Integration) time delay integration type image sensor. In this configuration, a polarizing beam splitter PBS (Polarization Beam Spritter) 208 a and a λ / 4 plate (¼ wavelength plate) 251 are installed between the objective lens 209 and the second objective lens 303. Since the parallel light is present between the objective lens 209 and the second objective lens 303, insertion of these elements does not cause deterioration of aberration. The utility of the polarizing beam splitter PBS 208a and the λ / 4 plate (¼ wavelength plate) 251 is as shown in FIG. 23, and the wafer 4 is irradiated with circularly polarized light or elliptically polarized light 334 via the objective lens 209. The reflected light from the wafer 4 reaches the λ / 4 plate, becomes P-polarized light 333, passes through the PBS 208a as it is, and reaches the image sensor 212a. In FIG. 21, an annular illumination filter 205 sets the degree of illumination annular zone. The intensity of illumination light is set by the ND filter 214, and the illumination wavelength and diffusivity are set by the color filter or the diffusion plate 316. In this configuration example, two types of lamps can be changed for switching the illumination wavelength. The zoom lens 213 sets an optical magnification. In such a configuration, optimum conditions can be set by the above-described image storage and analysis of the σ value, the degree of diffusion, the illumination wavelength, the magnification, and the like, which are illumination conditions of the optical system.
In the case of an apparatus using an electron beam, which will be described later, the beam diameter, acceleration voltage, etc. of the electron beam can be optimized.
[0066]
Apart from these, it can also be used as an image filing system as shown in FIG. In particular, since the CPU 19 can obtain a desired defect image in the defect memory 141 from the feature amount extraction unit 139 of the first and second comparison circuits 17a and 17b during the inspection, the defect image to the storage device 147 (13) is obtained. Can be filed in real time. That is, the CPU 19 detects, for example, the defect detection images (f (i, j), f ′ (i, j)) 11a and 11b and the statistical images (g (i, j), g ′) cut out by the cutting circuit 25. (I, j)) Since various files such as 10a and 10b can be filed on the database of the storage device 147 (13) via the memory 123 that primarily stores the image data, when an electrical failure of the LSI occurs, the image data It is useful as a failure analysis and yield improvement support system such as failure factor analysis and analysis by searching and confirming and dealing with failure events. By classifying the image data that is compatible with the electrical failure and collating it with the newly generated appearance failure, it can be immediately determined whether the appearance failure causes the electrical failure. Therefore, countermeasures against defects can be implemented simultaneously with the occurrence of defects, which is effective in improving yield. It is convenient for searching if information such as defect dimensions and coordinates is added to the image data. In addition, individual defects may be reviewed after defect detection, the operator may input the defect form and the cause of occurrence, and the input category data may be added to the image data.
[0067]
Further, the CPU 19 drives the cutout circuit 25 with a cutout signal (defect or defect candidate signal) 24, thereby causing a defect within the dimension range designated as the cutout signal (defect or defect candidate signal) 24 as shown in FIG. The user can store an image of a desired defect by instructing the defect as a defect within the designated position range. Specifically, when one or both of the two images used for the defect or defect candidate extraction are stored in the memory 123 simultaneously with the defect or defect candidate extraction, the first and second comparison circuits The defect or defect candidate presence / absence signal 143 obtained from the feature quantity extraction unit 139 of 18a and 18b, the coordinate signal 144 that is one of the feature quantities of the defect or defect candidate, or one of the feature quantities of the defect or defect candidate. A certain dimension signal 145 or an area 146 that is one of the feature quantities of a defect or defect candidate, or any combination is logically combined in the defect signal determination logic 142 and an image is stored based on the necessary signal. Control what to do. Needless to say, these signals are synchronized with the detected image signal.
[0068]
The image filing system described above has a function of transmitting data to the outside. If data transfer to an external database is possible, data can be stored in the database of the entire analysis system for a larger entire line.
Next, the calculation and alignment of the highly accurate displacement amount performed in the alignment circuits 46a and 46b of the first and second comparison circuits 18a and 18b will be described with reference to FIGS. FIG. 8 is a schematic explanatory view of an image alignment method for a pattern to be inspected according to an embodiment of the present invention, and FIG. 9 is a schematic explanatory view of a sampling position relationship between two images of the image alignment method of FIG. The detection of the positional deviation amount can be as follows.
(A) Linear interpolation method (method to minimize the difference in shading)
(B) Quadratic function interpolation method (method for minimizing differential value difference)
(C) Regularized interpolation method (minimum shade difference method with constraint conditions to reduce differential value difference)
In the method (a), the square errors of the light and shade of the two images to be processed are minimized and matched. The method (b) aims at applying linear interpolation to the differential image. The method (c) satisfies the method (a) using the method (b) as a constraint condition, and gives a regularization parameter γ as a weight to the sum of squares of the difference between the differential values. When the parameter γ = 0, the same result as the method (a) is given. Both methods do not require repetitive calculations and can be realized at one time.
[0069]
The (a) linear interpolation method will be described.
Image alignment is performed using the statistical image and the reference image by pixel alignment and sub-pixel alignment as shown in FIG.
The pixel alignment is performed by shifting one of two images to be compared (for example, the detected image fi, j and the statistical image gi, j) in units of pixels (correspondence between the value of each pixel of the reference image and the statistical image). The difference between the pixel values) is calculated, and the amount of positional deviation that minimizes the contrast is obtained. The range of image misregistration detection is, for example, a maximum of ± 3 pixels, and is variable according to the pattern design rules. The two images are aligned by shifting the position of one of the images by the amount of displacement obtained.
[0070]
First, pixel alignment will be described.
Description will be made using the following (Equation 5) described in the frame (A) of FIG.
[0071]
[Equation 5]

[0072]
The pixel alignment positional deviation detection 81 detects Δx and Δy where S (Δx, Δy) in the above equation (5) is min.
However, since the minimum position can be obtained only in units of pixels, it is added as an offset depending on whether the true position is closer to the obtained Δx or Δy.
[0073]
Based on the following formula, 1 is added to Δx, Δy or left as it is.
That is,
If S (1, 0) + S (1, −1) + S (0, −1) is minimum, Δx ++,
If S (-1, 0) + S (-1, -1) + S (0, -1) is minimum,
If S (−1,0) + S (−1,1) + S (0,1) is minimum, Δy ++,
If S (1, 0) + S (1, 1) + S (0, 1) is minimum, Δx ++, Δy ++,
Δx ++ means Δx = Δx + 1.
By aligning the two images delayed in each of the delay memories 82 and 83 in this way, the pixel alignment 84 always shifts the position of one image by the amount of positional deviation obtained from the detected image f. The two images are aligned. That is, the detected image f is always moved to the upper right to obtain a new image f ′, and the movement direction can be specified from one of four types (lower right movement, upper left movement, lower left movement, upper right movement). it can. This leads to hardware simplification.
[0074]
In the sub-pixel alignment, a positional deviation amount smaller than a pixel is obtained, and two images are aligned with high accuracy. Both the pixel unit alignment 84 and the subpixel alignment 88 are performed at once for every 256 lines, for example.
The sub-pixel alignment includes a misalignment detection unit 85, delay memories 86 and 87, and an alignment unit 88.
[0075]
First, the misregistration detection unit 85 will be described using the frame (B) in FIG.
The displacement detector 85 obtains images f ′ and g ′ based on linear interpolation. However, the positional deviation amounts α and β are detected as the positional deviation amounts with the smallest square error of the difference from f ′ and g ′. That is, the norm of positional deviation detection is to match the shades of the two interpolated images.
Next, the alignment unit 88 will be described using the frame (C) in FIG. New images f ′ and g ′ are obtained by interpolating the image by convolution (convolution sum) of S based on the positional deviation amounts α and β with the statistical image f and the reference image g. Symbols with x in the figure indicate convolution.
The relationship between the sampling positions of the original image f and the new image f ′ is shown in FIG. The difference in sampling position corresponds to the positional deviation amounts α and β.
[0076]
The feature of the above method is that the positional shift amounts α and β are obtained so that the shades of the two images to be aligned are well matched in the sense that the square error is minimum. I'm not looking for a value. However, in the comparison after alignment, the difference in light and shade of the normal part can be reduced, which is considered to be a convenient method in the comparison inspection.
In addition, the calculation of the positional deviation amounts α and β can be performed analytically without repeated calculation, and is suitable for hardware implementation.
[0077]
Next, the quadratic function interpolation method of method (b) will be described.
The purpose of this method is to apply linear interpolation to the differential image.
First, a differential interpolation formula of the following formulas (6) and (7) is assumed.
[0078]
[Formula 6]

[0079]
[Expression 7]

[0080]
The positional deviation amounts α and β are obtained so that the values of the differential interpolation equations expressed by the above equations (6) and (7) are minimized.
[0081]
[Equation 8]

[0082]
In the above formula, C shown in the following formula (9), formula (10), and formula (11) ₁ , C ₂ , C _Three Determine.
[0083]
[Equation 9]

[0084]
[Expression 10]

[0085]
[Expression 11]

[0086]
C in the above equation (9), equation (10), and equation (11) ₁ , C ₂ , C _Three Is used, the positional deviation amounts α and β expressed by the equations (12) and (13) are obtained.
[0087]
[Expression 12]

[0088]
[Formula 13]

[0089]
Next, the regularization interpolation method of method (C) will be described.
The positional deviation amounts α and β that minimize the difference in light and shade are obtained under the constraint condition that S expressed by the following equation (14), that is, the difference between the differential values is minimized.
[0090]
[Expression 14]

[0091]
C shown by the following (Expression 15), (Expression 16), (Expression 17), (Expression 18), (Expression 19), and (Expression 20). ₁ , C ₂ , C _Three , C _Four , C _Five , C ₆ Determine.
[0092]
[Expression 15]

[0093]
[Expression 16]

[0094]
[Expression 17]

[0095]
[Expression 18]

[0096]
[Equation 19]

[0097]
[Expression 20]

[0098]
This C ₁ , C ₂ , C _Three , C _Four , C _Five , C ₆ And the regularization parameter is γ, the above equation (14) is expressed by the following equation (21).
[0099]
[Expression 21]

[0100]
Α and β shown by the following (Equation 22) and (Equation 23) are obtained from this (Equation 21).
[0101]
[Expression 22]

[0102]
[Expression 23]

[0103]
In the above equation, when the regularization parameter γ is set to 0, it matches the conventional linear interpolation.
[0104]
In addition, the following method can be considered as a method of alignment of subpixel alignment.
(A) 'Linear interpolation method (method for minimizing shading)
(B) 'Bilinear interpolation method
(C) 'Secondary function interpolation method
(D) 'Third-order convolution method (spline interpolation) method
(A) ′ A new image f′ij expressed by the equation (Equation 24A) based on the linear interpolation method is based on the positional deviation amounts α and β and Sij expressed by the following equation (Equation 24B) and the original image. It can be obtained by convolution with fij.
[0105]
[Expression 24]

[0106]
Similarly, new images g′i + Δx and j + Δy expressed by the formula (25A) are based on the positional shift amounts α and β, and S′ij expressed by the following formula (25B). And the original image gi + Δx, j + Δy can be obtained by convolution.
[0107]
[Expression 25]

[0108]
Also, a new image f′ij represented by (Equation 26A) using the (b) ′ bilinear interpolation method is based on Sij represented by the following equation (Equation 26B) based on the positional shift amounts α and β. And the original image fij.
[0109]
[Equation 26]

[0110]
Similarly, new images g′i + Δx and j + Δy expressed by the equation (27A) are based on the positional shift amounts α and β, and S′ij expressed by the following equation (27B). And the original image gi + Δx, j + Δy can be obtained by convolution.
[0111]
[Expression 27]

[0112]
(C) 'A quadratic function interpolation method is obtained by differentiating the following equations (Equation 28) and (Equation 29).
[0113]
[Expression 28]

[0114]
[Expression 29]

[0115]
When the above equation is expressed by 4 × 4 convolution, it is expressed by the following Equation (30) and Equation (31).
[0116]
[30]

[0117]
[31]

[0118]
(D) 'In the cubic convolution method (spline interpolation) method, a new image f'ij is expressed by the following equation (32A), and the displacements α and β are expressed by equation (32). And the original image fij.
[0119]
[Expression 32]

[0120]
In the equation (32B), h (t) = sin (πt) / πt is set, and when developed by an approximate equation, h (t) is expressed by the following equation (33).
[0121]
[Expression 33]

[0122]
Further, in the formula (32B), x ₁ = 1 + α, x ₂ = Α, x _Three = 1−α, x _Four = 2−α, y ₁ = 1 + β, y ₂ = Β, y _Three = 1-β, y _Four = 2-β.
Similarly, new images g′i + Δx and j + Δy expressed by the equation (34A) are based on the positional shift amounts α and β, and S′ij expressed by the following equation (34B). And the original image gi + Δx, j + Δy can be obtained by convolution.
[0123]
[Expression 34]

[0124]
Where x ₁ = 1 + (1-α), x ₂ = (1−α), x _Three = 1− (1−α), x _Four = 2- (1-α), y ₁ = 1 + (1-β), y ₂ = 1-β, y _Three = 1- (1-β), y _Four = 2- (1-β).
Among these methods, the (d) ′ cubic convolution method (spline interpolation) method has the least smoothing effect and is considered to have no directionality. Here, it is realized by convolution of 4 × 4 pixels so that both methods can be used together. Examples of convolution weights are shown in Equations (35) and (36).
[0125]
[Expression 35]

[0126]
[Expression 36]

[0127]
However, these alignments are particularly necessary for chip comparison, and a fixed amount of deviation correction may be used for cell comparison.
[0128]
In any case, in the image alignment, the position shift detection is performed by linearly interpolating the images or linearly interpolating the differential images so that the amount of inconsistency between the interpolated images or the linear combination of the inconsistencies is minimized. The image shift amount is obtained with a resolution less than a pixel, and alignment can be obtained by linear interpolation or convolution interpolation of the image based on the detected position shift amount. As a result, the images can be aligned with extremely high accuracy, and the purpose intended by the present invention can be realized with higher sensitivity.
In the above-described embodiment, in one or a plurality of image registration methods including image misregistration detection and registration, misregistration detection is performed by linear interpolation for each image or linear interpolation for a differential image of each image. The deviation amount calculation data using the images should be obtained by the wiring logic so that the respective inconsistency amounts between the interpolation images or the linear combination of the mismatch amounts are minimized, and should be calculated from the deviation amount calculation data. It is also possible to determine the amount of deviation by program logic with a resolution of less than a unit of pixels, and to perform the alignment by linear logic, quadratic interpolation, or convolution interpolation based on the amount of positional deviation. For example, in the equation (8), a statistic ΣC2C3 is obtained by hardware, that is, a wiring logic. Thereafter, α and the like are obtained by program logic. At this time, error processing and the like can be performed flexibly when α is determined.
[0129]
In addition, the position shift detection is performed by linearly interpolating each image or linearly interpolating the differential image of each image, and using the image so that the amount of inconsistency between these interpolated images or the linear combination of the amount of inconsistency is minimized. The deviation amount calculation data is obtained by wiring logic, the deviation amount to be calculated from the deviation amount calculation data is obtained by program logic with a resolution of less than a pixel unit, and the alignment is performed based on the positional deviation amount. It is also possible to carry out the wiring logic by a convolution operation as shown in FIG. In the embodiment described above, the image alignment can be realized by a convolution operation as shown in the equations (Equation 24A), (Equation 26A), and (Equation 32A).
In addition, by applying these and displaying the distortion for each image, when the stage traveling state and the electron beam are scanned, the apparatus state such as the scanning state can be monitored.
In the above embodiment, the case of outputting from the first statistical image generation circuit 17a and the second statistical image generation circuit 17b in an 8-bit configuration has been described, but it may be output in a 10-bit configuration.
[0130]
In addition, in the method of detecting and comparing images continuously, one image can be obtained continuously, but the other image is not used during pixel alignment performed for each segmented area (for example, 256 × 256 pixels). May be continuous. FIG. 16 shows an example of the cause. Image distortion due to various causes such as inaccurate detection of misalignment due to low pattern density and lack of pattern information, optical system vibration, stage system vibration, and charging in the case of electron beams Occurs and the image becomes discontinuous. When discontinuous, the image boundary of the subdivided region becomes an indefinite value by subsequent image processing such as sub-pixel alignment, pixel interpolation, and differentiation. For this reason, mismatch occurs in the comparison, and erroneous detection occurs. If the images are continuous, there will be no discrepancy even if differentiation is performed. Also, if only conventional pixel unit comparison is performed after pixel alignment, no mismatch will occur.
Also, a method of performing pixel interpolation or differentiation in a larger range than the subdivided area and comparing normal values in the subdivided area is conceivable, but this leads to an increase in circuit scale.
[0131]
To solve this,
1) Detect whether the image is discontinuous
2) If it is discontinuous, decrease the sensitivity before and after the boundary (boundary part)
3) Or, if it is discontinuous, the area before and after the boundary is a non-inspection area
4) Or always reduce sensitivity before and after the boundary
5) Or always, before and after the boundary, non-inspection area
6) For sensitivity reduction, a binary image reduction (shrink) process is performed by binarizing the difference between two images.
7) Or the sensitivity is lowered by increasing the binarization threshold value of the difference in density.
Etc.
[0132]
The above 1) checks whether or not Δx, Δy (Δx, Δy) where S (Δx, Δy) in the equation (5) is the same value between pixels. To do. Further, it is checked whether or not the following offset is the same value.
Based on the following formula, 1 is added to Δx, Δy or left as it is.
That is,
If S (1, 0) + S (1, −1) + S (0, −1) is minimum, Δx ++,
If S (-1, 0) + S (-1, -1) + S (0, -1) is minimum,
If S (−1,0) + S (−1,1) + S (0,1) is minimum, Δy ++,
If S (1, 0) + S (1, 1) + S (0, 1) is minimum, Δx ++, Δy ++,
Δx ++ means Δx = Δx + 1.
Actually, it is checked whether the values after adding the offsets x and y to Δx and Δy are the same between the images.
[0133]
Next, the above-described sub-pixel alignment is performed in which the positional deviation amount smaller than the pixel is obtained for the aligned images, and the two images are aligned with high accuracy. When the image is discontinuous, the value of the pixel at the boundary of the image becomes indeterminate and adversely affects subsequent processing. For example, when differentiation is performed after sub-pixel alignment and the differential values are compared, the differential value has an abnormal value at a boundary pixel. What is uncertain for one boundary after sub-pixel alignment becomes so uncertain at two boundaries after primary differentiation that it has an adverse effect on defect detection. In various filters such as Sobel, the boundary is indefinite. For this reason, an abnormal boundary is determined according to the subsequent processing, and erroneous detection occurring at this boundary is prevented. For this, the above 2) to 7) are carried out.
Of course, if the differentiation process is performed before the alignment and the defect determination is only the comparison of the corresponding pixels, there is no erroneous detection at the boundary even if the image is discontinuous. However, usually, various processes are performed after alignment in terms of circuit scale, and boundary processing is necessary.
From the above, it is necessary to minimize the image boundary. This is determined so that the amount of data does not become enormous at the time of alignment by taking a large image within a range in which the distortion of one image can be tolerated.
[0134]
In addition, with respect to an image detected using an electron beam, it is possible to perform alignment of a plurality of images directly or using a plurality of past images, as well as a plurality of past images. This is shown in FIG. In FIG. 15, 27 is a delay memory, 28 is an edge position extraction circuit composed of a differentiation circuit, 29 is a binarization circuit, 30 is a mismatch detection circuit, 31 is a delay circuit, 32 is an alignment circuit, and 33 is a defect determination. Reference numeral 34 denotes a state memory circuit, and 35 denotes an alignment and sensitivity control circuit. The state detection circuit stores the alignment state of the image temporally before the target image, that is, the state such as the number of inconsistent pixels between the images and the amount of misalignment. Is used for alignment. Thereby, when there is no pattern information in the image of interest and it is considered that the alignment accuracy is insufficient, the alignment accuracy can be ensured. In this embodiment, the edge position extraction circuit 28 and the binarization circuit 29 are used to indicate the edge position of the pattern as a binarized image signal. However, as indicated by the chain line, the A / D converter 2 It goes without saying that the directly obtained digital grayscale image signal may be used as it is.
[0135]
FIG. 17 shows an embodiment of boundary processing. In the figure, (a) is an image (here, two consecutive difference images), (b) is a boundary signal (three pixels before and after the boundary), and (c) and (d) are types of reduction filters (two types). ) And the timing of application. The reduction filter A outputs a discrepancy greater than or equal to this size with respect to the binarized image of the difference image targeting an area other than the boundary. Specifically, an AND of these 2 × 2 pixels is obtained for the binarized image. Similarly, the reduction filter B outputs a discrepancy greater than or equal to this size with respect to the binarized image of the difference image for the boundary area. Here, the size of the reduction filter B is made larger than that of the reduction filter A, thereby reducing the sensitivity of the boundary portion. Of course, if the image is not discontinuous, the reduction filter B may be the same as the reduction filter A, or any of them can be eliminated. The processing shown in FIG. 17 is performed inside the defect determination circuit 33 (CPU 48).
[0136]
FIG. 18 shows an embodiment of the defect determination circuit 33. In the figure, the difference between the aligned images is detected, binarized, passed through a filter, and finally the mismatched features (coordinates, dimensions, area, etc.) are calculated. Reference numeral 136 denotes a difference detection circuit, 137 denotes a binarization circuit, 138 denotes a filter circuit that can execute either the filter A or the filter B, and 139 denotes a feature amount extraction (mismatch coordinates, dimensions, area, etc.) circuit. Further, it has a defect or defect candidate determination circuit that determines a feature amount extracted by the feature amount extraction circuit 139 based on a comparison parameter that is a determination criterion.
Here, the binarization threshold Vth may be a set value, or may be controlled by the alignment and boundary sensitivity control circuit 35. That is, as described above, the sensitivity reduction may be performed by increasing the binarization threshold value of the grayscale difference at the boundary portion in synchronization with the boundary signal. The signal input from 138 and from the boundary sensitivity control circuit 35 is a filter selection signal.
[0137]
Furthermore, according to this configuration, in synchronization with the boundary signal, the threshold value is set to 255, for example (maximum value in the case of 8-bit gradation) in the boundary portion, and the boundary portion is It can also be a non-inspection area.
Note that here, the values of the image are uncertain even at both ends of the image corresponding to both ends of the image sensor. However, this can prevent erroneous detection by masking or not using both ends of the image as usual.
[0138]
[Embodiment 2]
Further, in [Embodiment 1 of the invention] shown in FIG. 1, the defect inspection image processing apparatus for the pattern to be inspected, that is, each device from the A / D converter 2 to the CPU 19, the stage 5, the objective lens 6. Although the case where it applied to the apparatus comprised from the optical microscope system which consists of the illumination light source 7, the half mirror 8, and the image sensor 1 was demonstrated, it cannot be overemphasized that it can apply also to a scanning electron microscope system.
However, when the defect inspection image processing apparatus for a pattern to be inspected according to the present invention, that is, the A / D converter 2 to the CPU 19 shown in FIG. 1 are applied to a scanning electron microscope system, instead of the image sensor 1, It is composed of a detector such as a scintillator.
[0139]
A case where the present invention is applied to a scanning electron microscope will be described with reference to FIG. FIG. 10 is a schematic explanatory view of a defect inspection apparatus for a pattern to be inspected according to another embodiment of the present invention. FIG. 10 is a schematic explanatory view of an electron optical system when a scanning electron microscope is used in a defect inspection image processing apparatus for a pattern to be inspected.
In FIG. 10, 101 is an electron source that emits an electron beam, 102 is an electron beam emitted from the electron source, 103 and 104 are electrodes that form an objective lens that focuses the electron beam, and 105 is a deflector that deflects the electron beam. , 106 is a wafer having a pattern to be inspected, 108 is a secondary electron emitted from the wafer, 109 is a secondary electron detector, and 110 is a display / control device for controlling each device constituting the apparatus.
As shown in FIG. 10, an electron beam 102 emitted from an electron source 101 is focused on a wafer 106 as a sample by an objective lens composed of two electrodes 103 and 104. Of the two electrodes 103 and 104 constituting the objective lens, the voltage of the first electrode 103 located on the electron source 101 side is positive with respect to the second electrode 104 at the ground potential located on the wafer 106 side. By adjusting this voltage and adjusting the electric field between the first electrode 103 and the second electrode 104, the lens action of the objective lens is adjusted. Thereby, the lens main surface of the objective lens is formed on the lower side of the second electrode 104.
[0140]
Further, the electron beam 102 is surrounded by the first electrode 103 and is deflected by the electrostatic or magnetic deflector 105 in a space maintained at the same potential as the first electrode 103. , The wafer 106 is scanned two-dimensionally.
[0141]
Secondary electrons or reflected electrons generated from the wafer 106 by the irradiation of the electron beam 102 are two sets of secondary electron detectors or reflections arranged in a plane perpendicular to the tilt axis at a symmetrical position of the electron beam 102. An image of the wafer 106 is obtained on the display unit in the display control device 110 using this detection signal as a video signal.
The above configuration is the same as the charged particle beam observation apparatus described in Japanese Patent Laid-Open No. 4-51441 by the present inventors.
Here, in the case of an electrostatic objective lens, it is not necessary to wind an exciting coil as in the case of a magnetic lens, so that the lens itself can be reduced in size. For example, the size of a conventional magnetic lens has a diameter of 100 to 150 mm, whereas the electrostatic objective lens can have a diameter of 10 mm or less.
However, when the present invention is applied to the scanning electron microscope in this way, it is necessary to cope with the problem that image distortion or the like is likely to occur in the image detection process.
Therefore, even when a small set of repetitive patterns such as the memory mat portion 21 is targeted, it is important to reliably perform image alignment.
[0142]
Therefore, as shown in FIG. 10, a new backscattered electron detector 111, here an annular type, is provided, the backscattered electrons and the secondary electrons are separately detected, and a plurality of image positions are detected using the images detected by the backscattered electrons. Can be combined. Here, it can be said that the image by the reflected electrons is hardly affected by the charge-up of the pattern by the primary electrons, and is an image obtained by treating it as if it were light. The backscattered electron detector is an annular type which has good symmetry and is suitable for inspection of various patterns. Of course, any shape may be used.
Further, when images are continuously detected using an electron beam, image distortion can be further reduced by using an image of a repetitive pattern in the scanning direction of the electron beam for a plurality of repetitive patterns of the mat portion. is there.
In addition, the embodiment shown in FIG. 1 and the electron beam detector shown in FIG. 10 are combined to detect a defect using an image detected using light, in this case, the defect coordinates are calculated, and the image is detected using an electron beam. It is also possible to obtain detailed information on defects based on the feature amount of defects other than the presence or absence of defects (for example, the dimension of the defect or the brightness of the background of the defect) by using the peripheral image including the defect portion. Is useful for high-precision inspection.
[0143]
In the embodiment of the present invention, when obtaining a statistical image, gradation conversion by image histogram conversion or the like is not performed, but histogram equalization or the like may be performed as preprocessing. This is effective for measures such as charge-up by an electron beam.
[0144]
According to the embodiment of the present invention, it is possible to detect a defect with high sensitivity without being affected by the difference in brightness of the pattern depending on the location. Therefore, a dark region such as the memory mat portion 21 can be inspected with high sensitivity, and even in a pattern in which the brightness of the inside thereof varies greatly, it can be inspected with high sensitivity.
Also, the peripheral circuit unit 22 and the like can be optimally inspected. Moreover, it is effective not only to detect the difference in light and dark of the images, but also to compare various pieces of information in the images in an extremely accurate form. Therefore, a highly reliable inspection can be realized as compared with the conventional case.
Further, even if the image is distorted, the image can be aligned with high accuracy, and the same effect can be expected when the pattern density is low.
As described above, the embodiment of the present invention has been described with respect to image statistical image generation based on image detection mainly using an optical microscope or a scanning electron microscope, and a comparative inspection method. Needless to say, it is also effective when used for image detection.
[0145]
[Embodiment 3]
Next, with reference to FIG. 11, an application of analyzing the cause of defect occurrence in the semiconductor manufacturing process of the present invention will be described. FIG. 11 is an application diagram of the image processing apparatus according to the present invention to a semiconductor manufacturing process.
In the present embodiment, a pattern based on comparison results from the first comparison circuit 18a and the second comparison circuit 18b, feature amount information 51 output from the CPU 19, defect (including foreign matter) information 57a, and statistical information. Next, a description will be given of producing good semiconductor chips at a high yield by inputting the information 57b of the completed condition, analyzing the cause of the defect in the semiconductor manufacturing process, and removing the cause of the analyzed defect.
In FIG. 11, 380 is a semiconductor manufacturing line, 381 is a transfer path for the semiconductor wafer 4a, 382 is a CVD apparatus for executing a CVD film forming process for forming an insulating film in the semiconductor manufacturing process, and 383 is a semiconductor manufacturing process. , A sputtering apparatus for performing a sputtering process for forming a wiring film; 384, an exposure apparatus for performing an exposure process for performing resist coating, exposure, development, etc. in a semiconductor manufacturing process; 385, patterning in a semiconductor manufacturing process. An etching apparatus that performs an etching process, and thus a semiconductor wafer is manufactured through various manufacturing processes.
[0146]
Reference numeral 391 denotes an interface for inputting feature amount information 51 obtained from the comparison circuit 18 and the CPU 19, defect information 57a, and pattern completion information 57b based on statistical information; 392, a CPU for executing processing such as analysis; Is a memory storing a program such as analysis, 394, 395, 396, 397 is a control circuit, 398 is an output device such as a printing device that outputs an analysis result such as the cause of a defect, 399 is a display device that displays various data, 400 is a bus line for transferring data between devices, 401 is an input device composed of a keyboard, a disk, etc. 402 is a cause of a defect or a defect that causes a defect that is not shown but cannot be obtained from an inspection image processing apparatus An external storage device for storing causal history data or a database with factors, 403 includes information 41 The interface provided to the production line, 410 is information for controlling the information and manufacturing process conditions on the defective cause or defect factors were analyzed.
Reference numeral 390 denotes a pattern based on the feature amount information 51 output from the devices shown in the comparators 18a and 18b and the CPU 19 (see FIG. 1), defect (including foreign matter) information 57a, and statistical information. This information computer 57b is input to analyze the control information for controlling the cause of defect occurrence or the cause of defect occurrence and the manufacturing process conditions in the production line 380.
The production line 380 includes process devices 382, 383, 384, and 385 for producing semiconductors.
[0147]
The analysis computer 390 includes an interface 391 for inputting feature information 51, defect information 57a output from the comparators 18a and 18b (not shown) and the CPU 19, and information 57b on the pattern quality based on statistical information, CPU 392 that executes processing, memory 393 that stores an analysis program, control circuits 394, 395, 396, and 397, analysis results such as the cause of defects, and control information that is analyzed to control manufacturing process conditions An output device 398 such as a printing device for outputting; a display device 399 for displaying various data; an input device 401 for inputting data relating to the production line 380, data relating to the semiconductor wafer 4a flowing through the production line 380, and the like; The defect that occurred on the wafer 4a and the cause of the defect Is the history data or database of the causal relationship with the defect occurrence factor, the external storage device 402 storing the history data or database of the correspondence relationship between the performance of the pattern and the manufacturing process conditions, and the cause of the defect occurrence analyzed by the CPU 392 or It comprises an interface 403 that provides information related to the cause of defects and information 410 for controlling manufacturing process conditions to the manufacturing line 380 and a bus line 400 that connects them.
[0148]
Therefore, the CPU 392 in the analysis computer 390 generates the pattern quality information 57b based on the input feature amount information 51, defect information 57a, and statistical information, and the semiconductor wafer 4a stored in the external storage device 402. Causal history data or database and pattern results of each defect and the cause of the defect that caused the defect in the production line 380 including the process devices 382, 383, 384, and 385, and the results of the pattern and each process device Based on the history data or database of the correspondence relationship with the manufacturing process conditions of 382, 383, 384, 385, the cause of the defect or the defect that caused the defect in the manufacturing line 380 composed of each process device 382, 383, 384, 385 Occurrence factors and manufacturing process Control information for controlling the conditions is analyzed, and information regarding the analyzed cause of the defect or the cause of the defect and information 410 for controlling the manufacturing process condition are provided to each of the process devices 382, 383, 384, and 385. .
[0149]
Each process apparatus 382, 383, 384, 385 provided with information 410 for controlling the cause of the defect or the cause of the defect and the manufacturing process condition controls the various process conditions including the cleaning to generate the defect. The non-defective semiconductor wafer 4a can be sent to the next factory by removing the cause or the cause of the defect. As a result, a semiconductor can be manufactured with a high yield. The semiconductor wafer 4a to be subjected to defect inspection is sampled in units of the semiconductor wafer 4a or lots from the preceding and following processes where defects are likely to occur in the production line 380.
Further, the CPU 392 in the analysis computer 390 is detected by, for example, a dedicated foreign matter inspection apparatus (not shown) (the inspection pattern inspection apparatus shown in FIGS. 1 and 7 can also detect foreign matters as defects). In a production line 380 comprising foreign substance information obtained and inputted from the CPU 19 based on the foreign substance signal, foreign substances generated on the semiconductor wafer 1a stored in the external storage device 402, and the respective process devices 382, 383, 384, 385 Generation of foreign matter causing foreign matter in the production line 380 composed of the process devices 382, 383, 384, and 385 based on the history data or database of the cause of foreign matter causing the foreign matter or the causal relationship with the cause of foreign matter occurrence Analyze the cause or foreign matter generation factor.
[0150]
Information 410 relating to the analyzed cause of foreign matter generation or the cause of foreign matter generation is provided to each process device 382, 383, 384, 385 of the production line 380. Each process apparatus 382, 383, 384, 385 provided with information 410 regarding the cause of foreign matter generation or the cause of foreign matter generation is defective by controlling various process conditions including cleaning to remove the cause of foreign matter generation or the cause of foreign matter generation. A good semiconductor wafer 4a having no defect can be sent to the next process, and as a result, a semiconductor can be manufactured at a high yield.
[0151]
【The invention's effect】
According to the present invention, there is an effect that a pattern to be inspected can be inspected with high sensitivity and high reliability without being affected by the state of the surface of the multilayer inspected pattern in which surface roughness, grain, or the like occurs.
Further, according to the present invention, it is possible to inspect a repeated pattern to be inspected in the mat portion constituting the semiconductor memory with high sensitivity and high reliability without being restricted by the sensitivity of the entire chip. .
Further, according to the present invention, it is possible to inspect a true defect with high reliability by enabling detailed analysis of a defect or the like occurring in a repeated inspection pattern.
[0152]
Moreover, according to this invention, there exists an effect which can grasp | ascertain a quantitative condition about the pattern to be inspected repeatedly.
[0153]
In addition, according to the present invention, a manufacturing process (stepper resolution, etching quality, etc.) for manufacturing a pattern to be inspected by quantitatively grasping the condition of the pattern to be inspected repeatedly is diagnosed, and the result is applied to the manufacturing process. The effect which can be fed back is produced.
Further, according to the present invention, in a semiconductor substrate such as a semiconductor wafer, the pattern to be inspected is highly sensitive and reliable without being affected by the state of the surface of the multilayer inspected pattern in which surface roughness, grain, or the like occurs. There is an effect that a semiconductor substrate having high reliability can be manufactured by inspection.
Further, according to the present invention, it is possible to accurately align one or a plurality of images, and as a result, it is possible to faithfully extract a feature amount such as a defect in a pattern to be inspected that is repeated.
Further, according to the present invention, a pattern to be inspected that is repeated using an electron beam can be inspected with high sensitivity and high reliability without being affected by various errors such as distortion and brightness differences. There is an effect that can be done.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of an inspection pattern inspection apparatus according to the present invention.
2 is a schematic explanatory diagram of a grayscale statistical image in a memory mat portion obtained by the first statistical information generation circuit shown in FIG. 1; FIG.
FIG. 3 is a schematic explanatory diagram of a grayscale statistical image in a peripheral circuit unit obtained by the second statistical information generation circuit shown in FIG. 1;
FIG. 4 is a diagram for explaining that a statistical image of a pattern edge position obtained by the first and second statistical information generation circuits shown in FIG.
5 is a diagram for explaining the relationship of signal waveforms for extracting the edge position of a pattern by the edge position extraction circuit shown in FIG. 1; FIG.
FIG. 6 is a schematic explanatory diagram of matching based on a comparison between a statistical image and a reference image or a detected image.
FIG. 7 is a configuration diagram showing another embodiment of an inspection pattern inspection apparatus according to the present invention.
FIG. 8 is a schematic explanatory diagram of an image alignment method according to the present invention.
FIG. 9 is an explanatory diagram schematically showing a relationship between sampling positions of two images in the image alignment method shown in FIG. 8;
FIG. 10 is a configuration diagram showing still another embodiment of an inspection pattern inspection apparatus according to the present invention.
FIG. 11 is a configuration diagram showing an embodiment of a manufacturing process analysis system according to the present invention.
12 is a schematic explanatory view of a memory mat portion and a peripheral circuit portion in a memory chip having a pattern to be inspected according to the present invention. FIG.
13 is a histogram of brightness in a memory mat portion and a peripheral circuit portion in the memory chip shown in FIG.
14 is a schematic explanatory view of a pattern to be inspected when there is a grain in the memory mat portion shown in FIG.
FIG. 15 is a diagram showing another embodiment of an image alignment circuit.
FIG. 16 is an explanatory diagram of factors that cause discontinuity in an image.
FIG. 17 is a diagram for explaining an embodiment of image boundary processing;
18 is a diagram showing an embodiment of a specific configuration of the CPU in the comparison circuit shown in FIGS. 1 and 7 and the defect determination circuit shown in FIG. 15;
19 is a diagram showing a schematic configuration of another embodiment different from the CPU that performs the detailed analysis shown in FIGS. 1 and 7. FIG.
FIG. 20 stores an image of a desired defect or defect candidate when a user designates a defect or defect candidate within a specified dimension range as a defect or defect candidate signal, or a defect or defect candidate within a specified position range. It is a block diagram which shows one embodiment for doing.
FIG. 21 is a plan view of an embodiment of an optical system for detecting an optical image of a pattern to be inspected.
22 is a front view of FIG. 22. FIG.
23 is a diagram for explaining the relationship of polarization in the optical system shown in FIGS. 21 and 22. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image sensor, 2 ... A / D converter, 3a ... 1st delay memory, 3b ... 1st delay memory, 4, 4a ... Semiconductor wafer, 5 ... X, Y, Z, (theta) stage, 6 ... Objective Lens 7 illuminating light source 8 half mirror 9 digital image signal 10a 10b statistical information (statistical image signal) 11a 11b detected image signal 12 input means 13 storage device 17a first 1 statistical information generation circuit, 17b ... second statistical information generation circuit, 18a ... first comparison circuit, 18b ... second comparison circuit, 19 ... CPU, 20 ... chip, 21 ... memory mat section, 22 ... peripheral Circuit part, 23a to 23d ... Delay memory, 25 ... Extraction circuit, 28 ... Edge position extraction circuit, 29 ... Binarization circuit, 30 ... Mismatch detection circuit, 31 ... Delay circuit, 32 ... Positioning circuit, 33 ... Defect judgment circuit 34 ... State memory circuit 35 ... Positioning and sensitivity control circuit 43a, 43b ... Image memory, 44a, 44b ... CPU, 45a, 45b ... Memory, 46a, 46b ... Positioning circuit, 47a, 47b ... Comparison parameter setting means, 48a, 48b ... CPU, 51a, 51b ... defect or defect candidate signal, 52 ... display means, 57a ... defect information, 57b ... pattern condition information,
DESCRIPTION OF SYMBOLS 101 ... Electron source, 102 ... Electron beam, 103 ... 1st electrode, 104 ... 2nd electrode, 105 ... Deflector, 106 ... Semiconductor wafer, 108 ... Secondary electron, 109 ... Secondary electron detector, 110 ... Display / control device, 111 ... backscattered electron detector,
123 ... Memory, 136 ... Difference detection circuit, 137 ... Binarization circuit, 138 ... Filter circuit, 139 ... Feature quantity extraction circuit, 141 ... Defect memory, 147 ... Storage device,
380... Semiconductor manufacturing line, 381... Transport path of the semiconductor wafer 1 a, 382... CVD apparatus that executes insulating film formation, 383... Sputtering apparatus that forms wiring film, 384. Exposure apparatus that executes exposure process, 385. Etching apparatus for executing an etching process, 391 ... interface, 392 ... CPU for executing processing such as analysis, 393 ... memory storing programs such as analysis, 394, 395, 396, 397 ... control circuit, 398 ... printing apparatus, etc. 399 ... display device for displaying various data, 400 ... bus line for transferring data between the devices, 401 ... input device comprising keyboard, disk, etc. 402 ... external storage device for storing database, 403 ... Interface, 410 ... information on defect occurrence,

Claims (14)

A statistic indicated by a statistic indicating a variation in edge position or a difference between a maximum value and a minimum value at a corresponding position of the pattern to be inspected repeated from the detected image signal. A method for inspecting a pattern to be inspected, comprising generating information and quantifying the degree of completion of the pattern to be inspected using the generated statistical information. An image signal is detected from the repeated pattern to be inspected , and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal A statistical information indicated by a statistic of variation or a difference between a maximum value and a minimum value is generated, and a defect or a defect candidate existing in the inspection pattern is extracted using the generated statistical information. Inspection pattern inspection method. An image signal is detected from the repeated pattern to be inspected , and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal Defects or defect candidates present in the pattern to be inspected by generating statistical information indicated by the statistic of variation or the difference between the maximum and minimum values and comparing the generated statistical information with the detected image signal A method for inspecting a pattern to be inspected, characterized in that: An image signal is detected from the repeated pattern to be inspected , and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal Defects or defect candidates present in the pattern to be inspected by generating statistical information indicated by the statistic of variation or the difference between the maximum and minimum values and comparing the generated statistical information with the detected image signal A method for inspecting a pattern to be inspected, characterized by extracting a feature amount of the pattern. 5. The inspection pattern inspection method according to claim 1, wherein the statistical information is a statistical image signal. An image signal is detected from the repeated pattern to be inspected, and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal The statistical information shown by the statistic of the difference or the difference between the maximum value and the minimum value is generated, and the generated difference image is obtained by comparing the detected image signals of the repeated pattern to be inspected. A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in a pattern to be inspected is extracted by performing a determination process based on a determination criterion obtained based on statistical information . An image signal is detected from the repeated pattern to be inspected, and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal A pattern to be inspected by generating a statistical image signal represented by a statistic of variation or a difference between a maximum value and a minimum value, and aligning and comparing the statistical image signal with the detected image signal as a reference image signal A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in a pattern is extracted . An image signal is detected from the repeated pattern to be inspected, and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal By generating a statistical image signal indicated by a statistic of variation or the difference between the maximum value and the minimum value, and comparing the generated statistical image signal with the detected image signal as a reference image signal for comparison inspection method of an inspection pattern which is characterized by extracting a feature amount of defects or defect candidates of the test pattern. An image signal is detected from the repeated pattern to be inspected, and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal For the difference image obtained by generating statistical information indicated by the statistic of the difference or the difference between the maximum value and the minimum value and aligning and comparing the image signals of the detected repeated patterns to be inspected A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in a pattern to be inspected is extracted by performing a determination process based on a determination criterion obtained based on the generated statistical information . 10. The method for inspecting a pattern to be inspected according to claim 7, wherein the alignment is performed at least on a pixel basis . A statistic indicated by a statistic indicating a variation in edge position or a difference between a maximum value and a minimum value at a corresponding position of the pattern to be inspected repeated from the detected image signal. Appropriateness of the manufacturing process for generating information, quantifying the quality of the pattern to be inspected using the generated statistical information, and manufacturing the pattern to be inspected based on the quality of the quantified pattern to be inspected A method for diagnosing a manufacturing process, characterized by: An image signal is detected from the repeated pattern to be inspected, and the brightness (shading) variation or the difference between the maximum value and the minimum value or the edge position at the corresponding position of the pattern to be inspected repeated from the detected image signal Generate statistical information indicated by the statistic of variation or the difference between the maximum value and the minimum value, and use this generated statistical information to extract defects or defect candidates that exist in the pattern to be inspected. Alternatively, a manufacturing process diagnosing method comprising diagnosing the suitability of a manufacturing process for manufacturing a pattern to be inspected based on defect candidate information . A statistic indicated by a statistic indicating a variation in edge position or a difference between a maximum value and a minimum value at a corresponding position of the pattern to be inspected repeated from the detected image signal. Generate information, quantify the quality of the pattern to be inspected using the generated statistical information, and diagnose the suitability of the manufacturing process conditions of the pattern to be inspected based on the quality of the pattern to be inspected. A method of manufacturing a semiconductor substrate, comprising manufacturing a semiconductor substrate . An image signal is detected from a repeated pattern to be inspected, and a variation in brightness (shading) or a difference between a maximum value and a minimum value or an edge position at a corresponding position of the pattern to be inspected repeated from the detected image signal Generate statistical information indicated by the statistic of variation or the difference between the maximum value and the minimum value, and use this generated statistical information to extract defects or defect candidates that exist in the pattern to be inspected. Alternatively, a semiconductor substrate is manufactured by diagnosing the suitability of a manufacturing process condition of a pattern to be inspected based on defect candidate information, and manufacturing a semiconductor substrate .

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