JPH1074812A - Inspecting method of pattern to be inspected, diagnosing method of manufacturing process and manufacturing method of semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sensitive method of inspecting a pattern to be inspected to detect defects in a semiconductor wafer, and a diagnosing method of the manufacturing process. SOLUTION: Where defects in a pattern to be inspected in which multiple chips 20 formed so as to be identical by this inspection method are arranged are detected, from a set chip 20 in the pattern, an image signal 9 is detected, and a statistic image formed using statistics corresponding to this detection image signal 9 is generated. Then, by using this statistical image as a comparison reference, defects are detected, or by using the statistical image the quality of the pattern is quantified, and the process is diagnosed. By means of the information based on the convolution computing and the multiple images, the images are aligned with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a visual inspection for detecting a defect in a pattern to be inspected, and more particularly to a method for inspecting a pattern to be inspected in a semiconductor wafer, a liquid crystal display or the like. In particular, the present invention relates to a method of diagnosing a manufacturing process optimal for evaluating a manufacturing process and a method of manufacturing a semiconductor substrate such as a semiconductor wafer by utilizing these.

[0002]

2. Description of the Related Art Conventionally, this kind of inspection apparatus is disclosed in
As described in Japanese Patent Application Laid-Open No. 74409/74, while the pattern to be inspected is moved, an image of the pattern to be inspected is detected by an image sensor such as a line sensor, and the density of the image signal delayed by a predetermined time from the detected image signal is detected. By comparing these, the mismatch was recognized as a defect.

[0003]

Incidentally, in a pattern to be inspected such as a semiconductor wafer, the pattern is formed of various materials, and furthermore, is laminated in multiple layers. In such a multilayer pattern, for example, the surface of a certain layer may be rough while the surface is normal. In the above-described conventional inspection method, inspection performance is restricted by such a normal but roughened pattern, and a pattern without surface roughness should be able to be inspected with high sensitivity. In some cases, the sensitivity has to be lowered to match the pattern and the inspection has to be performed. Further, as described above, the sensitivity is lowered due to the surface roughness. However, when a grain is generated in the pattern, the sensitivity is also reduced. In addition, a layer having a rough surface and a layer having a grain do not always appear on the surface, but become a surface layer or a lower layer and are not constant, so that a complicated appearance is obtained. There was a problem that such a problem was not taken into consideration in the above-described conventional technology.

In addition, not only when ordinary light is used but also when an electron beam or the like is used, the distortion of an image is particularly large and the alignment error is large, so that a fine defect cannot be detected. there were. Further, since secondary electrons and the like are unstable, the brightness of the detected image tends to be unstable. As described above, since there is a difference between images even in a normal pattern, there is a problem that erroneous detection is likely to occur. Further, the conventional inspection method is merely a determination of the presence or absence of a defect, and there is a major problem here. In other words, although the resolution of a stepper or the quality of etching is not a defect, it is not suitable for a direct quantitative evaluation of the condition of a pattern which is a problem for a normal part. Was. In other words, conventional methods detect only fatal or easy-to-understand defects or epidermal defects with a face on the surface. In addition, there is a problem that it is not possible to make a quantitative determination. Further, the conventional inspection method cannot directly perform quantitative evaluation as described above, and thus has a problem that it is unsuitable for evaluation of a manufacturing process for manufacturing a semiconductor wafer or the like, for example.

[0005] An object of the present invention is to solve the above problems.
Provided is a method for inspecting a pattern to be inspected, which is capable of inspecting the pattern to be inspected with high sensitivity and high reliability without being affected by the state of the surface of the multilayer pattern to be inspected in which surface roughness, grains, etc. occur. It is in. Another object of the present invention is to provide a method for inspecting a pattern to be inspected, which enables a pattern to be repeatedly inspected in a mat portion constituting a semiconductor memory to be inspected with high sensitivity and high reliability. Another object of the present invention is to provide a method for inspecting a pattern to be inspected, which enables a detailed analysis of a defect or the like occurring in a pattern to be inspected repeatedly so that a true defect can be inspected with high reliability. is there.

It is another object of the present invention to provide a method of inspecting a pattern to be inspected, which enables the quality of the repeated pattern to be inspected to be grasped quantitatively. It is another object of the present invention to provide a manufacturing process diagnosis method capable of diagnosing a manufacturing process for manufacturing a pattern to be inspected by quantitatively grasping the performance of the pattern to be inspected repeatedly. Another object of the present invention is to inspect a pattern to be inspected with high sensitivity and high reliability without being affected by the state of the surface of the multilayer pattern to be inspected, in which surface roughness, grains, etc., occur on a semiconductor substrate. It is an object of the present invention to provide a method of manufacturing a semiconductor substrate, which is capable of manufacturing a semiconductor substrate having high reliability.

It is another object of the present invention to provide a method of aligning an image, which is capable of aligning one or more images with high accuracy. Another object of the present invention is to perform inspection with high sensitivity and high reliability without being affected by various errors such as distortion and differences in brightness for a pattern to be inspected repeated using an electron beam. An object of the present invention is to provide a method of inspecting a pattern to be inspected as described above.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention detects an image signal from a pattern to be inspected repeatedly and indicates the detected image signal by a statistic of the pattern to be inspected repeated from the detected image signal. This is a method for inspecting a pattern to be inspected, characterized by generating statistical information to be inspected and quantifying the degree of completion of the pattern to be inspected using the generated statistical information. Further, the present invention detects an image signal from the repeated pattern to be inspected, generates statistical information indicated by a statistic of the pattern to be inspected repeated from the detected image signal, and uses the generated statistical information. This is a method for inspecting a pattern to be inspected, which comprises extracting a defect or a defect candidate present in the pattern to be inspected. The present invention also provides
Detecting an image signal from the pattern to be inspected repeatedly, generating statistical information indicated by a statistic of the pattern to be inspected repeated from the detected image signal, and generating the generated statistical information and the detected image signal. And extracting a defect or a defect candidate present in the pattern to be inspected by comparing the pattern with the pattern to be inspected.

Further, according to the present invention, an image signal is detected from a repeated pattern to be inspected, and statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal. And comparing the detected image signal with the detected image signal to extract a feature amount of the pattern to be inspected. Further, the present invention is characterized in that a detailed analysis is performed based on the extracted feature amount to grasp a true defect and a state of a pattern to be inspected. Further, according to the invention, in the method for inspecting a pattern to be inspected, the statistical information is a statistical image signal. Further, in the inspection method of the pattern to be inspected, the detected image signal is a grayscale image signal of the pattern to be inspected and the statistical information is a statistical grayscale image signal of the pattern to be inspected repeated as the statistical information. And The present invention also provides the inspection pattern inspection method, wherein the detected image signal is an image signal indicating an edge position of the inspection pattern, and the statistical edge position of the inspection pattern is repeated as the statistical information. A statistical image signal shown in FIG. Further, the present invention detects an image signal from the repeated pattern to be inspected, generates a statistical image signal represented by an average value or a median value of the repeated pattern to be inspected from the detected image signal, and generates the generated statistical image signal. Extracting a defect or a defect candidate (including a case indicated by a feature amount) existing in the pattern to be inspected by comparing the image signal with the detected image signal as a reference image signal; Is the inspection method.

Further, according to the present invention, an image signal is detected from a repeated pattern to be inspected, and a statistical image signal represented by an average value or a median value of the repeated pattern to be inspected is generated from the detected image signal. A method for inspecting a pattern to be inspected, comprising extracting a feature amount of the pattern to be inspected by comparing the statistical image signal obtained as a reference image signal with the detected image signal. Further, the present invention is characterized in that a detailed analysis is performed based on the extracted feature amount to grasp a true defect and a state of a pattern to be inspected. Further, according to the present invention, an image signal is detected from a repetitive pattern to be inspected, and statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal. Extracting a defect or a defect candidate existing in the pattern to be inspected by performing a determination process on a difference image obtained by comparing the image signals of the inspection patterns based on the determination criterion obtained based on the generated statistical information. This is a method for inspecting a pattern to be inspected. Further, according to the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat section and a peripheral circuit section are arranged, and the detected image signal is represented by a statistic of the pattern to be inspected repeated in the mat section. It is characterized in that statistical information is generated, the degree of a pattern to be inspected in the mat portion is quantified using the generated statistical information in the mat portion, and conditions or states of a manufacturing process can be grasped or diagnosed. This is a method of inspecting a pattern to be inspected.

Further, according to the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged, and a statistical amount of the pattern to be inspected repeated in the mat portion is detected from the detected image signal. And statistical information indicated by the statistic of the pattern to be inspected repeated in the peripheral circuit unit are generated, and the state of the pattern to be inspected in the mat unit is determined by using the generated statistical information in the mat unit. Quantifying the degree of the pattern to be inspected in the peripheral circuit portion using the generated statistical information in the peripheral circuit portion, so as to be able to grasp or diagnose the condition and state of the manufacturing process. This is the inspection method of the pattern to be inspected. Further, according to the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat section and a peripheral circuit section are arranged, and the detected image signal is represented by a statistic of the pattern to be inspected repeated in the mat section. It is characterized in that statistical information is generated, and a defect or a defect candidate (including a feature amount) present in the pattern to be inspected in the mat portion is extracted using the generated statistical information in the mat portion. This is the inspection method of the pattern to be inspected.

According to the present invention, an image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged. And the statistical information represented by the statistic of the pattern to be inspected repeated in the peripheral circuit section, and the defect existing in the pattern to be inspected in the mat section is generated by using the generated statistical information in the mat section. Or extract defect candidates,
A defect or a defect candidate (including a case indicated by a feature amount) existing in the pattern to be inspected in the peripheral circuit portion is extracted using the generated statistical information in the peripheral circuit portion. It is an inspection method. Further, the invention is characterized in that the inspection method of the inspection pattern is applied to an inspection pattern in which a plurality of chips formed to be the same are arranged. According to the present invention, in the method for inspecting a pattern to be inspected, a statistical image is generated for each of a mat portion and a peripheral circuit portion. Further, the present invention is characterized in that, in the inspection method of the pattern to be inspected, the comparison between the statistical image and the detected image extracts a feature amount (a mismatch amount or a mismatch item) based on the mismatch (difference). . In the inspection method of the pattern to be inspected, the comparison between the statistical image and the detected image may include detecting a feature amount (a mismatch amount or a mismatch item) based on a difference (mismatch) in a pattern edge position. It is characterized by.

According to the present invention, an image signal is detected from a repeated pattern to be inspected, and statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal. Quantifying the degree of completion of a pattern to be inspected by using the method, and diagnosing the suitability of a manufacturing process for producing the pattern to be inspected based on the degree of completion of the quantified pattern to be inspected. Is the way. Further, the present invention detects an image signal from a repeated pattern to be inspected, generates statistical information indicated by a statistic of the repeated pattern to be inspected from the detected image signal, and uses the generated statistical information. A process for extracting information on a defect or a defect candidate present in the pattern to be inspected and diagnosing the suitability of a manufacturing process for manufacturing the pattern to be inspected based on the extracted information on the defect or the defect candidate. This is a process diagnosis method. Further, according to the present invention, in the manufacturing process diagnosis method, a diagnosis item of the manufacturing process includes a resolution of a pattern, a thickness of the pattern, and clarity of an edge thereof.
It is characterized by at least one.

According to the present invention, an image signal is detected from a semiconductor substrate on which a repetitive pattern to be inspected is formed, and statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal. The quality of the pattern to be inspected is quantified using the generated statistical information, and the semiconductor substrate is manufactured by diagnosing the suitability of the manufacturing process conditions of the pattern to be inspected based on the quality of the quantified pattern to be inspected. A method for manufacturing a semiconductor substrate, characterized in that: Further, the present invention detects an image signal from a semiconductor substrate on which a pattern to be repeated is formed, generates statistical information indicated by a statistic of the pattern to be repeated from the detected image signal, and generates the generated statistical information. The statistical information is used to extract information on defects or defect candidates present in the pattern to be inspected, and based on the information on the extracted defects or defect candidates, a diagnosis is made as to whether or not the manufacturing process conditions of the pattern to be inspected are appropriate. A method of manufacturing a semiconductor substrate characterized by manufacturing. Also, the present invention provides a method of linearly interpolating each image to be registered or linearly interpolating a differential image of each of the images, and performing the interpolation so that the amount of mismatch between these interpolated images or the linear combination of the amounts of mismatch is minimized. Find the amount of image shift with a resolution of less than a pixel,
An image positioning method is characterized in that the images are aligned by performing a linear interpolation, a secondary interpolation or a high-order convolution interpolation on each of the images based on the obtained positional deviation amount.

Further, according to the present invention, each image to be registered is linearly interpolated or a differential image of each of the images is linearly interpolated so that the amount of mismatch between these interpolated images or the linear combination of the amount of mismatch is minimized. The shift amount calculation data using the image is obtained by wiring logic, the shift amount to be calculated from the obtained shift amount calculation data is obtained by the program logic at a resolution of less than a pixel, and the obtained position is calculated. An image positioning method characterized by performing linear interpolation, quadratic interpolation, or higher-order convolution interpolation on each of the images based on the amount of displacement by wiring logic to thereby align the images. The present invention also provides
Each image to be aligned is linearly interpolated or a differential image of each of the images is linearly interpolated, and the amount of mismatch between these interpolated images or the amount of deviation using the images so that the linear combination of the amounts of mismatch is minimized The calculation data is obtained by wiring logic, the shift amount to be calculated from the obtained shift amount calculation data is obtained by the program logic at a resolution of less than a pixel, and the respective images are determined based on the obtained positional shift amount. An image registration method, wherein the image registration is performed by wiring logic based on a convolution operation. Further, the present invention detects an image signal from the pattern to be inspected repeatedly, generates a statistical image signal of the pattern to be inspected repeated from the detected image signal,
The generated statistical image signal is aligned with the detected image signal as a reference image signal and compared with each other to extract a defect or a defect candidate (including a case indicated by a feature amount) existing in the pattern to be inspected. This is a method for inspecting a pattern to be inspected.

Further, according to the present invention, an image signal is detected from a repetitive pattern to be inspected, a statistical image signal of the repetitive pattern to be inspected is generated from the detected image signal, and the generated statistical image signal is used as a reference image. A method for inspecting a pattern to be inspected, comprising extracting a feature amount of the pattern to be inspected by aligning and comparing the detected image signal as a signal. Further, the present invention is characterized in that a detailed analysis is performed based on the extracted feature amount to grasp a true defect and a state of a pattern to be inspected. Further, according to the present invention, an image signal is detected from a repetitive pattern to be inspected, and statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal, and the detected repetitive pattern to be inspected is generated. A defect or defect candidate existing in a pattern to be inspected by performing a determination process based on a determination criterion obtained based on the generated statistical information on a difference image obtained by aligning and comparing image signals of Is a method for inspecting a pattern to be inspected. The present invention is also an inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating an electron beam on a specimen having the pattern to be inspected, the inspection method being generated from the specimen by scanning the electron beam. The reflected electrons and the secondary electrons are separated to selectively detect the reflected electrons,
An inspection method of a pattern to be inspected is characterized in that an electron beam image is created based on the detected reflected electrons, and the pattern to be inspected is inspected using the electron beam image created by the reflected electrons.

The present invention is also an inspection method for inspecting a pattern to be inspected by using an electron beam image obtained by scanning and irradiating a sample having the pattern to be inspected with an electron beam. This is a method for inspecting a pattern to be inspected, characterized by detecting and aligning a plurality of images using images detected by backscattered electrons. The present invention also provides
An inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating an electron beam on a sample on which a pattern to be inspected is repeatedly formed, the inspection method comprising the steps of: This is a method for inspecting a pattern to be inspected, wherein the pattern to be inspected is inspected by using an obtained electron beam image. The present invention also provides
A method for inspecting a pattern to be inspected formed on a sample, comprising: a first inspection step of inspecting the pattern to be inspected based on an optical image detected from the pattern to be inspected; Scanning irradiation to obtain an electron beam image of the periphery including the inspected portion, and obtaining detailed information on the inspected portion based on the electron beam image. This is the inspection method of the pattern to be inspected.

Further, the present invention is a method of continuously detecting image signals for a pattern to be repeatedly inspected and inspecting the pattern to be inspected based on the image signals detected continuously, the method comprising: Inspection of a pattern to be inspected, wherein the continuity of the image is determined using not only the image of interest but also the displacement information of the past image, and the inspection sensitivity at the boundary of the discontinuous image is controlled based on the continuity. Is the way. Further, the present invention is a method for continuously detecting an image signal for a pattern to be repeatedly inspected, and inspecting the pattern to be inspected based on the image signal continuously detected,
The method is characterized in that the continuity of the images is determined by using not only the target image but also the positional deviation information of the past image for the alignment of the plurality of images, and the boundary of the discontinuous image is set as a non-inspection area based on the continuity. This is the inspection method of the pattern to be inspected.

As described above, according to the above configuration,
The inspected pattern can be inspected with high sensitivity and high reliability without being affected by the state of the surface of the multilayer inspected pattern in which surface roughness, grain or the like occurs. Further, according to the above configuration, the pattern to be repeatedly inspected in the mat portion constituting the semiconductor memory can be inspected with high sensitivity and high reliability. Further, according to the above configuration, it is possible to perform a detailed analysis on a defect or the like occurring in the pattern to be inspected repeatedly, so that a true defect can be inspected with high reliability.

Further, according to the above configuration, it is possible to quantitatively grasp the performance of the repeated pattern to be inspected. Further, according to the above configuration, it is possible to quantitatively grasp the quality of the repeated pattern to be inspected and diagnose the manufacturing process of manufacturing the pattern to be inspected.

Further, according to the above configuration, in a semiconductor substrate such as a semiconductor wafer, the pattern to be inspected can be formed with high sensitivity and high sensitivity without being affected by the state of the surface of the multilayer pattern to be inspected in which surface roughness, grain, etc. occur. By inspecting with reliability, a highly reliable semiconductor substrate can be manufactured. Further, according to the above configuration, it is possible to perform positioning with respect to one or a plurality of images with high accuracy. As a result, it is possible to faithfully extract a feature amount such as a defect in the repeated pattern to be inspected. Further, according to the configuration, it is possible to inspect the pattern to be inspected repeatedly using the electron beam with high sensitivity and high reliability without being affected by various errors such as distortion and difference in brightness. it can.

The effects obtained by the present invention will be described in detail from a functional aspect. For example, in a pattern to be inspected in which a plurality of chips each having a memory mat portion and a peripheral circuit portion are arranged, in order to quantitatively express the finished state of each pattern, and to use this to extract a feature amount of a defect or a defect candidate, Inspection of the generated defect or defect candidate with high sensitivity without the inspection sensitivity of the whole chip being restricted by the layer with poor finish of these multi-layer patterns, that is, the layer with surface roughness or grain of the pattern. Can be. Also, by using statistical information that quantitatively expresses the finished state of the pattern, it is possible to determine the quality of each pattern that does not become a defect but is limited as a normal part with respect to the resolution of a stepper or the quality of etching. ,
Quantitative evaluation can be performed accurately and directly. Needless to say, by using this statistical information, it is possible to directly and quantitatively grasp the state of the multi-layer pattern in detail. In addition, the manufacturing process itself can be quantitatively grasped by adopting a statistical image and an inspection method using the statistical image.

[0023]

Embodiments of the present invention will be described with reference to the drawings. First, an embodiment of a pattern to be inspected according to the present invention will be described. FIG. 12 is a diagram schematically illustrating a memory mat portion and a peripheral circuit portion in a semiconductor memory chip formed on a semiconductor wafer as one embodiment of a pattern to be inspected. FIG. FIG. 7 is a diagram showing a histogram of brightness (shade) in a memory mat portion and a peripheral circuit portion in the semiconductor memory chip shown in FIG. FIG. 14 is a schematic view of a pattern to be inspected having grains in the memory mat portion of FIG. FIG.
As shown in FIG.
Are arranged and formed in large numbers. The memory chip 20 can be roughly divided into a memory mat section 21 and a peripheral circuit section 22. The memory mat section 21 is a set of small repeating patterns, and the peripheral circuit section 22 is a set of patterns repeated in one axis direction as shown in FIG. The patterns of both the memory mat portion 21 and the peripheral circuit portion 22 are formed of various materials, and are stacked in multiple layers.

FIG. 13 shows the memory mat unit 21 of FIG.
And a histogram showing the distribution of brightness in the peripheral circuit section 22, that is, the frequency with respect to the density of a memory chip of a maximum of 1024 bits in a 10-bit configuration. dark. On the other hand, the peripheral circuit section 22 has a low pattern density and is generally bright. Therefore, it is difficult for the memory mat unit 21 to detect a minute defect.
In No. 2, there is a tendency that a normal part is erroneously detected as a minute defect. Further, as shown in FIG.
In the specific layer of the inner pattern, a large number of minute projections called grains are formed on the surface of the pattern, and this causes a difference in brightness. The position of the pattern in which the grain is generated is not constant due to the surface layer or the lower layer, and the density (brightness) of an image signal obtained by imaging from the pattern is not uniform. Similarly, with respect to surface roughness of the pattern, the density (brightness) of an image signal obtained by imaging the pattern becomes non-uniform.

Next, embodiments of a method of inspecting a pattern to be inspected, a method of diagnosing a manufacturing process, and a method of manufacturing a semiconductor substrate according to the present invention will be described.

[First Embodiment] A first embodiment of a method of inspecting a pattern to be inspected, a method of diagnosing a manufacturing process, and a method of manufacturing a semiconductor substrate according to the present invention will be described. FIG. 1 is a configuration diagram showing a first embodiment of a pattern inspection apparatus according to the present invention. FIG. 2 is a schematic explanatory view of a gray scale statistical image of gray scale (brightness) statistical information generated in the first embodiment in the memory mat section of the pattern to be inspected, and FIG. 3 is a peripheral circuit section of the pattern to be inspected. (Brightness) generated in the first embodiment in FIG.
FIG. 4 is a schematic explanatory diagram of a grayscale statistical image in statistical information. FIG.
FIG. 9 is a schematic explanatory view of a pattern edge of a pattern to be inspected for explaining a statistical image of a pattern edge in statistical information on a pattern edge generated in the second embodiment. FIG. 5 is a schematic explanatory diagram of local region matching for quantitatively grasping (inspection) the line width and the degree of droop of a pattern using a statistical image of a pattern edge. FIG. 6 is a configuration diagram showing a second embodiment of the inspection pattern inspection apparatus according to the present invention.

In the first embodiment, a semiconductor wafer will be described as an example of a pattern to be inspected. In FIG. 1, reference numeral 1 denotes an image sensor which outputs a grayscale image signal corresponding to the brightness of reflected light from the semiconductor wafer 4 as a pattern to be inspected, that is, a grayscale. Reference numeral 2 denotes an A / D converter for converting a grayscale image signal obtained from the image sensor 1 into a digital image signal 9; 3a, a first delay memory for delaying the digital image signal (digital grayscale image signal) 9; This is a second delay memory that delays the signal (digital grayscale image signal) 9. That is,
The first delay memory 3a includes a first statistical information generation circuit 17
The digital image signal (digital grayscale image signal) 9 is delayed until statistical information can be generated by about 5 to 20 two-dimensional repetitive patterns in a. The second delay memory 3b includes a second statistical information generation circuit 17b.
, The digital image signal (digital grayscale image signal) 9 is delayed until statistical information can be generated in units of about 5 to 20 one-dimensional repetitive patterns or several chips. Reference numeral 4 denotes a semiconductor wafer having a pattern to be inspected, 5 denotes a stage on which the semiconductor wafer 4 having the pattern to be inspected is mounted and moves in the X, Y, Z, and θ directions (rotation). ,
Reference numeral 7 denotes an illumination light source that illuminates the semiconductor wafer 4 of the pattern to be inspected, and 8 denotes a half mirror that reflects the illumination light to irradiate the semiconductor wafer 4 through the objective lens 6 and transmits the reflected light from the semiconductor wafer 4. Reference numeral 9 denotes a digital image signal obtained by converting a grayscale image signal by an A / D converter. In this manner, the illumination light from the illumination light source 7 is reflected and the semiconductor wafer 4 is subjected to, for example, bright field illumination through the objective lens 6. 28
Is, for example, differentiated from a digital image signal (shown in FIG. 5 (b)) corresponding to the gray level obtained from the A / D converter 2, and the differentiated signal (FIG. 5 (c)) is subjected to the primary differentiation. The differentiated signal waveform 42a is shown.) The signal 42a is output as it is or the differentiated signal has a predetermined threshold value of 2
The binarization process is performed (shown in FIG. 5D or 5E.
(D) shows a binarized signal waveform obtained by binarizing the differential signal waveform 42a with a predetermined positive threshold. FIG. 5E shows a binarized signal waveform having a polarity obtained by binarizing the differentiated signal waveform 42a with predetermined positive and negative threshold values. ), An edge extraction circuit that outputs the binarized signal 42b to extract the signal 42 (42a or 42b) indicating the edge position of the pattern. That is, the digital image signal 9 shown in FIG. 5B is output from the A / D converter 2 by, for example, bright field illumination from the pattern shown in FIG. The edge extracting circuit 28 differentiates the digital image signal 9 to obtain a differential signal 42a (FIG. 5 (c)) that prominently indicates edge position information of a pattern that changes most steeply in the digital image signal 9. ) Is obtained. Further, the edge extraction circuit 28 further binarizes the differentiated signal 42a with a predetermined threshold value, thereby obtaining a binarized signal 4 indicating the edge position information of the pattern.
2b (shown in FIG. 5D or 5E) is obtained. Reference numeral 41 denotes an electronic switch circuit, which switches between a digital image signal 9 corresponding to light and shade obtained from the A / D converter 2 and a signal 42 indicating an edge position of a pattern obtained from the edge extraction circuit 28, thereby switching the first and second signals. To the statistical information generating circuits 17a and 17b and the delay memories 3a and 3b. That is, in the defect inspection, when the signal to be handled is only the digital image signal 9 corresponding to the density, the edge extraction circuit 28 and the electronic switch circuit 41
Becomes unnecessary. In the defect inspection, when the signal to be handled is only the signal 42 indicating the edge position of the pattern,
The electronic switch circuit 41 becomes unnecessary. Conversely, by inputting a selection signal to the electronic switch circuit 41, it is possible to select one of the digital image signal 9 corresponding to shading and the signal 42 indicating the edge position of the pattern as a signal to be handled in the defect inspection.

The first statistic information generation circuit 17a has an A / D
For the digital image signal 9 corresponding to the density output from the converter 2, a statistical image or a density (brightness) of a repeated pattern in the memory mat unit 21 in which a pattern (memory cell) is repeated two-dimensionally. 2.) The edge position of the repeated pattern in the memory mat unit 21 in which the pattern (memory cell) is repeated two-dimensionally with respect to the signal 42 indicating the edge position of the pattern output from the edge extraction circuit 28 or the density statistical information composed of statistical data. , And edge position statistical information including statistical data indicating the edge position of the pattern. The first statistic information generation circuit 17a includes 5-2
A line memory 43a for sequentially storing detected image signals (detected grayscale image signals or detected edge position image signals) detected from about 0 two-dimensional repetitive patterns, and corresponding positions (i + kPx, j + lPy) from the line memory 43a
Of the detected image signal f (i + kPx, j + lPy), the average value or the median value g (i, j) (shown by the following (expression 1)), the standard deviation σ (i, j) (then (Expression 2)), the maximum value max (i,
j), the minimum value min (i, j), or the difference R (i, j) between the maximum value and the minimum value = max (i, j) -min
A CPU 44a for calculating (i, j);
The average value or median value g (i, i,
j), standard deviation σ (i, j), maximum value max (i,
j), a minimum value min (i, j), or a memory 45a for storing statistical information including a difference R (i, j) between the maximum value and the minimum value. The average value or median value g (i, j), standard deviation σ (i, j), maximum value max (i, j), minimum value min (i, j), or difference R between the maximum value and the minimum value (I, j) and the like are referred to as respective items (parameters) of the grayscale statistical image. In other words, the first statistical information generation circuit 17a calculates the corresponding position (i + kPx, j + lPy) from about 5 to 20 two-dimensional repetitive patterns in the memory mat unit 21 in which a pattern (memory cell) is repeated two-dimensionally. (Gray) or median value g (i, j) of edge position f (i + kPx, j + lPy), standard deviation σ (i, j) of brightness (grayscale) or edge position, brightness (grayscale) ) Or the maximum value max (i, j) of the edge position, brightness (shade)
Alternatively, the minimum value min (i, j) of the edge position, or the difference R (i, j) = max (i, j) -min (i, j) between the maximum value and the minimum value of the brightness (shading) or the edge position. ) Is detected. (I, j) indicates coordinates on the repeating pattern. Px is the pitch in the X direction of the repetitive pattern in the memory mat section 21, and Py is the memory mat section 21.
Shows the pitch in the Y direction of the repetitive pattern in FIG. Since these pitches Px and Py change depending on the type of wafer, the pitches Px and Py corresponding to the type of wafer are registered in the CPU 44a, and information on the type of wafer is input by the input means 12 to enter the information. From the registered pitches Px and Py information, it is possible to select a pitch that matches the type of the input wafer. That is, since the first statistical information generation circuit 17a is to generate a statistical image of the density or edge position, which is statistical information of a repetitive pattern in the memory mat unit 21, the CPU 44a is connected to a keyboard, a disk, and a CAD system. Based on the coordinates of the array data and the like in the chip on the wafer 4 obtained based on the design information input by the input unit 12 constituted by a communication network or the like, it is determined that the area is the area of the memory mat unit 21 and The pitch P of the repeated pattern in the X direction and the Y direction in the memory mat unit 21 obtained based on the design information input by the input means 12 with respect to the determined memory mat unit 21
Based on x and Py, it is possible to generate a statistical image of shading or edge position, which is statistical information of a repetitive pattern. The CPU 44a also detects the detected image signal f (i + i) at the corresponding position (i + kPx, j + lPy) from the line memory 43a.
kPx, j + lPy) is read out and subjected to statistical processing. At this time, the corresponding position (i + kPx, j) is read from the line memory 43a.
+ LPy), the detected image signal f (i + kPx, j + lPy) at the corresponding position (i + kPx, j + lPy) is calculated as the amount of mismatch, and the calculated amount of mismatch greatly deviates. Unless otherwise, by performing a process regarded as a match (performing a very coarse match determination process), it is possible to determine whether or not the area is the area of the memory mat unit 21 by looking at the repeatability to two dimensions. .
Therefore, the CPU 44a can determine that the area is the area of the memory mat unit 21 by adding the matching determination processing. Then, the X of the repetitive pattern input by the input means 12 is input to the memory mat unit 21.
The pitches Px and Py in the direction and the Y direction can be set.

As described above, the first statistical information generating circuit 17a uses the statistical image (average value or median value g (i, j), Standard deviation σ (i, j) of brightness (shading) or edge position,
Alternatively, a difference R (i, j) between the maximum value and the minimum value of the brightness (shading) or the edge position is generated, and the generated statistical image of the shading or the edge position is stored in the memory 45a. be able to. Then, from the first statistical image generation circuit 17a,
For example, it is configured to output a plurality of 8-bit digital signals. Note that the first statistical information generation circuit 17a has described that the CPU calculates a statistical image of shading or an edge position, which is statistical information of a repetitive pattern in the X-axis and Y-axis directions. It is clear that the CPU may calculate a statistical image of the density or edge position, which is statistical information of a repeated pattern only in the axial direction. This is because no change is observed in the statistical image of the shading or edge position due to the difference in the direction in which the pattern is repeated.

FIG. 2 shows a gray scale statistical image of one pattern (memory cell) that is repeated two-dimensionally in the memory mat portion 21 having a multilayer structure. FIG. 2A shows a statistical image of the standard deviation σ (i, j) × k of shading. 61
Is a pattern of the surface layer, and is greatly affected by randomly generated surface roughness and grains, and the standard deviation of brightness (variation in brightness) is increased, resulting in a bright image signal. Reference numeral 62 denotes a lower layer pattern. The portion overlapping the surface layer pattern 61 is erased by the surface layer pattern, and the other regions are lower layers, so that the influence of randomly generated surface roughness and grains is attenuated. As a result, the standard deviation of the shading (variation in brightness) is reduced and a dark image signal is obtained. Therefore, the standard deviation σ (i,
j) The sensitivity at the time of determining a defect or extracting a defect candidate from the cell comparison difference image in the comparison circuit 18a can be changed in accordance with the grayscale statistical image signal of × k. That is, the sensitivity of the pattern 21 of the surface layer is reduced due to a large variation in lightness (shading), and the sensitivity of the pattern 22 of the lower layer is increased due to a small variation in lightness (shading). Defect determination or defect candidates may be extracted. FIG. 2B shows a statistical image of the average value g (i, j) of light and shade. Reference numeral 61 denotes a pattern of the surface layer, which is detected as a relatively dark image signal on average. Reference numeral 62 denotes a lower layer pattern, which is detected as an image signal that is brighter on average than the surface layer pattern 61. Average value g of shading
The image of (i, j) indicates the average value of the detected image signals detected over about 5 to 20 two-dimensional repetitive patterns. The detected image signal f (i, j) is used to inspect a defect.
A reference image signal suitable for comparison with j) can be obtained from the wafer to be inspected. Therefore, as compared with the case where the detected image signals detected from the adjacent cells (repeated patterns) are compared with each other in the memory mat unit 21, the influence of randomly generated surface roughness and grain is reduced, and the defect determination or defect candidate determination is performed. The extraction can be realized with high reliability.

FIG. 2 (c) shows the minimum value min.
4 shows a statistical image of (i, j). Reference numeral 61 denotes a surface layer pattern, which has a large standard deviation (brightness variation) as shown in FIG. 2A with respect to an image signal that is relatively dark on average as shown in FIG. 2B. Therefore, the image with the minimum value is detected as very dark. Reference numeral 62 denotes a lower layer pattern, which has a standard deviation (brightness variation) as shown in FIG. 2A with respect to an image signal which is on average brighter than the surface layer pattern 61 as shown in FIG. 2B. ) Is small, the image of the minimum value min (i, j) is detected to be slightly darker than the image signal shown in FIG. As shown in FIG. 2B, the statistical image of the maximum value max (i, j) of the shading is obtained by comparing the image signal with the relatively dark image signal on the average as shown in FIG.
Is symmetrical with the image shown in FIG. Therefore, the difference R (i, j) between the maximum value and the minimum value of the shading (brightness) = max
The statistical image of (i, j) -min (i, j) is 5 to 20
This indicates the range in which the detected image signal detected from about two-dimensional repetitive patterns varies (fluctuates).
Further, the statistical image of the median value between the maximum value and the minimum value of the shading is almost the same as the statistical image of the average value g (i, j) of the shading. Further, instead of the statistical image of the standard deviation of light and shade, a statistical image of the difference R (i, j) between the maximum value and the minimum value of light and shade (brightness) can be used. In addition, the statistical image of the edge position of the two-dimensionally repeated pattern (memory cell) in the memory mat unit 21 that is multilayered and generated by the first statistical information generation circuit 17a includes the edge position (differential image signal or 2). Any of the valued image signals may be used.) The image and the edge position can be taken as the image and median value g (i, j) and the edge position standard deviation σ (i, j) indicating the variation of the edge position. The difference R (i, i) between the maximum value and the minimum value of the edge position indicating the range
j) = max (i, j) -min (i, j). The average value or median value g (i,
j), standard deviation σ (i, j), maximum value max (i,
j), the minimum value min (i, j), the difference R (i, j) between the maximum value and the minimum value, and the like are referred to as each item (parameter) of the statistical image of the edge position. The statistical image of the median value between the maximum value and the minimum value of the edge position is almost the same as the statistical image of the average value g (i, j) of the edge position. Instead of the statistical image of the standard deviation of the edge position, a statistical image of the difference R (i, j) between the maximum value and the minimum value of the edge position can be used.

Variations in process conditions such as uneven coating of resist, resolution of exposure by a stepper, variation in film thickness of a film formed by sputtering or CVD, and variation in etching conditions (for example, the variation between the central portion and the peripheral portion on a wafer). There are various fluctuation factors such as fluctuation, fluctuation by lot unit, and fluctuation based on the type of wafer.) As shown in FIG. That is, as shown in FIGS. 4 (a) and 4 (b), the edge of the pattern includes clarity (how much) depending on the process conditions such as etching and fine irregularities as shown in FIG. 4 (c). The line width partially varies within the wafer, and a phenomenon occurs. For each repetition pattern, the degree of droop of the edge shown in FIG. 4A is smaller than the degree of droop of the edge shown in FIG. The parameter that is the standard deviation of the differential image increases. In addition, as shown in FIG. 4C, the line width including fine irregularities varies for each repetition pattern, and as a result, a parameter which is the standard deviation of a differential image or a binarized image indicating the edge position of the pattern. Becomes larger. In addition, a pattern edge variation phenomenon occurs depending on the lot unit and product type.

The image of the average value g (i, j) of the edge positions is
Indicates the average value of detected image signals detected over about 5 to 20 two-dimensional repetitive patterns, and is suitable for comparison with the detected image signal f (i, j) for inspecting defects. A reference image signal can be obtained from the wafer to be inspected. Therefore, compared to comparing the detected image signals detected from adjacent cells (repeated patterns) in the memory mat unit 21, the influence of the condition of the edge of the pattern randomly generated due to the change in the process condition is reduced. As a result, defect determination or defect candidate extraction can be realized with high reliability. Also, by changing the sensitivity when judging a defect or extracting a defect candidate from the cell comparison difference image in the comparison circuit 18a in accordance with the statistical image signal of the standard deviation σ (i, j) of the edge position, Even if the condition of the edge of the pattern changes due to the change of the condition, the defect determination or the extraction of the defect candidate can be realized with high reliability.

The second statistic image generation circuit 17b has an A / D
As shown in FIG. 3A, the digital image signal 9 corresponding to the gray level output from the converter 2 is one-dimensionally (for example, in the Y-axis direction). Peripheral circuit section in which a pattern is repeated one-dimensionally with respect to a signal 42 indicating a gray scale (brightness) statistical image or gray scale statistical information including gray scale (brightness) statistical data or an edge position of a pattern output from the edge extraction circuit 28. In step 22, statistical image indicating the edge position of the repeated pattern or statistical information indicating the edge position of the pattern is generated. This first statistical information generation circuit 17b
A line memory 43b for sequentially storing detected image signals (detected grayscale image signals or detected edge position image signals) detected over about 5 to 20 one-dimensional repetitive patterns
And the corresponding position (i, j + 1) from the line memory 43b.
Py ′), the detected image signal f ′ (i, j + lPy ′) is read out, and the average value or median value g ′ (i, j) (shown by the following equation (3)) and the standard deviation σ ′ ( i, j)
(Shown by the following (Equation 4)), the maximum value max ′
(I, j), minimum value min ′ (i, j), or difference R ′ (i, j) between the maximum value and the minimum value = max ′ (i, j) −
a CPU 44b for calculating min ′ (i, j) and the CP
Average value or median value g 'calculated in U44b
(I, j), standard deviation σ ′ (i, j), maximum value max ′
(I, j), a minimum value min '(i, j), or a memory 45b for storing statistical information including a difference R' (i, j) between the maximum value and the minimum value. In other words, the second statistical information generating circuit 17b has about 5 to 20 1 in the peripheral circuit 22 in which the pattern is repeated in one dimension.
From the dimensional repetition pattern, the corresponding position (i, j + lP
y ′) mean value or median value g ′ (i, j), standard deviation σ ′ (i, j), maximum value max ′ (i, j), minimum value of the brightness f ′ (i, j + 1Py ′) min ′ (i, j) or the difference R ′ (i, j) between the maximum value and the minimum value = max ′
(I, j) -min '(i, j). (I, j) indicates coordinates on the repeating pattern. Py '
Indicates a pitch in, for example, the Y direction, which is a uniaxial direction of the one-dimensional repetitive pattern as shown in FIG. Since this pitch Py ′ changes depending on the type of wafer,
A pitch Py 'corresponding to the type of wafer is registered in U44b, and information matching the type of wafer inputted is selected from information of the registered pitch Py' by inputting information on the type of wafer. can do. That is, since the second statistical information generating circuit 17b generates a statistical image of shading or edge position, which is statistical information of a pattern in the peripheral circuit section 22, the CPU 44b
Is based on the coordinates of the array data and the like in the chip on the wafer 4 obtained based on the design information input by the input means 12 including a communication network, a keyboard, a disk, and the like connected to the CAD system. And the pitch Py in the Y direction of the repetitive pattern in the peripheral circuit unit 22 obtained based on the design information input by the input means 12 with respect to the determined peripheral circuit unit 22. Or a statistical image of the density or edge position, which is the statistical information of the repetitive pattern, based on the pitch in chip units. Further, the CPU 44a can determine whether or not the area is the area of the memory mat section 21.
Area can be determined. Therefore, C
The PU 44b receives the signal 56 in the area of the peripheral circuit unit 22 from the CPU 44a, and
2 and the peripheral circuit unit 22
The pitch Py ′ in the Y direction of the repetitive pattern input by the input means 12 or the pitch in chip units can be set.

[0035] Further, since the peripheral circuit section 22 is repeated for each chip, the second statistical image generation circuit 17b
A gray scale (brightness) statistic image or a gray scale (brightness) statistic of a pattern of the pattern in the peripheral circuit unit 22 which is repeated for the digital image signal 9 corresponding to the gray scale output from the A / D converter 2 in a chip unit. Statistical image or pattern of the pattern indicating the edge position of the pattern in the peripheral circuit unit 22 in the peripheral circuit unit 22 which is repeated in chip units with respect to the signal 42 indicating the edge position of the pattern output from the edge extraction circuit 28 or the gray scale statistical information composed of data. Edge position statistical information including statistical data indicating an edge position may be generated. In this case, it is necessary to store about several images in chip units in the line memory 43b. That is, the CPU 44b detects the detected image signal f '(i, j) at the position (i, j + 1Py') corresponding to each chip.
+ LPy ') and read the average value or median value g'
(I, j), standard deviation σ ′ (i, j), maximum value max ′
(I, j), minimum value min ′ (i, j), or difference R ′ (i, j) between the maximum value and the minimum value = max ′ (i, j) −
This is because it is necessary to calculate min ′ (i, j).

As described above, the second statistic information generation circuit 17b uses the statistic image (average value or median value g '(i, j), A brightness (shade) or a standard deviation σ ′ (i, j) of the edge position, or a difference (R ′ (i, j)) between the maximum value and the minimum value of the brightness (shade) or the edge position), The generated statistical image of shading or edge position can be obtained by storing it in the memory 45b. The second statistical image generation circuit 17b is configured to output, for example, a plurality of 8-bit digital signals corresponding to the respective statistics.

FIGS. 3B and 3C show grayscale statistical images of a part of the pattern in the peripheral circuit portion 22 which is stacked in multiple layers. FIG. 3B shows the standard deviation σ ′ (i, i,
j) × k statistical images are shown. 63 is a pattern of the surface layer, and is greatly affected by randomly generated surface roughness and grain, and is standard deviation of shading (variation in brightness).
Becomes large, resulting in a bright image signal. 65, 66,
Pattern 67 is the standard deviation of light and shade (variation in brightness)
Becomes an image signal having a medium brightness. 6
Reference numerals 4 and 68 denote lower layer patterns. The portion overlapping with the surface layer pattern 63 is erased by the surface layer pattern, and the other regions are lower layers. The image signal is attenuated, and the standard deviation of brightness (variation in brightness) is reduced, resulting in a dark image signal. Therefore, the standard deviation σ (i,
j) Sensitivity at the time of determining a defect or extracting a defect candidate from a repeated pattern comparison or chip comparison difference image in the comparing circuit 18b in accordance with the grayscale statistical image signal of × k can be changed. That is, the pattern 23 of the surface layer
Is lower in sensitivity due to large variations in lightness (shading), and the lower patterns 64 and 68 are increased in sensitivity due to small variations in lightness (shading) to determine a defect or determine a defect candidate. Should be extracted.

FIG. 3 (c) shows the average value g '(i, j) of the shading.
3 shows a statistical image of the present invention. The patterns 63, 64 and 68 are detected as an averagely bright image signal. The patterns 66 and 67 are detected as image signals having a medium brightness on average. The 65 patterns are detected as dark image signals on average. The image of the average value g '(i, j) of the gray level indicates the average value of about 5 to 20 one-dimensional repetitive patterns or the average value of the detected image signals detected over several chips, and inspects for defects. Thus, a reference image signal suitable for comparison with the detected image signal f ′ (i, j) can be obtained from the wafer to be inspected. Therefore,
Also in the peripheral circuit unit 22, the influence of randomly generated surface roughness and grain is reduced and the defect determination or defect candidate extraction is more reliable than comparing detected image signals detected from adjacent repeated patterns. Can be realized in degrees. In the peripheral circuit section 22, similarly to the memory mat section 21, the difference R '(i, j) between the maximum value and the minimum value of shading (brightness) = max' (i, j) -min '(i,
The statistical image of j) shows about 5 to 20 one-dimensional repetitive patterns or a range in which the detected image signal detected over a unit of several chips varies (changes). Therefore, the statistical image of the median value of the maximum and minimum values of the gray level is almost the same as the statistical image of the average value g '(i, j) of the gray level. Further, instead of the statistical image of the standard deviation of light and shade, a statistical image of a difference R ′ (i, j) between the maximum value and the minimum value of light and shade (brightness) can be used.

The statistical image of the edge position of the one-dimensionally repeated pattern (memory cell) in the multi-layered peripheral circuit section 22 generated by the second statistical information generating circuit 17b includes an edge position (differential image). Signal or a binarized image signal) and an image related to the median value g ′ (i, j) and an image related to the standard deviation σ ′ (i, j) of the edge position indicating the variation of the edge position. Difference R ′ (i, j) = max ′ (i, j) between the maximum value and the minimum value of the edge position indicating the possible range of the edge position
−min ′ (i, j) image. The statistical image of the median value between the maximum value and the minimum value of the edge position is almost the same as the statistical image of the average value g ′ (i, j) of the edge position. Also, instead of the statistical image of the standard deviation of the edge position,
A statistical image of the difference R ′ (i, j) between the maximum value and the minimum value of the edge position can be used.

Variations in process conditions such as uneven coating of resist, resolution of exposure by a stepper, variation in film thickness of a film formed by sputtering or CVD, and variation in etching conditions (for example, a difference between a central portion and a peripheral portion on a wafer). There are various fluctuation factors such as fluctuation, fluctuation by lot unit, and fluctuation based on the type of wafer.) As shown in FIG. That is, as shown in FIGS. 4 (a) and 4 (b), the edge of the pattern includes clarity (how much) depending on the process conditions such as etching and fine irregularities as shown in FIG. 4 (c). The line width partially varies within the wafer, and a phenomenon occurs. For each repetition pattern, the degree of droop of the edge shown in FIG. 4A is smaller than the degree of droop of the edge shown in FIG. The parameter that is the standard deviation of the differential image increases. In addition, as shown in FIG. 4C, the line width including fine irregularities varies for each repetition pattern, and as a result, a parameter which is the standard deviation of a differential image or a binarized image indicating the edge position of the pattern. Becomes larger. In addition, a pattern edge variation phenomenon occurs depending on the lot unit and product type. The image of the average value g ′ (i, j) of the edge position indicates the average value of the detected image signals detected over about 5 to 20 one-dimensional repetitive patterns. Detection image signal f '
A reference image signal suitable for comparison with (i, j) can be obtained from the wafer to be inspected. Therefore, as compared with comparing the detected image signals detected from adjacent cells (repeated pattern) or chip units in the peripheral circuit unit 22, the influence of the edge condition of the pattern randomly generated due to the change of the process condition is compared. And the defect determination or defect candidate extraction can be realized with high reliability. Also, the standard deviation σ ′ (i,
By changing the sensitivity when judging a defect or extracting a defect candidate with respect to the difference image of the cell comparison or the chip comparison in the comparison circuit 18b in accordance with the statistical image signal of j), the pattern is changed due to the change of the process condition. Defect determination or defect candidate extraction can be realized with high reliability even if the state of the edge changes.

Next, a description will be given of the pattern defect inspection and the quantification of the quality of the pattern. The first comparison circuit 18a includes, for example, a first statistical image signal (gi, j) 10a, which is first statistical information shown in FIG. 8, and a first detection image signal (fi) obtained from the first delay memory 3a. ,
j) A positioning circuit 46a for detecting and performing a position shift with respect to 11a, and a comparison parameter setting means 47a in which a comparison parameter for determining a defect is set.
And the first alignment performed by the alignment circuit 46a.
Of the statistical image signal (g′i + Δx, j + Δy) 49a and the first detected image signal (f′i,
and j) a CPU 48a for extracting a feature quantity and extracting a defect candidate or a defect by comparing the 50a with the 50a based on the comparison parameter set by the comparison parameter setting means 47a. The comparison parameter setting means 47 a
Standard deviation σ of shading or edge position in the memory mat section 21 generated by the statistical information generating circuit 17a of FIG.
Based on (i, j) or the difference R (i, j) between the maximum value and the minimum value of the shading or the edge position, the CPU 48a extracts a feature amount and sets a comparison parameter for extracting a defect candidate or a defect. Can be set. The comparison parameter setting means 47a includes a communication network connected to a process device (eg, an exposure device such as a stepper, an etching device, a film forming device such as CVD or sputtering, a resist coating device, and the like), a keyboard, a disk, and a type and lot of a wafer. Process conditions (exposure conditions,
Etching conditions, film forming conditions, resist coating conditions, etc.) and the type and lot of wafers can also be set.
In short, it is necessary to change the defect candidate and the defect determination criteria according to the type and lot of the wafer. In addition, it is possible to change the criterion for determining a defect candidate or a defect according to process conditions.

As described above, the first comparison circuit 18
In FIG. 8A, first, the alignment circuit 46a
The first statistical image signal (gi, gi) which is the first statistical information shown in FIG.
j) Alignment is performed by detecting a positional shift between 10a and the first detected image signal (fi, j) 11a obtained from the first delay memory 3a. Next, the CPU 48a compares the first statistical image signal (g′i + Δx, j + Δy) 49a aligned with the alignment circuit 46a with the first delay memory 3a.
Is compared with the first detected image signal (f'i, j) 50a obtained based on the comparison parameter set by the comparison parameter setting means 47a. A mismatch candidate area or a maximum length of the digitized image, a barycenter coordinate (position coordinate) of the mismatch, etc.) are extracted, and a defect candidate or a defect signal 51a is extracted including the barycenter coordinate (position coordinate) indicating the occurrence position. That is, the first statistical image signal (gi, j) 10a becomes an averaged reference image signal in the cell comparison for the memory mat unit 21, and
In the PU 48a, the influence of randomly generated surface roughness and grain, or the effect of the condition of the edge of a pattern randomly generated due to a change in process conditions is reduced, and the defect judgment or the extraction of the defect candidate is performed with high reliability. Can be realized. The memory mat unit 21 sets comparison parameters in accordance with the statistical image signal of the standard deviation σ (i, j), so that the comparison circuit 18
The sensitivity can be changed when a defect is determined or a defect candidate is extracted with respect to the difference image of the cell comparison in a, and the sensitivity is set in accordance with the variation in the lightness (shading) obtained from the pattern. Defect judgment or defect candidates can be extracted, and sensitivity can be set in accordance with the degree of edge of the pattern, and defect judgment or defect candidate extraction can be realized with high reliability.

In the second comparison circuit 18b, first, the positioning circuit 46b firstly outputs the second statistical image signal (gi, j) 10b which is the second statistical information shown in FIG.
Of the first detected image signal (f
i, j) and 11b to detect the positional deviation and perform the alignment. Next, the CPU 48b operates the alignment circuit 46b.
The second statistical image signal (g′i + Δx, j +
Δy) 49b and the second delay memory 3b obtained from the second delay memory 3b.
Is compared with the detected image signal (f'i, j) 50b based on the comparison parameter set by the comparison parameter setting means 47b. Of the defect candidate or defect 51b including the barycentric coordinates (position coordinates) indicating the generation position by extracting the area, the maximum length, and the barycentric coordinates (position coordinates) of the mismatch.
Is extracted. That is, the second statistical image signal (gi, j)
10b is an averaged reference image signal in the cell comparison or the chip comparison with respect to the peripheral circuit unit 22;
In the PU 48b, the influence of randomly generated surface roughness and grain, or the influence of the condition of the edge of the pattern randomly generated due to the change of the process condition is reduced, and the defect judgment or the extraction of the defect candidate is performed with high reliability. Can be realized. The peripheral circuit unit 22 sets a comparison parameter in accordance with the statistical image signal of the standard deviation σ ′ (i, j), whereby the comparison circuit 18 b
It is possible to change the sensitivity when judging a defect or extracting a defect candidate from the difference image of the cell comparison or the chip comparison in the above, and set the sensitivity according to the variation in the lightness (shading) obtained from the pattern To extract defect judgments or defect candidates (including cases indicated by feature amounts), and to set the sensitivity in accordance with the degree of edge of the pattern, and to perform defect judgment or defect candidate extraction with high reliability. Can be realized.

The first comparison circuit 18a and the second comparison circuit 18b may be of a system developed by the present inventors, such as the one described in Japanese Patent Application Laid-Open No. 61-212708. As shown in FIG. 18, the image alignment circuits 46a and 46b and the difference image detection unit 136 of the aligned image and the difference image detected by the difference image detection unit 136 are binarized by a threshold value Vth to obtain a binary image. A mismatch detector 137 for detecting a dimension mismatch and the mismatch detector 13
And a filter section 138 for removing a noise component from the binarized mismatched image detected in Step 7 by the filter selected by the filter selection signal 140 obtained from the alignment and boundary section sensitivity control circuit 35 shown in FIG. A feature amount extraction unit 139 for calculating a feature amount such as an area, a length (projection length), and coordinates of a mismatched portion (defect portion or defect candidate portion) from the binarized mismatched image from which the noise component has been removed by 138. CPUs 48a and 48b may be used. The CPUs 48a and 48b include a difference image detection unit 136, a mismatch detection unit 137, and a filter unit 13.
8 and the feature amount extraction unit 139 may be realized by a circuit configuration. When the first comparison circuit 18a and the second comparison circuit 18b compare the statistical image with the detected image, the brightness (shade value) of the pixel of interest in the detected image is
If the brightness of the average value at the corresponding pixel of the statistical image is within a range of k times the standard deviation (for example, k = 3), it is determined to be normal, and if it is out of the range, it is determined as a defect or a defect candidate. Can be output.

In the above case, the first comparison circuit 18a and the second comparison circuit 18b determine the presence or absence of a defect or a defect candidate. However, as shown exaggeratedly in FIG. The deviation amount ΔG from the range or the deviation amount ΔG ′ from the average value, which becomes information on the performance of the corresponding pattern, may be output as the mismatch amount (shown by oblique lines). In this case, if the detected image contains a defect, the information becomes defect candidate information, and if the detected image does not contain a defect, it becomes information indicating the state of the pattern. In any case, even if it is the information of the defect candidate, it can be handled as the information indicating the state of the pattern by the processing method in the CPU 19. Further, in the first comparison circuit 18a and the second comparison circuit 18b, the above-mentioned comparison parameters are variously changed, the inspection is performed a plurality of times, and a logical sum of the inspection results of the plurality of times is obtained to obtain the final result. This is the same as the case of the lighting conditions described later. In addition, it is obvious that the first comparison circuit 18a and the second comparison circuit 18b can extract a defect or a defect candidate according to the finished condition of the pattern.

The CPU 19 includes a defect candidate (characteristic amount) including the barycentric coordinates (position coordinates) indicating the occurrence position in the memory mat unit 21 obtained by optimizing the sensitivity by setting the comparison parameter from the first comparator 18a. Or a signal 51a indicating a defect, and a barycentric coordinate (position indicating a generation position in the peripheral circuit unit 22 obtained by optimizing the sensitivity by setting the comparison parameter from the second comparator 18b. (Including coordinates) or defect signal 51b
Statistical information 10a in the memory mat section 21 obtained from the first statistical information generating circuit 17a, statistical information 10b in the peripheral circuit section 22 obtained from the second statistical information generating circuit 17b, and a process device (for example, a stepper or the like). Exposure equipment, etching equipment, film forming equipment such as CVD or sputtering, resist coating equipment, etc.), a communication network connected to a higher-level CAD system, a keyboard, a disk, and a reader for reading the kind and lot of a wafer. Detailed analysis of the defect candidate is performed based on the process conditions input by the input unit 12, the information on the kind and lot of the wafer, and the coordinate information such as the array data including the inside of the chip on the wafer 4 obtained based on the design information. And analyze the state of the pattern.

That is, the CPU 19 sets the first comparator 18a
Defect candidates including the barycentric coordinates (position coordinates) indicating the occurrence position in the memory mat unit 21 obtained by optimizing the sensitivity by setting the comparison parameter obtained from (including the case where the defect is provided by data indicating the feature amount) By performing a detailed analysis on 51a, it can be determined as a true defect. For example, when the defect candidate signal 51a is regularly generated according to the pattern repeated from the first comparator 18a, the defect candidate signal 51a is
A true defect can be detected by erasing using coordinate information such as array data including the inside of the chip above. In addition, the feature amount (the amount of inconsistency of light and shade (brightness) and the area or maximum length of mismatch of the binarized image (including the image indicating the edge position) obtained from the first comparator 18a and the coordinates of the center of gravity of the mismatch (position Signal 51a of a defect candidate indicated by coordinates
On the other hand, it is possible to detect a true defect under an optimum condition by changing a criterion for determining that the defect is a true defect in accordance with the process conditions, the kind and lot information of the wafer, the array data on the wafer 4, and the like. it can. Fig. 4
As shown in (c), there are a chipped defect 71, a projected defect 72, an isolated defect 73, and the like, and it is necessary to change the criterion according to the type of these defects. For example, when a true defect is determined based on a mismatched area, it is necessary to change the area according to the type of the defect as a criterion.

Similarly to the memory mat unit 21, the CPU 19 supplies the second comparator 18b to the peripheral circuit unit 22 as well.
Defect candidates including the barycentric coordinates (position coordinates) indicating the occurrence position in the peripheral circuit unit 22 obtained by optimizing the sensitivity by setting the comparison parameter obtained from (including the case where the defect is provided by data indicating the feature amount) Alternatively, a true defect can be detected under optimum conditions by performing a detailed analysis on the defect signal 51b. Then, the CPU 19 can store the inspected defect information 57a in, for example, the storage device 13 so as to be able to output including the barycentric coordinates (position coordinates) indicating the occurrence position. Further, the CPU 19 can display and monitor the defect candidate signals 51a and 51b indicated by the feature amounts obtained from the first comparator 18a and the second comparator 18b on a display means 52 such as a display. At this time, the process conditions input by the input means 12, the information on the kind and lot of the wafer, the arrangement data on the wafer 4, and the like can also be displayed on the display means 52 together with the display means 52. Monitor the process status. The first comparison circuit 18
a, the comparison result of the memory mat section 21 is obtained.
The comparison result of the peripheral circuit unit 22 is obtained from the comparison circuit 18b of the memory mat unit 2 based on the coordinate information on the wafer input by the input unit 12, for example.
1 or the peripheral circuit unit 22 to identify the comparison result from the first comparison circuit 18a and the second comparison circuit 18b.
May be selected to make the final determination. Further, the CPU 19 compares the cell in the memory mat unit 21 by the first comparator 18a and the second comparator 1
The selection between the cell comparison and the chip comparison in the peripheral circuit unit 21 according to 8b may be performed as follows. That is,
The CPU 19 calculates the mismatch information based on the cell comparison obtained from the first comparator 18a, for example, for each image in a predetermined range of the number of mismatched pixels. By being able to determine that there is no area, the result of the peripheral circuit section 22 obtained from the second comparator 18b is selected, and if the number of mismatched pixels is smaller than the threshold value, it can be determined that the area is the area of the memory mat section 21. As a result, the first comparator 18a
Can be selected. According to this method, the CPU 19 can select the chip comparison or the cell comparison without the arrangement information in the chip.

The CPU 19 also controls the first and second statistical images 10a stored in the delay memories 23a and 23c.
And 10b and the detected image signals 11a and 11b stored in the delay memories 23a and 23c, through a clipping circuit 25 by a clipping signal 24 obtained based on, for example, a defect signal or a defect candidate signal 51a and 51b, for detailed analysis. It is clear that this may be done. When the CPU 19 quantifies and analyzes the performance of the pattern for the memory mat unit 21 and the peripheral circuit unit 22, the first statistical information generation circuit 17a
Information 10 in the memory mat unit 21 obtained from the
and the statistical information 10b in the peripheral circuit section 22 obtained from the second statistical information generating circuit 17b. Then, the CPU 19 can store, for example, in the storage device 13 so as to be able to output the quality of the pattern as quantified data 57b. That is, depending on whether a pattern having a grain or surface roughness in the surface exists in the surface layer or the lower layer in the multi-layer pattern, the density image 9 obtained from the pattern greatly varies. As a result, for example, FIG. As shown in FIG.
The parameters of the standard deviation σ (i, j) of the density and the difference R (i, j) between the minimum value and the maximum value, which are the statistical information 10a of the density in the memory mat section 21 obtained from the memory mat 7a, are increased. As shown in (b), the standard deviation σ ′ (i, j) of the density which is the density statistical information 10b in the peripheral circuit unit 22 obtained from the second statistical information generation circuit 17b.
The parameter of the difference R '(i, j) between the minimum value and the maximum value increases.

Further, the CPU 19 obtains the statistical information 10a of the edge position in the memory mat section 21 obtained from the first statistical information generating circuit 17a based on the image signal 42 indicating the edge position of the pattern obtained from the edge extracting circuit 28.
The average value g (i, j), the standard deviation σ (i, j) of the edge position, and the difference R (i, j) between the minimum value and the maximum value
Can be quantified on the basis of the above parameters, and the average value g '(), which is the statistical information 10b of the edge position in the peripheral circuit unit 22 obtained from the second statistical information generating circuit 17b, is obtained. i, j) (shown in FIG. 3A) and the standard deviation σ ′ of the edge position.
(I, j) and the difference R '(i, j) between the minimum value and the maximum value
Based on these parameters, it is possible to quantify the quality of the pattern of the peripheral circuit section. That is, the CPU 19
By comparing the statistical information of the edge position in the central portion obtained from the first and second statistical information generating circuits 17a and 17b with the statistical information of the edge position in the peripheral portion of one wafer 4, one wafer is obtained. The difference between the central part and the peripheral part in the wafer 4 can be grasped. When the statistical information is an average value, it is possible to quantitatively grasp an average difference such as a pattern width between a central portion and a peripheral portion in the wafer 4 and an inclination of a pattern edge (a degree of pattern cutting by etching). .

The CPU 19 can grasp the difference in the lot unit by comparing the statistical information of the edge position obtained in the lot unit of the wafer 4 from the first and second statistical information generating circuits 17a and 17b. . When the statistical information is an average value, it is possible to quantitatively grasp an average difference such as a pattern width and an inclination of a pattern edge (a degree of pattern cutting by etching) in a lot unit. Further, the CPU 19 can grasp the difference according to the type of the wafer by comparing the edge position statistical information obtained from the first and second statistical information generating circuits 17a and 17b according to the type of the wafer 4. it can. When the statistical information is an average value, it is possible to quantitatively grasp an average difference such as the pattern width and the inclination of the pattern edge (the degree of cutting of the pattern by etching) according to the type of wafer. CPU 19
As shown in FIG. 6A, the average value statistical image (FIG. 6) showing the edge position in the edge position statistical information obtained from the first and second statistical information generating circuits 17a and 17b.
It is shown on the right side of (a). ) And an ideal reference image (a reference image based on design specifications) based on CAD information input using the input unit 12 (shown on the left side of FIG. 6A) as indicated by an arrow. The amount of deviation for each local region is obtained by performing matching for each pattern, and the sum of the amounts of deviation is calculated over the region where the pattern exists, thereby obtaining a difference in pattern with respect to the design value (variation of line width and drooping of edge. Changes) can be grasped quantitatively. That is, even when the edge of the pattern is drooping in a large area, the degree of deformation of the pattern can be quantified and output.

Incidentally, the shape of the actually manufactured pattern is often slightly different from the design value. So, CP
U19 is not actually compared with an ideal reference image based on CAD information, but is actually captured and detected from the A / D converter 2, and standard detection is performed from the detected image signals stored in the delay memories 23b and 23d. The image signal 53 can be cut out and selected by the cutout circuit 25 by the cutout designation signal 24.

Then, as shown exaggeratedly in FIG. 6B, the CPU 19 selects the selected standard detected image signal 53.
, The first and second statistical information generation circuits 17a,
Average value statistical image g indicating the edge position obtained from 17b
By calculating a discrepancy amount (shown by oblique lines) that deviates from the allowable value ± ΔE set using the standard deviation σ (i, j) or the like for (i, j), the degree of pattern completion (line) The width, the degree of deformation due to the degree of cutting due to etching, etc.) can be quantified and grasped. Note that the allowable value ± ΔE may be arbitrarily set using the input unit 12. The average statistical image g (i, j) and the standard detected image signal 53 may be differential image signals. In this case, the amount of mismatch is the integral value of the difference signal between the differential image signals.

In the above-described embodiment, the standard detected image signal 53 is cut out from the delay memories 23b and 23d and selected, and the first and second standard detected image signals 53 are used for the selected standard detected image signal 53. Statistical information generation circuit 17a, 1
Average value statistical image g showing the edge position obtained from 7b
By calculating the amount of mismatch (indicated by oblique lines) that deviates from (i, j) by using the standard deviation σ (i, j) or the like and set to an allowable value ± ΔE, the quality of the pattern is determined. However, the discrepancy between the edge positions obtained from the first and second comparators 18a and 18b (the average value g (i, j) which is a statistical image of the edge positions) is obtained.
Of the edge position in the detected image f (i, j) from the range based on the standard deviation σ (i, j) with respect to the detected image f (i, j) from the average value g (i, j) which is a statistical image of the edge position. i, j) is determined by C
In the PU 19, a total of a predetermined pattern area (for example, a cell unit), a total for a chip unit, or a total for a wafer unit is obtained, thereby forming a pattern in a predetermined pattern area (for example, a cell unit) or a chip unit or a wafer unit. The state can be quantified and grasped. As a result, the information on the state of the quantified pattern can be used as a measure of process conditions such as exposure, etching, film formation, and resist application.

As described above, the statistical information (average value and standard deviation) of the edge position obtained from the first and second statistical information generating circuits 17a and 17b is used for direct exposure, etching, film formation, resist coating, and the like. It can be used as a measure of process conditions.

Naturally, with respect to the data 57b quantifying the quality of the pattern obtained by the CPU 19, the data on the wafer 4 obtained based on the process conditions input by the input means 12, the information on the kind and lot of the wafer, and the design information. It is apparent that the information can be stored in the storage device 13 so that coordinate information such as array data including the inside of the chip can be added and output.

Next, an embodiment different from the embodiment shown in FIG. 1 will be described with reference to FIG. In this embodiment, the first delay memory 3 is provided in the first comparator 18a.
a from the detected image signal 11a and the delay memory 54a
The cell is compared with the detected image signal 11b which is delayed by an integral multiple of the pitches Px and Py of the repetitive pattern.
The feature amount is extracted from the detected image signal 50a and the detected image signal 50c aligned in 6a based on the comparison parameter set by the comparison parameter setting means 47a, and a defect candidate or a defect is extracted. Comparator 18b
, The detected image signal 11b obtained from the second delay memory 3b and the detected image signal 11d obtained by delaying the pitch Py 'of the repetitive pattern by an integral multiple or the pitch of the chip in the delay memory 54b by cell comparison or chip comparison and alignment. A feature amount is extracted from the detected image signal 50b and the detected image signal 50d aligned by the circuit 46b based on the comparison parameter set by the comparison parameter setting means 47b to perform a defect candidate or defect extraction process. is there. Then, the first statistical information 10a obtained from the first statistical information generating circuit 17a is input to the comparison parameter setting means 47a of the first comparator 18a, and the second statistical information obtained from the second statistical information generating circuit 17b is input. That is, the statistical information 10b is input to the comparison parameter setting means 47b of the second comparator 18b. In the case of this embodiment, the first and second
The comparators 18a and 18b compare the detected image signals with each other to extract a difference image, and each of the first and second determination criteria (comparison parameters) when extracting a defect candidate or a defect from the extracted difference image is used as a first criterion. Statistical information generation circuit 17
a and the second statistical information 10b obtained from the second statistical information generating circuit 17b.
Is to use.

As a criterion (comparison parameter) in the first comparator 18a, a standard deviation σ (i, j) indicating, for example, a variation which is the first statistical information 10a obtained from the first statistical information generating circuit 17a. ) And the difference R (i, j) between the maximum value and the minimum value are used, and the second comparator 18b
, The second statistical information 10 obtained from the second statistical information generating circuit 17b as a criterion (comparison parameter).
b, for example, a standard deviation σ ′ (i, j) indicating a variation
And the difference R '(i, j) between the maximum value and the minimum value are used, and depending on whether a pattern having a grain or surface roughness in the surface exists in the surface layer or the lower layer in the multilayer pattern,
Even if there is a large variation in the density detection image 9 obtained from this pattern, or even if the processing condition of the pattern changes due to a change in the process conditions, the first and second comparators 18a and 18b determine whether or not there is a defect. Candidate extraction can be realized with high reliability. The arithmetic processing in the CPU 19 is the same as in the embodiment shown in FIG.

Inspection is performed a plurality of times by changing the above-mentioned comparison parameters variously.
What may be the final result is the same as in the case of the lighting conditions described below.

As described above, the statistical information generation circuit 1
The statistical information generated in 7a and 17b can be used in various forms. Statistical information or statistical images are, for example, reference or standard detection images, setting of comparison parameters, parameters for detailed analysis, parameters for quantifying the quality of pattern, in wafer, lot unit and wafer type Can be used as an index of change. In the above-described embodiment, bright field illumination is adopted as illumination. However, the illumination is not limited to this, and any illumination can be used as long as it can be used as microscope illumination such as dark field illumination or annular illumination. Needless to say, the present invention can be applied to illumination by an electron beam. However, for example, pattern edges are observed dark in bright-field illumination, but brightly observed in dark-field illumination. Therefore, what is compared mainly depends on the illumination. Inspection may be performed a plurality of times by changing these illumination conditions variously, and a logical sum of the inspection results of the plurality of inspections may be obtained as a final result. Alternatively, a logical product may be taken to reliably identify the defect, and a process diagnosis may be performed based on, for example, the defect distribution and number. In this case, it is not necessary to perform a review for visually confirming a mismatched portion, and the operation can be simplified and simplified.

Next, the operation of the inspection apparatus having the above configuration will be described. That is, in FIG. 1, the image sensor 1 scans the stage 5 with the illumination light converged by the objective lens 6 and moves the target area of the semiconductor wafer 4 of the pattern to be inspected at a constant speed. , That is, the brightness information (shade image signal) of the memory mat portion 21 and the peripheral circuit portion 22 in the chip 20 are detected. Then, the target area is moved at high speed between the target areas. In other words, the inspection is performed at the repetition of the constant speed movement and the high speed movement. Of course, a step-and-repeat inspection can be used. Then, the A / D converter 2 converts the output (shade image signal) of the image sensor 1 into a digital image signal 9. This digital image signal 9 has a 10-bit configuration. Next, for the digital image signal 9 or the signal 41 indicating the edge of the pattern, the first statistical image generating circuit 17a generates statistical information such as a statistical image in the memory mat unit 21. The first comparator 18a is a memory mat unit 21
The signal (data) of the defect or the defect candidate indicated by the feature amount in is extracted. The second statistical image generation circuit 17b generates statistical information such as a statistical image in the peripheral circuit unit 22 for the digital image signal 9 or the signal 41 indicating the edge of the pattern. The second comparator 18b extracts a signal (data) of a defect or a defect candidate indicated by the feature amount in the peripheral circuit unit 22. The CPU 19 performs a detailed analysis based on the signals (data) of the defects or defect candidates extracted by the first and second comparators 18a and 18b to calculate true defect information. Based on statistical information such as statistical images obtained from the statistical image generation circuits 17a and 17b, the degree of performance of the pattern is quantified and grasped. As a result, from the CPU 19, information on the true defect and information quantifying the degree of the pattern can be obtained.

The CPU 19 can output the statistical image itself and associate it with the process, or correlate the statistical image with the electrical characteristic data of the element to help improve the process. Here, the electrical characteristic data refers to the access time of the memory element and the like, and is correlated with the statistical image and the quality data of the result of the electrical characteristic,
It can also help improve processes. Here, for example, since the standard deviation of the position of the edge of the pattern represents the variation of the edge of the pattern, it can be used as a state monitor of an exposure apparatus or an etching apparatus. By examining which layer has a large pattern edge variation using the design data, it is possible to specify a process device related to the specific layer.

The pattern inspection apparatus according to the present invention has delay memories (image storage memories) 23a to 23d as shown in FIGS.
By driving the cutout circuit 25 with the cutout signal 24, one or both of the two images used for the extraction of the defect or defect candidate indicated by the feature amount are simultaneously copied with the defect or defect candidate. It is also possible to cut out, input and store, and to use the stored image to obtain detailed information such as defect size and defect brightness indicated by feature amounts other than the presence or absence of a defect or defect candidate. Specifically, the stored image data is read out by the CPU 19 during or after the inspection, and the image analysis is performed on the CPU 19. In the image analysis in the CPU 19, the difference image (mismatch) between the statistical image indicating the normal part obtained from the first and second comparison circuits 18a and 18b and the detected image having the defective part is obtained.
(A brightness mismatch amount based on a gray-scale difference image, a mismatched two-dimensional area binarized for the difference image, its shape (for example, circularity and length), a defect portion with respect to a normal portion) Of the brightness, the variation in the brightness inside the mismatch, etc.) can be analyzed in a wide variety of ways. Further, the CPU 19 evaluates the state of the pattern of the normal part corresponding to the mismatch (defect or defect candidate indicated by the feature amount), that is, evaluates the shape and appearance of the pattern, and takes correspondence with the appearance of the pattern of the defective part. This makes it possible to grasp the influence of the defect on the pattern. For example, in a detection image having a defective portion cut out by the cutout circuit 25, if the edge of the pattern is seen in the same manner as the statistical image which is a normal portion cut out by the cutout circuit 25, a defect such as a change in film thickness (water) Mark etc.). For example, in a detection image having a defective portion cut out by the cutout circuit 25,
If there is no pattern edge, it can be determined that the pattern itself is a shape defect (such as defective etching) such as damage to the pattern itself. Therefore, the CPU 19 can classify the defect. Of course, using technologies such as neural networks,
Classification may be made according to the characteristics of the pattern or the characteristics of the defect. Further, the position where the defect has occurred can also be determined from the shape of the pattern. For example, even if there is no cell position coordinate information, it is possible to determine whether a defect has occurred in the mat or not by evaluating the repeatability of the pattern. Here, since both the defect image and the corresponding normal image can be stored in the memory at the same time during the inspection, the analysis can be performed more effectively.

Further, the first and second comparison circuits 18
a, setting of comparison parameters in 18b and CPU
It can also be used for setting conditions such as determination of analysis parameters at the time of analysis at 19. That is, a difference image (absolute value) is obtained by comparing the gray-scale average value images 10a and 10b in the statistical image with the gray-scale detection images 11a and 11b in the first and second comparison circuits 18a and 18b. On the other hand, the CPU 19 extracts a defect or a defect candidate based on an extraction margin (comparison parameter) of a defect or a defect candidate set in accordance with the difference between the density standard deviation or the maximum value and the minimum value of the density of the statistical image. Based on the extracted result, it is determined whether or not the extraction margin (comparison parameter) of the defect or the defect candidate is appropriate. If the extraction margin is not appropriate, the input means 12 or the like is used to extract the defect or defect candidate. By correcting the (comparison parameter), an extraction margin (comparison parameter) for an appropriate defect or defect candidate for the wafer is obtained. This method is particularly effective for setting conditions of an optical system. The σ value, the degree of diffusion, the illumination wavelength, the magnification, and the like, which are the illumination conditions of the optical system, are changed, and the statistical images obtained from the first and second statistical information generation circuits 17a and 17b obtained according to these changes are changed. Change or first and second comparison circuits 18a,
Margin (comparison parameter) set for the difference image obtained by comparing the statistical image with the detected image from 18b
The extraction result of defects or defect candidates obtained based on
By performing the evaluation analysis in the CPU 19, the optimal optical system conditions can be set.

A specific embodiment of an optical system for detecting an optical image of a pattern on the wafer 4 is shown in FIG. 21 (plan view), FIG. 22 (front view), and FIG. In these figures, an infinity correction system is used as the objective lens 209 (6), and a second objective lens (also called a tube lens) 303 having a long focal length (for example, f = 200 mm) is used. A ring-shaped illumination (bright-field illumination) niria image sensor 212a and a dark-field illumination linear image sensor 308 corresponding to the image sensor 1 are TDI (Ti
me Delay Integration) It consists of a time delay integration type image sensor. In this configuration, the objective lens 209 and the second
Between the objective lens 303 and the polarizing beam splitter PB
An S (Polarization Beam Splitter) 208 a and a λ / 4 plate (quarter wavelength plate) 251 are provided. Since the light between the objective lens 209 and the second objective lens 303 is parallel light, insertion of these elements does not cause deterioration of aberration. The utility of the polarizing beam splitter PBS 208 a and the λ / 4 plate (quarter wavelength plate) 251 is as shown in FIG. 23. The reflected light from wafer 4 is
reaches the λ / 4 plate, becomes P-polarized light 333, and becomes PBS208a.
Is transmitted as it is, and reaches the image sensor 212a.
In FIG. 21, a ring-shaped illumination filter 205 sets the degree of the ring of illumination. The intensity of the illumination light is set by the ND filter 214, and the illumination wavelength and the diffusivity are set by the color filter or the diffusion plate 316. In this configuration example, in order to switch the illumination wavelength,
Two types of lamps can be changed. Zoom lens 213
Sets the optical magnification. In such a configuration, the illumination conditions of the optical system, such as the σ value and the degree of diffusion, the illumination wavelength,
Optimal conditions can be set by the above-described image storage and analysis of the magnification and the like. In the case of an apparatus using an electron beam described later,
The beam diameter of the electron beam, the acceleration voltage, etc. can be optimized.

Apart from these, it can also be used as an image filing system as shown in FIG. In particular, C
The PU 19 performs the first and second comparison circuits 17a during the inspection,
Since a desired defect image can be obtained in the defect memory 141 from the feature amount extraction unit 139 of 17b, the storage device 147 (13)
The filing of a defect image into a device can be performed in real time. That is, the CPU 19 detects, for example, the detected image (f (i, j), f ′ (i, j)) of the defective portion extracted by the extraction circuit 25.
11a, 11b and statistical images (g (i, j), g '(i,
j)) Since various kinds of images such as 10a and 10b can be filed on the database of the storage device 147 (13) via the memory 123 for primary storage, when an electrical failure of the LSI occurs, the image data is searched. By confirming and responding to a failure event, it is useful as a failure analysis such as analysis and analysis of failure factors and a yield improvement support system. By classifying the image data corresponding to the electrical defect and comparing it with a newly generated appearance defect, it is immediately known whether or not the appearance defect is a factor of the electric defect. Therefore, a defect countermeasure can be taken simultaneously with the occurrence of a defect, which is effective in improving the yield. It is convenient for searching if information such as the size and coordinates of a defect is added to the image data. After defect detection, individual defects are reviewed,
An operator may input the form and the cause of the defect, and add the input category data to the image data.

In the CPU 19, the cut-out circuit 2
20 is driven by the cutout signal (defect or defect candidate signal) 24, thereby causing a defect within the dimension range designated as the cutout signal (defect or defect candidate signal) 24 or within the designated position range as shown in FIG. By instructing the user as a defect, an image of a desired defect can be stored. Specifically, when one or both of the two images used for extracting the defect or the defect candidate are partially stored in the memory 123 simultaneously with the extraction of the defect or the defect candidate, the first and second comparison circuits are used. The defect / defect candidate presence / absence signal 143 obtained from the characteristic amount extraction units 139 of 18a and 18b, the coordinate signal 144 which is one of the characteristic amounts of the defect or defect candidate, or one of the characteristic amounts of the defect or defect candidate A certain dimension signal 145, an area 146 which is one of the feature amounts of a defect or a defect candidate, or any combination is logically combined in the defect signal determination logic 142, and an image is stored based on a necessary signal. Control what you do. Needless to say, these signals are synchronized with the detected image signal.

The image filing system described above has a function of transmitting data to the outside, and if data can be transferred to an external database, data can be stored in the database of the overall analysis system for a larger entire line. Become. Next, the first and second comparison circuits 1
The highly accurate calculation and positioning of the positional deviation amount performed by the positioning circuits 46a and 46b of 8a and 18b will be described with reference to FIGS. FIG. 8 is a schematic explanatory diagram of a method of aligning an image of a pattern to be inspected according to an embodiment of the present invention, and FIG. 9 is a schematic diagram illustrating a sampling position relationship between two images in the image aligning method of FIG. The following can be considered as the detection of the displacement amount. (A) Linear interpolation method (method for minimizing the difference in shading) (b) Quadratic function interpolation method (method for minimizing the difference between differential values) (c) Regularized interpolation method (the difference between differential values is reduced) Method (a) for minimizing the difference between light and shade with a constraint condition The method (a) is to minimize and match the square error of the light and dark of two target images. The method (b) aims at applying linear interpolation to the differential image. The method (c) satisfies the method (a) using the method (b) as a constraint, and the regularization parameter γ is given as a weight to the sum of squares of the difference between the differential values. When the parameter γ = 0, the same result as the method (a) is given.
Both methods do not require repetitive operations or the like, and can be realized only once.

The (a) linear interpolation method will be described. The image alignment is performed using the statistical image and the reference image by pixel alignment and sub-pixel alignment as shown in FIG. The pixel alignment is used to compare two images (for example, a detected image f
The grayscale difference (the difference between the value of each pixel of the reference image and the value of the corresponding pixel of the statistical image) is calculated while shifting one of i, j and the statistical image gi, j) in pixel units, and the grayscale difference is minimized. This is for obtaining the amount of displacement. The range for detecting the positional deviation of the image is, for example, a maximum of ± 3 pixels, and is variable according to the pattern design rule. By shifting one image position by the obtained positional shift amount, the two images are aligned.

First, the pixel alignment will be described. This will be described using the following equation (5) described in the frame (A) of FIG.

[0071]

(Equation 5)

Pixel Position Alignment Detection 81
Is to detect Δx and Δy where S (Δx, Δy) in the above equation (5) is min. However, since the minimum position can be obtained only in pixel units, it is added as an offset depending on which of Δx and Δy is closer to the true position.

Based on the following equation, 1 is added to Δx and Δy or is left as it is. That is, S (1,
0) + S (1, -1) + S (0, -1) is the minimum,
Δx ++, S (-1, 0) + S (-1, -1) + S
If (0, -1) is the minimum, S (-1, 0) +
If S (-1, 1) + S (0, 1) is minimum, then Δy +
+, S (1, 0) + S (1, 1) + S (0, 1) are minimum, Δx ++, Δy ++, Δx ++ is Δx
= Δx + 1. The two images delayed by each of the delay memories 82 and 83 are aligned with each other, and the pixel alignment 84 shifts the position of one of the images by the position shift amount always obtained by the detected image f. , The two images are aligned.
That is, the detected image f is always moved to the upper right to obtain a new image f ', and the moving direction can be specified from four types (lower right, upper left, lower left, upper right) to one type. it can. This leads to hardware simplification.

In the sub-pixel alignment, a positional shift amount smaller than a pixel is obtained, and two images are aligned with high accuracy. The pixel unit alignment 84 and the sub-pixel alignment 88 are collectively performed, for example, every 256 lines. The sub-pixel alignment is performed by the displacement detection unit 85.
, Delay memories 86 and 87, and a positioning unit 88.

First, the displacement detecting section 85 will be described with reference to the frame (B) of FIG. The displacement detector 85
Calculates images f 'and g' based on linear interpolation. However, as for the displacement amounts α and β, the one that minimizes the square error of the difference between f ′ and g ′ is detected as the displacement amount.
That is, the criterion of the displacement detection is to match the shading of the two interpolation images. Next, the positioning unit 88
Now, description will be made using the frame (C) in FIG. New images f 'and g' are obtained by interpolating the images based on the convolution (convolution sum) of S based on the positional shift amounts α and β with the statistical image f and the reference image g. ×
The symbol with indicates convolution. FIG. 9 shows the relationship between the sampling positions of the original image f and the new image f '. The difference between the sampling positions corresponds to the displacement amounts α and β.

The feature of the above method is that the position shift amounts α and β are obtained so that the shading of the two images to be aligned is well matched in the sense of the minimum square error. We are not seeking the true value of the quantity. However, in the comparison after the alignment, the difference in the density of the normal part can be reduced, and this is considered to be a convenient method in the comparative inspection. Further, the calculation of the positional deviation amounts α and β can be performed analytically without repeated calculation, which is advantageous in that it is suitable for hardware.

Next, the quadratic function interpolation method of the method (b) will be described. This method aims at applying linear interpolation to a differential image. First, the following equation (6)
It is assumed that a differential interpolation equation of the equation (7) is used.

[0078]

(Equation 6)

[0079]

(Equation 7)

The displacement amounts α and β are set so that the value of the differential interpolation formulas expressed by the above-mentioned equations (6) and (7) becomes the minimum value of S expressed by the equation (8). Ask for.

[0081]

(Equation 8)

In the above equation, the following equation (Equation 9) and (Equation 1)
0) equation, defines a C _1, C _2, C ₃ shown in equation (11).

[0083]

(Equation 9)

[0084]

(Equation 10)

[0085]

[Equation 11]

The above equations (9), (10), (1)
Using C ₁ , C ₂ , and C ₃ in equation (1), equation (12) is used.
The displacement amounts α and β shown in Expression (13) are obtained.

[0087]

(Equation 12)

[0088]

(Equation 13)

Next, the regularization interpolation method of the method (C) will be described. S, which is expressed by the following equation (14), that is, the displacement amounts α and β that minimize the difference in shading are obtained under the constraint that the difference between the differential values is minimized.

[0090]

[Equation 14]

The following equations (15), (16), (1)
7) C ₁ , C ₂ , C ₃ , C ₄ , C ₅ , and C ₆ shown in the equations (Equation 18), (Equation 19), and (Equation 20) are determined.

[0092]

(Equation 15)

[0093]

(Equation 16)

[0094]

[Equation 17]

[0095]

(Equation 18)

[0096]

[Equation 19]

[0097]

(Equation 20)

Using these C ₁ , C ₂ , C ₃ , C ₄ , C ₅ , and C ₆ and letting the regularization parameter be γ, the above equation (14) is represented by the following equation (21).

[0099]

(Equation 21)

From the equation (21), the following equation (22) is obtained.
Α and β shown in Expression (23) are obtained.

[0101]

(Equation 22)

[0102]

(Equation 23)

In the above equation, the regularization parameter γ
Is equal to 0, which matches the conventional linear interpolation.

The following method is conceivable as a method of positioning the sub-pixel alignment. (A) 'Linear interpolation method (method for minimizing the difference in density) (b)' Bilinear interpolation method (c) 'Quadratic function interpolation method (d)' Tertiary convolution method (spline interpolation method) (a ) ′ A new image f′ij represented by equation (24A) by the linear interpolation method is obtained by combining Sij represented by equation (24B) below and the original image fij based on the displacement amounts α and β. Can be obtained by the convolution.

[0105]

(Equation 24)

Similarly, a new image g′i + △ x, j + △ y represented by the formula (25A) is represented by the following formula (25B) based on the displacement amounts α and β. S'ij and original image g
It can be obtained by convolution with i + △ x and j + △ y.

[0107]

(Equation 25)

(B) 'A new image f'ij represented by the equation (26A) by the bilinear interpolation method is expressed by the following equation (26B) based on the displacement amounts α and β. And the convolution of the original image fij.

[0109]

(Equation 26)

Similarly, a new image g′i + △ x, j + △ y represented by the formula (27A) is represented by the following formula (27B) based on the displacement amounts α and β. S'ij and original image g
It can be obtained by convolution with i + △ x and j + △ y.

[0111]

[Equation 27]

(C) 'The quadratic function interpolation method is as follows (Equation 2)
8) It is obtained by differentiating the interpolation formulas of Expression (29).

[0113]

[Equation 28]

[0114]

(Equation 29)

When the above equation is expressed by a 4 × 4 convolution, it is expressed by the following (Equation 30) and (Equation 31).

[0116]

[Equation 30]

[0117]

(Equation 31)

(D) 'In the tertiary convolution method (spline interpolation), the new image f'ij is expressed by the following (Equation 32A).
It is obtained by the convolution of Sij and the original image fij, which are represented by the formulas, and the displacement amounts α and β are represented by the formula (32B).

[0119]

(Equation 32)

In the equation (32B), h (t) = si
When n (πt) / πt is set and expanded by an approximate expression, h
(T) is represented by the following equation (33).

[0121]

[Equation 33]

In the equation (32B), x ₁ = 1
+ Α, x ₂ = α, x ₃ = 1−α, x ₄ = 2-α, y ₁ = 1 +
β, y ₂ = β, y ₃ = 1-β, y ₄ = 2-β. Similarly, a new image g′i + △ expressed by Expression (34A)
x and j + △ y are based on the displacement amounts α and β,
B) can be obtained by the convolution of S′ij represented by the equation and the original images gi + △ x and j + △ y.

[0123]

(Equation 34)

In the above formula, x ₁ = 1 + (1−α), x ₂
= (1−α), x ₃ = 1− (1−α), x ₄ = 2− (1−
α), y ₁ = 1 + (1−β), y ₂ = 1−β, y ₃ = 1−
(1-β), y ₄ = 2- (1-β). Among these methods, the (d) 'cubic convolution method (spline interpolation) is considered to have the smallest smoothing effect and has no directionality. Here, realization is performed by convolution of 4 × 4 pixels so that both methods can be used together. Equations (35) and (36) show examples of convolution weights.

[0125]

(Equation 35)

[0126]

[Equation 36]

However, these alignments are particularly necessary in chip comparison, and a fixed amount of shift correction may be used in cell comparison.

In any case, in the registration of the images, the positional deviation is detected by linearly interpolating the images or linearly interpolating the differential images, and minimizing the amount of mismatch between the interpolated images or the linear combination of the amounts of mismatch. So that
The displacement amount of the image is obtained with a resolution smaller than the pixel, and the alignment can be obtained by performing linear interpolation or convolution interpolation on the image based on the detected displacement amount. As a result, the image can be aligned with extremely high accuracy, and the object intended in the present invention can be realized with higher sensitivity. Further, in the above-described embodiment, in one or a plurality of image alignment methods including image shift detection and alignment, position shift detection is performed by linearly interpolating each image or linearly interpolating a differential image of each image. In order to minimize the amount of mismatch between these interpolated images or the linear combination of the amount of mismatch, data for calculating the shift amount using the image should be obtained by wiring logic, and calculated from the data for calculating the shift amount. The shift amount may be obtained by a program logic at a resolution of a unit smaller than a pixel, and the position alignment may be performed by wiring logic to perform linear interpolation, quadratic interpolation or convolution interpolation of each image based on the position shift amount. This is, for example, in equation (8), Σ
The statistic C2C3 is obtained by hardware, that is, wiring logic. Thereafter, α and the like are obtained by program logic.
At this time, when α and the like are obtained, error processing and the like can be performed flexibly.

The detection of the positional deviation is performed by linearly interpolating each image or by linearly interpolating the differential image of each image, and by making the amount of mismatch between these interpolated images or the linear combination of the amount of mismatch the minimum. The shift amount calculation data using the image is obtained by wiring logic, the shift amount to be calculated from the shift amount calculation data is obtained by the program logic at a resolution of less than a pixel, and the alignment is performed based on the position shift amount. It can also be performed by wiring logic by convolution as in the embodiment. In the above-described embodiment, the alignment of the image is performed by using (Equation 24A), (Equation 26A), and (Equation 32).
As shown in the example of A), all of them can be realized by the convolution operation. In addition, by applying these and displaying the distortion for each image, it is also possible to monitor the state of the apparatus such as the running state of the stage and the scanning state when scanning with an electron beam. In the above embodiment,
The case where the output is performed in the 8-bit configuration from the first statistical image generation circuit 17a and the second statistical image generation circuit 17b has been described, but the output may be performed in the 10-bit configuration.

In the method of continuously detecting and comparing images, one image can be obtained continuously.
The other image is divided into regions (for example, 256 × 2
(56 pixels) at the time of pixel alignment. FIG. 16 shows an example of the cause. Image distortion due to various causes such as low density of pattern and inaccurate detection of displacement due to lack of pattern information, vibration of optical system or vibration of stage system, and charging in case of electron beam. And the image becomes discontinuous. When discontinuity occurs, the boundary of the image in the subdivided area becomes an indefinite value by image processing such as sub-pixel alignment, pixel interpolation, and differentiation. For this reason, a mismatch occurs in the comparison, and erroneous detection occurs. If the images are continuous, no discrepancy occurs even if differentiation is performed. Also, if only the conventional pixel-by-pixel comparison is performed after pixel alignment, no mismatch occurs. In addition, a method of performing pixel interpolation, differentiation, and the like in a range larger than the subdivided region and comparing normal values in the subdivided region may be considered, but this causes an increase in circuit scale.

To solve this, 1) detect whether the image is discontinuous 2) If it is discontinuous, lower the sensitivity before and after the boundary (boundary portion) 3) If it is discontinuous, or if it is discontinuous, the sensitivity before and after the boundary is not 4) Or, always lower the sensitivity before and after the boundary 5) Or always, set the non-inspection area before and after the boundary 6) Decrease the sensitivity by converting the difference between the two images into a binary image. The reduction (shrink) process is performed 7) or the sensitivity is lowered by increasing the binarization threshold value of the gray level difference.

The above 1) is based on Δx, Δy of the detected amount of misalignment for pixel alignment (S (Δx, Δ
It is to check whether Δx and Δy), where y) is min, have the same value between the pixels. Furthermore, it checks whether the following offsets are the same value. Based on the following formula, add 1 to Δx and Δy, or
leave it as it is. That is, S (1,0) + S (1,-
1) If + S (0, -1) is minimum, Δx ++, S (-
If (1,0) + S (-1, -1) + S (0, -1) is the minimum, S (-1,0) + S (-1,1) + S
If (0,1) is the minimum, Δy ++, S (1,0) + S
If (1,1) + S (0,1) is minimum, then Δx ++, Δ
y ++, Δx ++ means Δx = Δx + 1. In practice, it is checked whether the values after adding x and y offsets to Δx and Δy are the same between the images.

Next, the above-described sub-pixel alignment is performed on the aligned image in such a manner that a positional shift amount of a unit smaller than the pixel is obtained, and the two images are aligned with high accuracy. If the image is discontinuous, the value of the pixel at the boundary of the image becomes indeterminate, which adversely affects subsequent processing. For example, when differentiation is performed after sub-pixel alignment and the differential values are compared, the differential value has an abnormal value at the boundary pixel. The defect in which one boundary is uncertain after the sub-pixel alignment becomes more uncertain in the two boundary pixels after the first differentiation has a bad influence on defect detection.
In various filters such as Sobel, the boundary is uncertain in any case. Therefore, an abnormal boundary is determined according to the subsequent processing, and erroneous detection that occurs at this boundary is prevented. For this, the above 2) to 7) are performed. Of course, the differentiation process is performed before the alignment, and if the defect determination is only the comparison of the corresponding pixels, there is no erroneous detection at the boundary even if the image is discontinuous. However, usually, various processes are executed after the alignment in terms of the circuit scale, and the boundary process is required. From the above, it is necessary to minimize the boundaries of images. This is determined by taking an image as large as possible within a range in which distortion of one image can be tolerated, and so that the data amount does not become enormous at the time of alignment.

Further, for an image detected using an electron beam, it is possible to perform positioning of a plurality of images not only for the image of interest but also for a plurality of past images directly or by using these positional deviation information. This is shown in FIG. FIG.
5, reference numeral 27 denotes a delay memory, 28 denotes an edge position extracting circuit constituted by a differentiating circuit, 29 denotes a binarizing circuit,
30 is a mismatch detection circuit, 31 is a delay circuit, 32 is a positioning circuit, 33 is a defect determination circuit, 34 is a state storage circuit,
Reference numeral 35 denotes a positioning and sensitivity control circuit. The state detection circuit stores the state of alignment of the image temporally before the image of interest, that is, the state of the number of mismatched pixels between images and the amount of misalignment, and at the time of alignment of the image of interest,
Positioning is performed in consideration of such information. Accordingly, when it is considered that there is no pattern information in the target image and the positioning accuracy is insufficient, the positioning accuracy can be ensured. In this embodiment, the edge position of the pattern is indicated by the binarized image signal using the edge position extracting circuit 28 and the binarizing circuit 29. Needless to say, a directly obtained digital gray image signal may be used as it is.

FIG. 17 shows an embodiment of the boundary processing. In the figure, (a) shows an image (here, two continuous images).
(B) shows the boundary signal (three pixels before and after the boundary), and (c) and (d) show the types (two types) of reduction filters and the timing of application. Reduction filter A
Is to output a mismatch equal to or larger than this size to the binarized image of the difference image for an area other than the boundary.
Specifically, for a binarized image, the AN of these 2 × 2 pixels is used.
D is obtained. Similarly, the reduction filter B outputs a mismatch equal to or larger than this size to the binarized image of the difference image for the boundary area. Here, the size of the reduction filter B is made larger than that of the reduction filter A, thereby lowering the sensitivity at the boundary. Of course, when the images are not discontinuous, the reduction filter B may be the same as the reduction filter A, or may be omitted. The processing shown in FIG. 17 is performed by the defect determination circuit 33 (CPU
48).

FIG. 18 shows an embodiment of the defect judgment circuit 33. In the figure, the difference between the aligned images is detected, binarized, filtered, and finally the unmatched features (coordinates, dimensions, areas, etc.) are calculated. 136 is a difference detection circuit, 137 is a binarization circuit, 138 is a filter circuit that can execute either the filter A or the filter B, 13
Reference numeral 9 denotes a feature amount extraction (unmatched coordinates, dimensions, area, etc.) circuit. In addition, there is provided a defect or defect candidate determination circuit for determining the characteristic amount extracted by the characteristic amount extraction circuit 139 based on a comparison parameter which is a criterion.
Here, the threshold value Vth for binarization may be a set value, but may be controlled by the alignment and boundary portion sensitivity control circuit 35. That is, as described above, the decrease in sensitivity is caused by the difference of 2
This may be performed by increasing the value threshold at the boundary in synchronization with the boundary signal. The signal from the alignment and boundary sensitivity control circuit 35 input to 138 is a filter selection signal.

Further, according to this configuration, in synchronization with the boundary signal, the threshold value is set to, for example, 255 at the boundary portion (the maximum value in the case of 8-bit gradation), and the mismatch is completely output. The boundary may be a non-inspection area.
In this case, the value of the image is uncertain at both ends of the image corresponding to both ends of the image sensor. However, this can be prevented from being erroneously detected by masking or not using both ends of the image as in the related art.

[Embodiment 2] In [Embodiment 1] shown in FIG. 1, a defect inspection image processing apparatus for a pattern to be inspected, that is, an A / D converter 2
From the stage 5, the objective lens 6, the illumination light source 7, the half mirror 8, the image sensor 1
Although the description has been given of the case where the present invention is applied to an apparatus constituted by an optical microscope system composed of, for example, the present invention can be applied to a scanning electron microscope system. However, the defect inspection image processing apparatus for the pattern to be inspected according to the present invention, that is, the A / D converter 2 to the CPU 19 shown in FIG.
When applied to a scanning electron microscope system, the image sensor 1
Instead of a detector such as a scintillator.

A case where the present invention is applied to a scanning electron microscope will be described with reference to FIG. FIG. 10 is a schematic explanatory view of a defect inspection apparatus for a pattern to be inspected according to another embodiment of the present invention. FIG. 10 is a schematic explanatory view of an electron optical system when a scanning electron microscope is used in a defect inspection image processing apparatus for a pattern to be inspected. In FIG. 10, reference numeral 101 denotes an electron source that emits an electron beam; 102, an electron beam emitted from the electron source;
Reference numerals 03 and 104 denote electrodes constituting an objective lens for converging an electron beam, 105 a deflector for deflecting the electron beam, 106 a wafer having a pattern to be inspected, 108 secondary electrons emitted from the wafer, and 109 secondary electron detection. Reference numeral 110 denotes a display / control device for controlling each device of the apparatus. As shown in FIG. 10, an electron beam 102 emitted from an electron source 101
Is focused on a wafer 106 as a sample by an objective lens including two electrodes 103 and 104. Of the two electrodes 103 and 104 constituting the objective lens,
The voltage of the first electrode 103 located on the electron source 101 side is set to a positive voltage with respect to the second electrode 104 at the ground potential located on the wafer 106 side, and this voltage is adjusted.
By adjusting the electric field between the first electrode 103 and the second electrode 104, the lens function of the objective lens is adjusted.
As a result, the lens main surface of the objective lens is
4 is formed below.

Further, the electron beam 102 is surrounded by the first electrode 103 so that the electron beam 102 is deflected by an electrostatic or magnetic deflector 105 in a space maintained at the same potential as the first electrode 103. And scanned two-dimensionally on the wafer 106.

The secondary electrons or reflected electrons generated from the wafer 106 by the irradiation of the electron beam 102 are detected by two sets of secondary electrons which are arranged at a position symmetrical to the electron beam 102 and in a plane perpendicular to the tilt axis. Detector or backscattered electron detector 108
The image of the wafer 106 is obtained on a display unit in the display control device 110 using the detection signal as a video signal. The configuration described above is disclosed in
The configuration is the same as that of the charged particle beam observation device described in US Pat. Here, when an electrostatic type objective lens is used, it is not necessary to wind an exciting coil as in the case of a magnetic field type lens, so that the lens itself can be downsized. For example, while the size of a conventional magnetic lens is 100 to 150 mm in diameter, the diameter of an electrostatic objective lens can be 10 mm or less. However, when the present invention is applied to the scanning electron microscope as described above, it is necessary to deal with the problem that image distortion or the like is likely to occur in the image detection process. Therefore, it is important to reliably perform image alignment even when a small set of repeating patterns such as the memory mat unit 21 is targeted.

Therefore, as shown in FIG. 10, a new backscattered electron detector 111, here of an annular type, is provided to separate and detect backscattered electrons and secondary electrons, and to use a plurality of images based on the images detected by the backscattered electrons. Image alignment can be performed. Here, the image by the reflected electrons is hardly affected by the charge-up of the pattern by the primary electrons, and can be said to be an image obtained by treating the image as if it were light.
As for the backscattered electron detector, an annular type has good symmetry and is suitable for inspection of various patterns, but of course, any shape may be used. Further, when continuously detecting an image using an electron beam, image distortion can be further reduced by using an image of a repeated pattern in the scanning direction of the electron beam for a plurality of repeated patterns of the mat portion. is there. Further, by combining the embodiment shown in FIG. 1 with the electron beam detector shown in FIG. 10, defect detection is performed using an image detected using light, in which defect coordinates are calculated, and an image detected using an electron beam is used. It is also possible to obtain detailed information of a defect based on the feature amount of the defect other than the presence or absence of the defect (for example, the size of the defect and the brightness of the defect against the background) using the peripheral image including the more defective portion. Is useful for high precision inspection.

In the embodiment of the present invention, when a statistical image is obtained, gradation conversion such as conversion of an image histogram is not performed. However, histogram equalization or the like may be performed as preprocessing. . this is,
It is effective for countermeasures such as charge-up by an electron beam.

According to the embodiment of the present invention, a defect can be detected with high sensitivity without being affected by a difference in brightness of a pattern depending on a place. Therefore, a dark area such as the memory mat section 21 can be inspected with high sensitivity, and a pattern with a large variation in brightness inside can be inspected with high sensitivity. Also, the peripheral circuit section 22 and the like can be subjected to an optimal inspection. In addition, not only is it possible to detect the difference in density of an image, but also it is possible to compare various types of information of the image in an extremely accurate manner, which is effective. Therefore,
Inspection with higher reliability than before can be realized. Further, even if the image is distorted, the image can be aligned with high accuracy, and the same effect can be expected even when the pattern density is low. As described above, in the embodiment according to the present invention, the generation of the statistical image of the image based on the image detection using the optical microscope or the scanning electron microscope and the comparative inspection method have been described. It is needless to say that the present invention is similarly effective when used for the detected image detection.

[Embodiment 3] Next, referring to FIG. 11, an application of the present invention to the analysis of the cause of defects in a semiconductor manufacturing process will be described. FIG. 11 is an application diagram of the image processing apparatus according to the present invention to a semiconductor manufacturing process. In the present embodiment, the comparison result from the first comparison circuit 18a and the second comparison circuit 18b, the feature amount information 51 output from the CPU 19, and the defect (including foreign matter) information 57a
And information on the degree of pattern formation based on statistical information, and analyze the causes of defects in the semiconductor manufacturing process, and remove the analyzed causes of defects to produce non-defective semiconductor chips with high yield. Will be described. In FIG. 11, reference numeral 380 denotes a semiconductor manufacturing line, 381 denotes a transfer route of the semiconductor wafer 4a, and 382 denotes a semiconductor manufacturing process in which an insulating film is formed.
A CVD apparatus for performing a VD film forming process, 383 is a sputtering apparatus for performing a sputtering step for forming a wiring film in a semiconductor manufacturing process, and 384 is an exposing step for performing resist coating, exposure, development and the like in a semiconductor manufacturing process. Is an etching apparatus for performing an etching step for patterning in a semiconductor manufacturing process, and a semiconductor wafer is manufactured through various manufacturing steps.

391 is a comparison circuit 18 and a CPU.
An interface for inputting the feature amount information 51, defect information 57a, and information 57b on the degree of pattern formation based on the statistical information obtained from 19; 392, a CPU for executing processing such as analysis; and 393, a program for analysis and the like stored. The memories 394, 395, 396, and 397 are control circuits,
Reference numeral 98 denotes an output device such as a printing device that outputs an analysis result of a defect occurrence cause or the like, 399 denotes a display device that displays various data,
400 is a bus line for transferring data between the devices, 40
Reference numeral 1 denotes an input device including a keyboard, a disk, and the like;
Is an external storage device (not shown) for storing history data or a database of a defect occurrence cause or a causal relationship with the defect occurrence factor that caused a defect that cannot be obtained from the inspection image processing apparatus. The interface 410 provides information on the analyzed cause of the defect or the cause of the defect and information for controlling the manufacturing process conditions. Further, 390 is the state of the pattern based on the feature amount information 51 output from the devices shown in the comparators 18a and 18b and the CPU 19 (see FIG. 1), defect 57 (including foreign matter) information and statistical information. Of the production line 380
Is an analysis computer for analyzing control information for controlling a defect generation cause or a defect generation factor and a manufacturing process condition. The manufacturing line 380 includes process devices 382, 383, 384, and 3 for manufacturing semiconductors.
85.

The analysis computer 390 includes an interface 391 for inputting the feature amount information 51, defect information 57a, and information 57b on the degree of pattern formation based on the statistical information output from the comparators 18a and 18b and the CPU 19 (not shown). CPU 392 that executes processing such as analysis
Memory 393 storing an analysis program and the like; control circuits 394, 395, 396, and 397; a printing device that outputs analysis results such as causes of defects and control information analyzed for controlling manufacturing process conditions; Output device 3
98, a display device 399 for displaying various data, data related to the production line 380, and the production line 38.
An input device 401 for inputting data or the like relating to the semiconductor wafer 4a flowing into the semiconductor wafer 4a, history data of a defect occurring on the semiconductor wafer 4a and a cause of the defect or a cause and effect of the defect occurrence factor, a database and a pattern and the like. External storage device 402 storing history data or a database of the correspondence relationship with the manufacturing process conditions
The information on the cause of the defect or the cause of the defect analyzed by the CPU 392 and the information 410 for controlling the manufacturing process conditions are stored in the manufacturing line 380.
And a bus line 400 for connecting them.

Therefore, the CPU 392 of the analysis computer 390 determines whether the input feature amount information 51, defect information 57a, and the information 57b of the pattern condition based on the statistical information are stored in the semiconductor wafer 4a stored in the external storage device 402. Defects generated above and each process device 3
Production line 38 consisting of 82, 383, 384, 385
0, history data of a defect generation cause or a causal relationship with the defect generation factor that caused the defect at 0, the state of the database and the pattern, and the respective process devices 382, 38
3, 384, 385 based on the historical data or database of the correspondence relationship with the manufacturing process conditions, the defect generation cause or the defect generation factor that caused the defect in the production line 380 composed of each process device 382, 383, 384, 385 And the control information for controlling the manufacturing process conditions is analyzed, and the analyzed information on the cause of the defect or the cause of the defect and the information 410 for controlling the manufacturing process condition are provided to each of the process devices 382 and 38.
3, 384, 385.

Each of the process apparatuses 382, 383, and 3 provided with the information on the cause of the defect or the cause of the defect and the information 410 for controlling the manufacturing process condition.
84 and 385 can send a non-defective semiconductor wafer 4a to the next factory by controlling various process conditions including cleaning and removing a defect generation factor or a defect generation factor. As a result, semiconductors can be manufactured with high yield. The semiconductor wafer 4a on which the defect inspection is performed is formed on the manufacturing line 380 from a process before and after a location where a defect is likely to occur.
It is sampled in units or lots. Also,
The CPU 392 of the analysis computer 390 outputs a foreign matter signal detected by, for example, a dedicated foreign matter inspection device (not shown) (the foreign matter can also be detected as a defect by the inspected pattern inspection device shown in FIGS. 1 and 7). Foreign matter information obtained and input from the CPU 19 based on the data and the semiconductor wafer 1 stored in the external storage device 402
a and the process devices 382, 383,
A production line composed of the process devices 382, 383, 384, and 385 based on a foreign substance generation cause or a historical data or a database of a causal relationship with the foreign substance generation factor that caused the foreign substance on the production line 380 composed of 384 and 385. The foreign matter generation cause or foreign matter generation factor that caused the foreign matter in 380 is analyzed.

The analyzed information 410 on the foreign matter generation cause or the foreign matter generation factor is provided to each of the process devices 382, 383, 384, 385 of the manufacturing line 380. Each of the process devices 382, 383, and 3 to which the information 410 on the foreign matter generation cause or the foreign matter generation factor is provided.
84 and 385 can control the various process conditions including the cleaning to remove the cause of foreign matter generation or the cause of foreign matter generation so that a non-defective non-defective semiconductor wafer 4a can be sent to the next step, and as a result, a high yield of semiconductor can be obtained. Can be manufactured.

[0151]

According to the present invention, a pattern to be inspected can be inspected with high sensitivity and high reliability without being affected by the state of the surface of a multilayer inspected pattern in which surface roughness, grains, etc. occur. The effect that can be performed. Further, according to the present invention, there is an effect that the pattern to be repeatedly inspected in the mat portion constituting the semiconductor memory can be inspected with high sensitivity and high reliability without being restricted by the sensitivity of the entire chip. . Further, according to the present invention, a true defect can be inspected with high reliability by enabling a detailed analysis of a defect or the like occurring in a repeated pattern to be inspected.

Further, according to the present invention, it is possible to quantitatively grasp the performance of the repetitive pattern to be inspected.

Further, according to the present invention, the quality of the repetitive pattern to be inspected is quantitatively grasped to diagnose the manufacturing process for manufacturing the pattern to be inspected (resolution of stepper, quality of etching, etc.), and the result is evaluated. This produces an effect that can be fed back to the manufacturing process. Further, according to the present invention, on a semiconductor substrate such as a semiconductor wafer, surface inspection can be performed with high sensitivity and high reliability without being affected by the surface condition of a multilayer inspection pattern in which surface roughness or grain or the like occurs. It is possible to produce a semiconductor substrate having high reliability by inspection. Further, according to the present invention, it is possible to perform positioning with respect to one or a plurality of images with high accuracy, and as a result, it is possible to faithfully extract a feature amount such as a defect in a repeated pattern to be inspected. Further, according to the present invention, it is possible to inspect a pattern to be inspected repeatedly using an electron beam with high sensitivity and high reliability without being affected by various errors such as distortion and difference in brightness. The effect that can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a pattern inspection apparatus according to the present invention;

FIG. 2 is a schematic explanatory view of a gray scale statistical image in a memory mat section obtained by a first statistical information generating circuit shown in FIG. 1;

FIG. 3 is a schematic explanatory diagram of a gray scale statistical image in a peripheral circuit portion obtained by a second statistical information generating circuit shown in FIG. 1;

FIG. 4 is a diagram for explaining that a statistical image of an edge position of a pattern obtained by the first and second statistical information generating circuits shown in FIG. 1 indicates the state of the pattern;

FIG. 5 is a diagram for explaining a relationship between signal waveforms for extracting an edge position of a pattern by the edge position extraction circuit shown in FIG. 1;

FIG. 6 is a schematic explanatory diagram of matching based on a comparison between a statistical image and a reference image or a detected image.

FIG. 7 is a configuration diagram showing another embodiment of the inspection apparatus of the pattern to be inspected according to the present invention.

FIG. 8 is a schematic explanatory diagram of a method for aligning images according to the present invention.

FIG. 9 is an explanatory diagram schematically illustrating a relationship between sampling positions of two images in the image alignment method illustrated in FIG. 8;

FIG. 10 is a configuration diagram showing still another embodiment of the inspection pattern inspection apparatus according to the present invention.

FIG. 11 is a configuration diagram showing one embodiment of a manufacturing process analysis system according to the present invention.

FIG. 12 is a schematic explanatory view of a memory mat portion and a peripheral circuit portion in a memory chip of a pattern to be inspected according to the present invention.

13 is a histogram of brightness in a memory mat portion and a peripheral circuit portion in the memory chip shown in FIG.

14 is a schematic explanatory view of a pattern to be inspected when there is a grain in the memory mat section shown in FIG. 12;

FIG. 15 is a diagram showing another embodiment of the image positioning circuit.

FIG. 16 is an explanatory diagram of a cause of discontinuous images.

FIG. 17 is a diagram for describing an embodiment of image boundary processing.

FIG. 18 shows a CP in the comparison circuit shown in FIGS. 1 and 7;
FIG. 16 is a diagram showing one embodiment of a specific configuration of the defect determination circuit shown in FIG.

FIG. 19 is a CPU for performing the detailed analysis shown in FIGS. 1 and 7;
FIG. 14 is a diagram illustrating a schematic configuration of another embodiment different from the first embodiment.

FIG. 20 stores an image of a desired defect or defect candidate when the user designates a defect or defect candidate within a dimension range designated as a signal of a defect or defect candidate or a defect or defect candidate within a designated position range. FIG. 1 is a configuration diagram showing an embodiment for performing the above.

FIG. 21 is a plan view of an embodiment of an optical system that detects an optical image of a pattern to be inspected.

FIG. 22 is a front view of FIG. 22;

FIG. 23 is a diagram for explaining the relationship of polarized light in the optical systems shown in FIGS. 21 and 22.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image sensor, 2 ... A / D converter, 3a ... 1st delay memory, 3b ... 1st delay memory, 4, 4
a: semiconductor wafer, 5: X, Y, Z, θ stage,
Reference numeral 6: Objective lens, 7: Illumination light source, 8: Half mirror, 9: Digital image signal, 10a, 10b: Statistical information (statistical image signal), 11a, 11b: Detection image signal, 12: Input means, 13: Storage device, 17a ...
1st statistical information generation circuit, 17b ... second statistical information generation circuit, 18a ... first comparison circuit, 18b ... second comparison circuit, 19 ... CPU, 20 ... chip, 21 ...
Memory mat section, 22... Peripheral circuit section, 23 a to 23
d: delay memory, 25: cutout circuit, 28: edge position extraction circuit, 29: binarization circuit, 30: mismatch detection circuit, 31: delay circuit, 32: positioning circuit,
33: Defect determination circuit, 34: State storage circuit, 35
... Positioning and sensitivity control circuit 43a, 43b ... Image memory, 44a, 44b ... CPU, 45a, 45b
... memories, 46a, 46b ... alignment circuits, 47
a, 47b... comparison parameter setting means, 48a, 48b
... CPU, 51a, 51b ... Defect or defect candidate signal, 52 ... Display means, 57a ... Defect information, 57b
... Information on how the pattern is made 101. Electron source 10
2 electron beam 103 103 first electrode 104 second electrode 105 deflector 106 semiconductor wafer
108 ... secondary electron, 109 ... secondary electron detector, 110
... Display / control device 111 Backscattered electron detector 123
.., Memory 136, difference detection circuit, 137, binarization circuit, 138, filter circuit, 139, feature quantity extraction circuit, 141, defect memory, 147, storage device, 38
0: semiconductor production line, 381: semiconductor wafer 1
a transport path a, 382... CV to be formed to form an insulating film
D apparatus, 383: sputtering apparatus for forming a wiring film, 384: exposure apparatus for performing an exposure step, 385
... Etching apparatus for performing an etching step, 391
.., An interface, 392, a CPU for executing processing such as analysis, 393, a memory storing programs for analysis, etc., 394, 395, 396, 397, a control circuit,
398: an output device such as a printing device; 399: a display device for displaying various data; 400: a bus line for transferring data between the devices; 401: an input device including a keyboard and a disk; 402: an external device for storing a database Storage device, 403 ... interface, 4
10 ... Information on defect occurrence,

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location G01N 21/88 G01N 21/88 D G01R 31/02 G01R 31/02 G06T 7/00 G06F 15/62 405A

Claims (30)

[Claims] An image signal is detected from a repeated pattern to be inspected, statistical information indicated by a statistic of the repeated pattern to be inspected is generated from the detected image signal, and the generated statistical information is used. A method for inspecting a pattern to be inspected, characterized by quantifying the degree of completion of the pattern to be inspected. 2. An image signal is detected from a repeated pattern to be inspected, statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal, and the generated statistical information is used. A method of inspecting a pattern to be inspected, comprising extracting a defect or a defect candidate present in the pattern to be inspected. 3. An image signal is detected from the repeated pattern to be inspected, and statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal. A method for inspecting a pattern to be inspected, comprising: comparing a detected image signal with a defect or a defect candidate existing in the pattern to be inspected. 4. An image signal is detected from the repeated pattern to be inspected, and statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal. A method for inspecting a pattern to be inspected, comprising: extracting a feature amount of the pattern to be inspected by comparing the image signal with a detected image signal. 5. The method according to claim 1, wherein the statistical information is a statistical image signal. 6. The method according to claim 1, wherein said detected image signal is a grayscale image signal of a pattern to be inspected, and said statistical information is a statistical grayscale image signal of a pattern to be inspected repeated as said statistical information. Or the inspection method of the pattern to be inspected according to 4. 7. The detected image signal is an image signal indicating an edge position of a pattern to be inspected, and the statistical image signal is a statistical image signal indicating a repeated edge position of the pattern to be inspected as the statistical information. Claim 1
Or the inspection method of the pattern to be inspected according to 2 or 3 or 4. 8. An image signal is detected from the repeated pattern to be inspected, and a statistical image signal represented by an average value or a median value of the repeated pattern to be inspected is generated from the detected image signal. A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in the pattern to be inspected is extracted by comparing an image signal as a reference image signal with the detected image signal. 9. An image signal is detected from a repeated pattern to be inspected, and a statistical image signal represented by an average value or a median value of the repeated pattern to be inspected is generated from the detected image signal. A method for inspecting a pattern to be inspected, comprising extracting a feature amount of the pattern to be inspected by comparing an image signal with a detected image signal as a reference image signal. 10. An image signal is detected from a repetitive pattern to be inspected, and statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal, and the detected repetitive pattern to be inspected is generated. Extracting a defect or a defect candidate existing in the pattern to be inspected by performing a determination process on a difference image obtained by comparing the image signals of the inspection patterns based on the determination criterion obtained based on the generated statistical information. A method for inspecting a pattern to be inspected, characterized in that: 11. An image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged,
From the detected image signal, statistical information represented by the statistical amount of the pattern to be inspected repeated in the mat portion is generated, and the state of the pattern to be inspected in the mat portion is determined using the generated statistical information in the mat portion. A method for inspecting a pattern to be inspected, characterized in that: 12. An image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged,
From the detected image signal, statistical information represented by the statistic of the repeated pattern to be inspected in the mat portion and statistical information represented by the statistic of the repeated pattern to be inspected in the peripheral circuit portion are generated. Quantifying the performance of the pattern to be inspected in the mat portion using the statistical information in the mat portion, and quantifying the performance of the pattern to be inspected in the peripheral circuit portion using the generated statistical information in the peripheral circuit portion. An inspection method of a pattern to be inspected as a feature. 13. An image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged,
From the detected image signal, statistical information represented by the statistic of the pattern to be inspected repeated in the mat portion is generated, and the defect or the defect existing in the inspected pattern in the mat portion is generated using the generated statistical information in the mat portion. A method of inspecting a pattern to be inspected, comprising extracting a defect candidate. 14. An image signal is detected from a pattern to be inspected in which a plurality of chips each having a mat portion and a peripheral circuit portion are arranged,
From the detected image signal, statistical information represented by the statistic of the repeated pattern to be inspected in the mat portion and statistical information represented by the statistic of the repeated pattern to be inspected in the peripheral circuit portion are generated. A defect or defect candidate existing in the pattern to be inspected in the mat portion is extracted using the statistical information in the mat portion, and a defect or defect existing in the pattern to be inspected in the peripheral circuit portion is extracted using the generated statistical information in the peripheral circuit portion. A method of inspecting a pattern to be inspected, comprising extracting a defect candidate. 15. An image signal is detected from a repetitive pattern to be inspected, statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal, and the generated statistical information is used. A method of diagnosing a manufacturing process, comprising quantifying the state of a pattern to be inspected and diagnosing the suitability of a manufacturing process for manufacturing the pattern to be inspected based on the quantified state of the pattern to be inspected. 16. An image signal is detected from a repeated pattern to be inspected, statistical information represented by a statistic of the pattern to be inspected repeated from the detected image signal is generated, and the generated statistical information is used. A process for extracting information on a defect or a defect candidate present in the pattern to be inspected and diagnosing the suitability of a manufacturing process for manufacturing the pattern to be inspected based on the extracted information on the defect or the defect candidate. Process diagnosis method. 17. An image signal is detected from a semiconductor substrate on which a repetitive pattern to be inspected is formed, and statistical information indicated by a statistic of the repetitive pattern to be inspected is generated from the detected image signal. A method of quantifying the quality of a pattern to be inspected using statistical information, and diagnosing the suitability of a manufacturing process condition of the pattern to be inspected based on the quality of the quantified pattern to be inspected to manufacture a semiconductor substrate. Manufacturing method of a semiconductor substrate. 18. An image signal is detected from a semiconductor substrate on which a repeated pattern to be inspected is formed, and statistical information represented by a statistic of the repeated pattern to be inspected is generated from the detected image signal. The statistical information is used to extract information on a defect or defect candidate present in the pattern to be inspected, and based on the extracted information on the defect or defect candidate, a diagnosis is made as to whether the manufacturing process conditions of the pattern to be inspected are appropriate or not. A method for manufacturing a semiconductor substrate, comprising: manufacturing a semiconductor substrate. 19. An image to be registered is linearly interpolated, or a differential image of each of the images is linearly interpolated, and the amount of mismatch between these interpolated images or the linear combination of the amounts of mismatch is minimized. Calculating the amount of image shift with a resolution of less than a pixel, and performing the position alignment of the images by performing linear interpolation, secondary interpolation, or higher-order convolution interpolation on each image based on the obtained amount of position shift. An image positioning method characterized by the following. 20. Linearly interpolating each image to be registered or linearly interpolating a differential image of each of the images, so that the amount of mismatch between these interpolated images or the linear combination of the amount of mismatch is minimized. Is calculated by the wiring logic, and the deviation to be calculated from the obtained deviation calculation data is determined by the program logic with a resolution of less than a pixel. And performing linear interpolation, quadratic interpolation or higher-order convolution interpolation on each of the images based on wiring logic based on the respective images. 21. Linearly interpolating each image to be registered or linearly interpolating a differential image of each of the images, so that the amount of mismatch between these interpolated images or the linear combination of the amounts of mismatch is minimized. Is calculated by the wiring logic, and the deviation to be calculated from the obtained deviation calculation data is determined by the program logic with a resolution of less than a pixel. An image alignment method, wherein the image alignment is performed by performing a wiring logic based on a convolution operation with respect to each of the images. 22. An image signal is detected from the repeated pattern to be inspected, a statistical image signal of the repeated pattern to be inspected is generated from the detected image signal, and the generated statistical image signal is used as a reference image signal. A method for inspecting a pattern to be inspected, wherein a defect or a defect candidate existing in the pattern to be inspected is extracted by aligning and comparing the detected image signal. 23. An image signal is detected from a repeated pattern to be inspected, a statistical image signal of the pattern to be repeated is generated from the detected image signal, and the generated statistical image signal is used as a reference image signal. A method for inspecting a pattern to be inspected, comprising extracting a feature amount of the pattern to be inspected by aligning and comparing the detected image signal. 24. An image signal is detected from a repetitive pattern to be inspected, and statistical information represented by a statistic of the repetitive pattern to be inspected is generated from the detected image signal, and the detected repetitive pattern to be inspected is generated. A defect or defect candidate existing in a pattern to be inspected by performing a determination process based on a determination criterion obtained based on the generated statistical information on a difference image obtained by aligning and comparing image signals of A method for inspecting a pattern to be inspected. 25. An inspection method for inspecting a pattern to be inspected by using an electron beam image obtained by scanning and irradiating an electron beam on a specimen having the pattern to be inspected, wherein the pattern is generated from the specimen by scanning the electron beam. The reflected electrons and secondary electrons are separated to selectively detect the reflected electrons, an electron beam image is created based on the detected reflected electrons, and a pattern to be inspected is formed using the created electron beam image of the reflected electrons. A method for inspecting a pattern to be inspected, characterized by inspecting a pattern. 26. An inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating a sample having the pattern to be inspected with an electron beam, wherein reflected and secondary electrons are separated and detected, A method for inspecting a pattern to be inspected, comprising aligning a plurality of images using an image detected by backscattered electrons. 27. An inspection method for inspecting a pattern to be inspected using an electron beam image obtained by scanning and irradiating a sample on which a pattern to be inspected is repeatedly formed with an electron beam, wherein the pattern is formed in the scanning direction of the electron beam. A method of inspecting a pattern to be inspected, comprising inspecting the pattern to be inspected using an electron beam image obtained from the repeated pattern. 28. A method for inspecting a pattern to be inspected formed on a sample, comprising: a first inspection step of inspecting the pattern to be inspected based on an optical image detected from the pattern to be inspected; Scanning and irradiating the inspection pattern with an electron beam to obtain an electron beam image of the periphery including the inspected portion,
A second inspection step of obtaining detailed information on the inspected portion based on the electron beam image. 29. A method for repeatedly detecting an image signal for a pattern to be inspected repeatedly and inspecting the pattern to be inspected based on the image signals detected continuously, the method comprising: In addition, a method of inspecting a pattern to be inspected, characterized in that continuity of an image is determined using positional deviation information of a past image, and inspection sensitivity at a boundary portion of a discontinuous image is controlled based on the continuity. 30. A method of repeatedly detecting image signals for a pattern to be inspected repeatedly and inspecting the pattern to be inspected based on the image signals detected continuously, wherein the alignment of a plurality of images is performed based on an image of interest. In addition, a method of inspecting a pattern to be inspected, characterized in that continuity of an image is determined using positional deviation information of a past image and a boundary of a discontinuous image is set as a non-inspection area based on the continuity.