JP2001077125A - Hetero junction bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor, having less variations in current gain, and fluctuations in device characteristics is suppressed under application of a voltage during use. SOLUTION: A first conductivity collector layer 2, a second conductivity base layer 3, and a first conductivity emitter layer 4 comprising a semiconductor material, whose inhibition band width is larger than the base layer 3 are provided for lamination structure. Here, at the mesa part of the emitter layer 4 as well as around an electrode 8 of the emitter layer 4, an i-type semiconductor layer 6 having the same inhibition band width with the emitter layer 4 and completely depleted is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor, and more particularly to a heterojunction bipolar transistor having a small variation in current gain and a small variation in characteristics when a voltage is applied.

[0002]

2. Description of the Related Art A conventional heterojunction bipolar transistor has a first conductivity type comprising a collector layer of a first conductivity type, a base layer of a second conductivity type, and a semiconductor layer having a wider bandgap than the base layer. The emitter layer is of a mesa type, and a structure in which a guard ring layer is formed around the mesa type emitter layer is known.

[0003]

In the above-mentioned conventional hetero-junction bipolar transistor, the emitter layer is etched into a mesa type, and a guard ring layer is formed around the mesa type. There is a problem that recombination occurs at the interface between the insulating film on the side surface and the semiconductor layer. Also in this guard ring layer, although the effect provided is seen, there is a problem that recombination occurs to some extent. Further, in this heterojunction bipolar transistor, etching is used to form the guard ring layer. However, since it is difficult to control the etching, there is a problem that the thickness of the guard ring layer varies. .

[0004] Due to such problems, in the conventional heterojunction bipolar transistor, variations in current gain and deterioration with time occur, which has been a serious problem in reliability. Therefore, in order to reduce the variation in the thickness of the guard ring layer, a structure in which the emitter layer is thinned until the entire guard ring portion of the emitter layer is depleted has been proposed (for example, Japanese Unexamined Patent Publication (Kokai) No. HEI 9-26186). 03-053563
Gazette). However, in this structure, since the intrinsic emitter layer is also thin, the barrier at the upper end of the valence band is effectively reduced, and holes are injected back into the emitter layer, resulting in deterioration of characteristics. was there.

As described above, in the conventional heterojunction bipolar transistor, since the guard ring layer does not sufficiently fulfill its function, current gain variation and deterioration over time occur, which is a serious problem in reliability. I was Further, in a heterojunction bipolar transistor having a structure in which the emitter layer is made thin, there is a problem that holes are reversely injected into the emitter layer, and characteristics are deteriorated.

The present invention has been made in view of the above circumstances, and provides a heterojunction bipolar transistor in which variation in current gain is small and variation in device characteristics due to application of a voltage during use is suppressed. The purpose is to:

[0007]

In order to solve the above problems, the present invention employs the following heterojunction bipolar transistor. That is, the heterojunction bipolar transistor according to claim 1 has a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type of a semiconductor material having a larger bandgap than the base layer. In a heterojunction bipolar transistor having a multilayer structure constituted by an emitter layer, a mesa portion of the emitter layer and a periphery of an electrode of the emitter layer have the same forbidden band width as the emitter layer and are completely depleted. It is characterized by comprising an i-type semiconductor layer.

According to a second aspect of the present invention, there is provided a heterojunction bipolar transistor comprising a first conductive type collector layer, a second conductive type base layer, and a semiconductor material having a larger forbidden band width than the base layer. In a heterojunction bipolar transistor having a laminated structure constituted by the emitter layer of the above, a forbidden band width larger than that of the emitter layer and around the mesa portion of the emitter layer and the electrode of the emitter layer are completely depleted. And an i-type semiconductor layer.

According to a third aspect of the present invention, there is provided a heterojunction bipolar transistor, wherein the first conductivity type collector layer, the second conductivity type base layer, and a semiconductor material having a larger forbidden band width than the base layer. In a hetero-junction bipolar transistor having a stacked structure constituted by the above-mentioned emitter layer and a guard ring layer thicker than the emitter layer around a mesa portion of the emitter layer, the guard ring layer is completely depleted. It is characterized by having.

A heterojunction bipolar transistor according to a fourth aspect of the present invention is the heterojunction bipolar transistor according to the first, second or third aspect, wherein a thin i-type emitter layer is provided between the base layer and the emitter layer. It is characterized by:

According to a fifth aspect of the present invention, there is provided a heterojunction bipolar transistor according to the fourth aspect, wherein the i-type emitter layer has a thickness of about 20.
nm or less.

A heterojunction bipolar transistor according to a sixth aspect is characterized in that, in the heterojunction bipolar transistor according to the third, fourth or fifth aspect, a metal film is formed on the guard ring layer.

According to a seventh aspect of the present invention, in the heterojunction bipolar transistor of the third, fourth, fifth or sixth aspect, at least a part of the guard ring layer is made semi-insulating by ion implantation. It is characterized by having.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the heterojunction bipolar transistor of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view showing a heterojunction bipolar transistor according to a first embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a high-concentration n-type GaAs subcollector layer formed on a GaAs (gallium arsenide) substrate;
2 is an n-type GaAs collector layer, 3 is a high concentration p-type GaAs
The base layer 4 is an n-type AlGaAs (aluminum gallium arsenide) emitter layer, and the reference numeral 5 is a high-concentration n-type InGaAs (indium gallium arsenide) sub-emitter layer. These high-concentration n-type GaAs subcollector layers 1 to high-concentration n-type In
The GaAs sub-emitter layer 5 has a laminated structure.

A base electrode 7 is formed on the high-concentration p-type GaAs base layer 3 and a high-concentration n-type InGaAs sub-emitter layer 5 is formed.
An emitter electrode 8 is formed thereon, and a collector electrode 9 is formed on the high-concentration n-type GaAs sub-collector layer 1, and an Au plating wiring layer 10 is connected to each of these electrodes 7-9. The n-type AlGaAs emitter layer 4, the high-concentration n-type InGaAs sub-emitter layer 5, and the emitter electrode 8
Is formed around the i-type AlGaAs layer 6 having the same bandgap as the emitter layer 4.

The i-type AlGaAs layer 6 is completely depleted due to its small thickness, and functions as a guard ring layer for the emitter layer 4. In this structure, the thickness of the intrinsic emitter layer can be set independently of the thickness of the guard ring layer, and a thick intrinsic emitter layer having a thickness of 60 nm or more can be manufactured. Therefore, unlike the thin-layer emitter structure, the barrier at the upper end of the valence band is not effectively reduced, and the back injection of holes into the emitter layer does not increase.

Next, a method of manufacturing the heterojunction bipolar transistor of the present embodiment will be described with reference to FIG. First, as shown in FIG. 2A, using the photoresist film 11 as a mask, the emitter electrode 8 and the high-concentration n-type In
The GaAs sub-emitter layer 5 and the n-type AlGaAs emitter layer 4 are selectively removed.

Next, as shown in FIG. 2B, a silicon oxide film 12 is deposited on the entire surface of the wafer, and only the emitter region is removed by selective etching. Next, an i-type AlGaAs layer 6 having the same bandgap as the emitter layer is grown. Next, as shown in FIG. 2C, the silicon oxide film 12 is removed to remove the unnecessary i-type AlGaAs layer 6, and then the base electrode 7, the unnecessary base layer 3 and the collector electrode 9 are formed. By performing the steps sequentially, the heterojunction bipolar transistor of the present embodiment can be obtained.

As described above, according to the heterojunction bipolar transistor of this embodiment, the n-type AlGaAs
Since the i-type AlGaAs layer 6 having the same bandgap as the emitter layer 4 was formed around the emitter layer 4, the high-concentration n-type InGaAs sub-emitter layer 5, and the emitter electrode 8,
The i-type AlGaAs layer 6 can extend the depletion layer from the semiconductor surface longer than n-type or p-type semiconductors. Therefore, when this i-type AlGaAs layer 6 is used as a guard ring layer of a hetero-junction bipolar transistor, a thick guard ring layer can be realized.

[Second Embodiment] The heterojunction bipolar transistor of this embodiment is different from the heterojunction bipolar transistor of the first embodiment in that
Having the same forbidden band width as that of type AlGaAs emitter layer 4
The point is that an i-type AlGaAs layer having a larger forbidden band width than the emitter layer 4 is used instead of the type AlGaAs layer 6.

The method of manufacturing the heterojunction bipolar transistor of the present embodiment is different from the method of manufacturing the heterojunction bipolar transistor of the first embodiment described above in that the same bandgap as that of the n-type AlGaAs emitter layer 4 is used. Instead of growing the i-type AlGaAs layer 6 having
The point is that an i-type AlGaAs layer having a larger bandgap than the type-AlGaAs emitter layer 4 is grown.

Since the i-type AlGaAs layer is thin, it is completely depleted, and has a larger forbidden band width than the emitter layer 4. Therefore, the i-type AlGaAs layer has the same structure as that of the first embodiment. It can serve as a more complete guard ring layer for the emitter layer 4 as compared to a junction bipolar transistor.

Third Embodiment FIG. 3 is a sectional view showing a heterojunction bipolar transistor according to a third embodiment of the present invention. In FIG. 3, a high-concentration n-type GaAs subcollector layer is formed on a GaAs substrate. 1, n-type GaAs collector layer 2, high-concentration p-type GaAs base layer 3, n-type AlGaAs
The s-emitter layer 4 and the high-concentration n-type InGaAs sub-emitter layer 5 are sequentially formed to form a laminated structure.
Around the mesa portion of the aAs emitter layer 4, a completely depleted guard ring layer 21 having a thickness of 60 nm or more is formed.

In this heterojunction bipolar transistor, the intrinsic emitter layer 4 also has a thickness of 60 nm or more, so that the barrier at the upper end of the valence band is not effectively reduced unlike the thin-layer emitter structure. Back injection of holes into the emitter layer does not increase.

[Fourth Embodiment] FIG. 4 is a process diagram showing a method for manufacturing a heterojunction bipolar transistor according to a fourth embodiment of the present invention. In this manufacturing method, first, FIG.
As shown in FIG. 3A, the emitter electrode 8 and the high-concentration n-type InGaAs sub-emitter layer 5 are selectively removed using the photoresist film 11 as a mask.

Next, as shown in FIG. 4B, a metal film 13 is deposited on the entire surface of the wafer. At this time, the high-concentration n-type In
Since the side surface of the GaAs sub-emitter layer 5 is etched, the metal film 13 is deposited in a self-aligned manner with respect to the emitter electrode 8.

Next, as shown in FIG. 4C, a photoresist film 11 having a larger area than the emitter electrode 8 is formed in the emitter region. Next, as shown in FIG. 4D, unnecessary portions of the metal film 13 and the n-type AlGaAs emitter layer 4 are selectively removed using the photoresist film 11 as a mask.

Finally, as shown in FIG. 4E, a base electrode 7 and a collector electrode are formed. In this way,
A heterojunction bipolar transistor having the metal film 13 on the thick guard ring layer 21 can be manufactured.
By applying an arbitrary voltage to the metal film 13, the thick guard ring layer 21 can be completely depleted.

[Fifth Embodiment] FIG. 5 is a process chart showing a method for manufacturing a heterojunction bipolar transistor according to a fifth embodiment of the present invention. In this manufacturing method, first, FIG.
As shown in FIG. 3A, the emitter electrode 8 and the high-concentration n-type InGaAs sub-emitter layer 5 are selectively removed using the photoresist film 11 as a mask.

Next, as shown in FIG. 5B, a silicon oxide film 12 is deposited on the entire surface of the wafer, and only the region of the emitter electrode 8 is opened. Using the silicon oxide film 12 and the emitter electrode 8 as a mask, ion implantation 22 of boron or the like is performed. At this time, as shown in FIG.
A semi-insulated guard ring layer 23 damaged by boron or the like is formed around the mesa portion of the As emitter layer 4.

Next, a silicon oxide film 12 is deposited on the entire surface of the wafer, and thereafter, the unnecessary n-type AlGaAs emitter layer 4 is selectively removed from the photoresist film 11 including the guard ring layer 23. Finally, as shown in FIG. 5D, a base electrode 7 and a collector electrode are formed. Thus, a heterojunction bipolar transistor having the thick semi-insulating guard ring layer 23 can be manufactured.

Sixth Embodiment FIG. 6 is a sectional view showing a heterojunction bipolar transistor according to a sixth embodiment of the present invention. In FIG. 6, a high-concentration n-type GaAs subcollector is formed on a GaAs substrate. Layer 1, n-type GaAs collector layer 2, high concentration p-type GaAs base layer 3, thin i-type Al
A GaAs emitter layer 24, an n-type AlGaAs emitter layer 4, and a high-concentration n-type InGaAs sub-emitter layer 5 are sequentially formed to form a laminated structure.

The base electrode 7 is formed on the thin i-type AlGaAs emitter layer 24, the emitter electrode 8 is formed on the high-concentration n-type InGaAs sub-emitter layer 5, and the high-concentration n-type GaAs is formed.
A collector electrode 9 is formed on each of the s subcollector layers 1. This base electrode 7 is made of a thin i-type AlGa
By baking the As emitter layer 24, a high concentration p-type G
A good contact with the aAs base layer 3 can be formed.

An i-type AlGaAs layer 6 having the same forbidden band width as the emitter layer 4 is formed around the n-type AlGaAs emitter layer 4, the high-concentration n-type InGaAs sub-emitter layer 5, and the emitter electrode 8. . Also, thin i
The type AlGaAs emitter layer 24 is preferably thin enough not to adversely affect the traveling of electrons, for example, 20 nm.
The following is preferred.

Therefore, the thin i-type AlGaAs emitter layer 24 around the mesa portion of the emitter layer 4 is completely depleted, and functions as a guard ring layer for the emitter layer 4. In this structure, the intrinsic emitter layer has a thickness of 60 nm or more, so that the barrier at the upper end of the valence band does not decrease effectively unlike the thin-layer emitter structure. No back-injection occurs.

Furthermore, since a completely depleted thin i-type AlGaAs emitter layer 24 exists not around the regrowth interface of the i-type AlGaAs layer 6 but around the mesa portion of the emitter-base junction, the electron / positive Hole recombination can be effectively suppressed.

Seventh Embodiment The heterojunction bipolar transistor of this embodiment is different from the heterojunction bipolar transistor of the sixth embodiment in that
Having the same forbidden band width as that of type AlGaAs emitter layer 4
The point is that an i-type AlGaAs layer having a larger forbidden band width than the emitter layer 4 is used instead of the type AlGaAs layer 6.

The i-type AlGaAs layer is completely depleted due to its small thickness, and has a larger forbidden band width than the emitter layer 4. Therefore, the i-type AlGaAs layer has a larger band gap than the heterojunction bipolar transistor of the sixth embodiment. This i-type A
The lGaAs layer can serve as a more complete guard ring layer for the emitter layer 4.

[Eighth Embodiment] FIG. 7 is a sectional view showing a heterojunction bipolar transistor according to an eighth embodiment of the present invention. In FIG. 7, a high-concentration n-type GaAs subcollector is formed on a GaAs substrate. Layer 1, n-type GaAs collector layer 2, high concentration p-type GaAs base layer 3, thin i-type Al
A GaAs emitter layer 24, an n-type AlGaAs emitter layer 4, and a high-concentration n-type InGaAs sub-emitter layer 5 are sequentially formed to form a laminated structure.

The base electrode 7 is formed on the thin i-type AlGaAs emitter layer 24, the emitter electrode 8 is formed on the high-concentration n-type InGaAs sub-emitter layer 5, and the high-concentration n-type GaAs is formed.
A collector electrode 9 is formed on each of the s subcollector layers 1. This base electrode 7 is made of a thin i-type AlGa
By forming the As emitter layer 24, a high-concentration p-type G
A good contact with the aAs base layer 3 can be formed.

A guard ring layer having a thickness of 60 nm or more, which is completely depleted, is formed around the n-type AlGaAs emitter layer 4. Also, thin i-type Al
The GaAs emitter layer 24 is preferably thin enough not to adversely affect the traveling of electrons, and is preferably, for example, 20 nm or less.

Therefore, the thin i-type AlGaAs emitter layer 24 around the mesa portion of the emitter layer 4 is completely depleted, and functions as a guard ring layer for the emitter layer 4. In this structure, the intrinsic emitter layer has a thickness of 60 nm or more, so that the barrier at the upper end of the valence band does not decrease effectively unlike the thin-layer emitter structure. No back-injection occurs.

Further, since a completely depleted thin i-type AlGaAs emitter layer 24 exists not around the regrowth interface of the i-type AlGaAs layer 6 but around the mesa portion of the emitter-base junction, the electron / positive layer is formed. Hole recombination can be effectively suppressed.

The embodiments of the heterojunction bipolar transistor of the present invention have been described above with reference to the drawings. However, the specific configuration is not limited to the present embodiment, and is not departed from the gist of the present invention. It is possible to change the design.

[0045]

As described above, according to the heterojunction bipolar transistor of the first or second aspect of the present invention, the i-type semiconductor layer has a larger thickness than the n-type semiconductor layer or the p-type semiconductor layer. The extension of the depletion layer from the surface can be lengthened. Therefore, when this i-type semiconductor layer is used as a guard ring layer, the thickness of the guard ring layer is determined by the thickness of the i-type semiconductor layer, and the controllability of the thickness of the guard ring layer is greatly improved. be able to. Therefore, variation in current gain can be significantly reduced.

When the regrown i-type semiconductor layer is used for the guard ring layer, the guard ring layer thickness and the emitter layer thickness can be set independently, so that the guard ring thickness and the emitter layer thickness can be reduced. Optimization can be done independently.
Further, since the guard ring layer can be completely depleted even with a thick emitter structure, back injection of holes into the emitter layer can be suppressed.

According to the heterojunction bipolar transistor of the third aspect, a guard ring layer thicker than the emitter layer is provided around the mesa portion of the emitter layer, and the guard ring layer is completely depleted. The guard ring layer can function as a more complete guard ring layer for the emitter layer. Therefore, variation in current gain can be significantly reduced.

According to the heterojunction bipolar transistor of the fourth aspect, since the thin i-type emitter layer is provided between the base layer and the emitter layer, the i-type emitter layer is formed around the mesa portion of the emitter-base junction. Instead of the type semiconductor layer regrowth interface, a completely depleted thin i-type semiconductor layer is present, and electron-hole recombination can be more effectively suppressed.

As described above, it is possible to realize a heterojunction bipolar transistor in which variation in current gain is small and fluctuation in device characteristics due to voltage application during use is suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a heterojunction bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing a heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a heterojunction bipolar transistor according to a third embodiment of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a heterojunction bipolar transistor according to a fourth embodiment of the present invention.

FIG. 5 is a process chart showing a method for manufacturing a heterojunction bipolar transistor according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a heterojunction bipolar transistor according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a heterojunction bipolar transistor according to an eighth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 high-concentration n-type GaAs subcollector layer 2 n-type GaAs collector layer 3 high-concentration p-type GaAs base layer 4 n-type AlGaAs emitter layer 5 high-concentration n-type InGaAs subemitter layer 6 i-type AlGaAs layer 7 base electrode 8 emitter electrode 9 Collector electrode 10 Au plated wiring layer 11 Photoresist film 12 Silicon oxide film 21 Guard ring layer 22 Ion implantation 23 Guard ring layer 24 Thin i-type AlGaAs emitter layer

Claims (7)

[Claims] 1. A laminate comprising a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type made of a semiconductor material having a larger bandgap than the base layer. A heterojunction bipolar transistor having a structure, comprising, around a mesa portion of the emitter layer and an electrode of the emitter layer, an i-type semiconductor layer having the same bandgap as the emitter layer and being completely depleted. A heterojunction bipolar transistor characterized by the above-mentioned. 2. A laminate comprising a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer made of a semiconductor material having a larger bandgap than the base layer. In a heterojunction bipolar transistor having a structure, an i-type semiconductor layer having a larger bandgap than the emitter layer and being completely depleted is provided around a mesa portion of the emitter layer and an electrode of the emitter layer. A heterojunction bipolar transistor characterized by the above-mentioned. 3. A laminate comprising a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type made of a semiconductor material having a larger bandgap than the base layer. A heterojunction bipolar transistor having a structure and a guard ring layer thicker than the emitter layer around a mesa portion of the emitter layer, wherein the guard ring layer is completely depleted. Transistor. 4. The heterojunction bipolar transistor according to claim 1, further comprising a thin i-type emitter layer between said base layer and said emitter layer. 5. The thickness of the i-type emitter layer is approximately 20 nm.
5. The heterojunction bipolar transistor according to claim 4, wherein the value is equal to or less than the above. 6. The hetero-junction bipolar transistor according to claim 3, wherein a metal film is formed on the guard ring layer. 7. The heterojunction bipolar transistor according to claim 3, wherein at least a part of the guard ring layer is made semi-insulating by ion implantation.