JP2001077050A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form CoSi2 films on source/drain diffused layers without causing a deterioration of the electrical characteristics of a semiconductor device even though a miniaturization of an element is progressed. SOLUTION: Arsenic ions are implanted in a silicon substrate 11 in a state that a substrate temperature is kept at a low temperature of 100 deg.C or lower and thereafter, a heat treatment is performed to form source/drain diffused layers 16 in the substrate 11. Then after cobalt films 19 are respectively deposited on the layers 16, a heat treatment is performed to form CoSi2 films 23 on the layers 16. At this time, this heat treatment is performed by two times. The first heat treatment is performed at a temperature of 400 deg.C or higher to 500 deg.C or lower to form CoSi films 22 and the following heat treatment is performed at a temperature of 800 deg.C or higher to 900 deg.C or lower to change the films 22 into the films 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a step of forming a silicide film.

[0002]

2. Description of the Related Art In recent years, semiconductor devices which have been miniaturized, especially MOS-type FET devices intended for high-speed operation,
In order to reduce the parasitic resistance of the device, it is necessary to use a so-called salicide technique in which a metal silicide is self-aligned onto the surfaces of the source / drain diffusion layers and the gate electrode (polysilicon film). As a metal silicide, cobalt disilicide (CoSi ₂ ) has come to be widely used, especially in a generation having a gate length of 0.18 μm or less.

FIG. 11 is a process sectional view showing a method for manufacturing a MOS type FET device using a conventional cobalt salicide process. First, as shown in FIG.
00) An element isolation insulating film (silicon oxide film) 62 and a p-type well diffusion layer 63 are formed on an n-type silicon substrate 61 having a plane orientation.

[0004] Next, as shown in FIG. 11 (b), after forming a gate oxide film 64, an undoped polysilicon film is deposited thereon, and is patterned to form a gate electrode 6.
5 is formed. Next, as shown in FIG. 3B, an n-type shallow source / drain diffusion layer (extension) 66 is formed by arsenic ion implantation and heat treatment such as RTA.

Next, as shown in FIG. 11C, a silicon nitride film is deposited on the entire surface, and anisotropic etching such as RIE is performed on the silicon nitride film to form a gate sidewall insulating film (spacer).
A silicon nitride film 67 is formed.

Next, as shown in FIG. 11C, arsenic ions are implanted using the silicon nitride film 67 and the gate electrode 65 as a mask to form an n-type deep source / drain diffusion layer 68.

After that, arsenic in the source / drain diffusion layers 66 and 67 is activated by a heat treatment such as RTA. At this time, arsenic introduced into the gate electrode 65 by ion implantation at the time of forming the source / drain diffusion layers 66 and 67 is also activated. As a result, the resistance of the gate electrode 65 decreases to such a degree that it can be used as an electrode.

Then, after removing the silicon oxide film such as the natural oxide film and the chemical oxide film remaining on the surface of the source / drain diffusion layer 68 and the gate electrode 65 using dilute hydrofluoric acid or the like, FIG. As shown in (), a cobalt film 69 is deposited on the entire surface.

Next, as shown in FIG.
The surface of the source / drain diffusion layer 68 and the surface of the gate electrode 65 react with the cobalt film 69 by lamp annealing at about 550 ° C. to form a cobalt monosilicide (CoSi) film 70. At this time, the cobalt film 69 on the element isolation insulating film (SiO ₂ film) 62 and the silicon nitride film 67 does not react and remains in the state of the cobalt film.

Finally, as shown in FIG. 11 (f), after removing the unreacted cobalt film 69 using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide, a lamp at about 700 to 850 ° C. The annealing changes the cobalt monosilicide (CoSi) film 70 into a cobalt disilicide (CoSi ₂ ) film 71 having a lower resistance.

In recent years, in the manufacture of fine transistors, especially n-channel MOS FET devices for high-speed logic, the so-called short channel effect, which is a phenomenon in which device characteristics are degraded with a reduction in gate length, is suppressed. In addition, formation of a high concentration and shallow source / drain diffusion layer has been required.

In forming the source / drain diffusion layers of this type of MOS type FET device, arsenic ions as described in the step of FIG. 11C are used instead of phosphorus ion implantation which has been widely used in the past. Injection has been used. The reason is that arsenic has a small diffusion coefficient in silicon and easily forms a high concentration diffusion layer.

FIG. 12 shows an arsenic concentration distribution (impurity concentration profile) in the depth direction of a diffusion layer formed by arsenic ion implantation. This means that a 10 nm thick silicon oxide film is formed on a (100) oriented silicon substrate,
Acceleration energy 50 keV, dose 5 × 10 ¹⁵ cm ^-3
After the arsenic ions are implanted into the silicon substrate through the silicon oxide film under the conditions described above, impurity activation is performed by lamp annealing at 1000 ° C. for 20 seconds.

From the figure, it is found that the impurity concentration is 5 × 10 ¹⁷ cm ^-3.
It can be seen that a shallow diffusion layer is formed where the depth decreases to a depth of about 120 nm from the substrate surface.

By the way, in the arsenic diffusion layer formed by the conventional method, as shown in FIG. 13A, the surface portion of the silicon substrate is made amorphous by the implanted arsenic, and the (thermal) energy by ion implantation is increased. As a result, the temperature of the surface portion of the silicon substrate which has become amorphous increases, and silicon recrystallization occurs near the interface between the amorphous silicon region and the crystalline silicon region.

During this recrystallization, minute crystal defects are formed near the interface between the amorphous silicon region and the crystalline silicon region. As shown in FIG. 13B, when the amorphous silicon is recrystallized in the subsequent impurity activity annealing (lamp annealing at 1000 ° C. for 20 seconds in the above-described example) step, as shown in FIG. 111) It grows to a crystal defect of the plane orientation. That is, the above-described conventional method of forming a diffusion layer by arsenic ion implantation has a problem of causing crystal defects in the diffusion layer. FIG. 14 shows a TEM photograph of a cross section of the arsenic diffusion layer formed under the above-described conditions. .
From the figure, it was found that a crystal defect of (111) plane orientation occurred at a depth of about 80 to 90 nm from the substrate surface.

Even if such crystal defects occur in the source / drain diffusion layers, the MOS type FE as shown in FIG.
In the case of the T element, since the crystal defect 72 is sufficiently separated from the junction surface between the source / drain diffusion layer 68 and the well diffusion layer 63 (about 30 nm), no extreme junction failure occurs.

However, in order to reduce the parasitic resistance of the MOS type FET device, a cobalt silicide film 7 is formed on the surface of the source / drain diffusion layer 68 as shown in FIG.
When 1 is formed in a self-aligned manner, the cobalt silicide film 71 may be formed so as to penetrate deep into the substrate due to the presence of the crystal defect 72. As a result, FIG.
As shown in (1), the cobalt silicide film 71 may reach a position deeper than the position of the crystal defect (about 100 nm from the substrate surface).

As described above, when the cobalt silicide film 71 approaches the junction between the source / drain diffusion layer 68 and the well diffusion layer 63, the depletion layer extending from the junction becomes a diffusion of cobalt atoms extending at or near the cobalt silicide film 71. Layer. As a result, there arises a problem that a junction leak current increases and a junction failure occurs. This is because the process conditions of the source / drain diffusion layers forming the cobalt silicide film have not been optimized conventionally.

Further, as shown in FIG.
Process of silicidation reaction between silicon and silicon (1st RTA
Step) and the CoSi film shown in FIG.
Si _TwoAbout thermal process (2nd RTA process) to change into film
However, it can be said that it has not been optimized in the past.

One of the reasons is that the crystal defects existing in the source / drain diffusion layers, the cobalt film and the silicon region (the source / drain diffusion layers, the polysilicon film serving as the gate electrode, etc.) Due to the silicon oxide film such as a natural oxide film present at the interface between the cobalt silicide film and the silicon region, the unevenness at the interface between the cobalt silicide film and the silicon region becomes large. Was not seen.

For this reason, the annealing temperature in the first RTA step is in a temperature range (400 to 600 ° C.) in which the cobalt film reacts with the silicon region to form a CoSi film, and the second RTA
The annealing temperature of the process is the same as that of Co formed in the first RTA process.
The temperature was selected to be sufficient (650 ° C. or higher) to completely change the Si film into a CoSi ₂ film, but further optimization has not been performed much.

However, according to the study of the present inventors, the first
In the RTA process, depending on the annealing temperature, the morphology of the cobalt silicide film, particularly the flatness of the interface between the silicide film and the silicon region changes (the lower the temperature, the better the flatness), and in the second RTA process,
Differences in the annealing temperature and the rate of temperature rise change the manner in which cobalt atoms spread in the silicon region below the silicide film. (The diffusion of cobalt atoms spreading from the silicide film at higher temperatures and higher rates of temperature is suppressed. )
It turns out that.

Therefore, the problems described so far,
In particular, when the crystal defects remaining in the source / drain diffusion layers are reduced, the effect of optimizing the conditions of the first and second RTA processes is increased.

Furthermore, the film forming temperature (substrate temperature) of the cobalt film shown in FIG. 11D has not been optimized conventionally. Hereinafter, this point will be described in detail.

The cobalt film reacts with the silicon region by annealing in the salicide process to form a cobalt silicide film, but has a feature that it does not react with the silicon oxide film at all.

For this reason, in FIG. 11D, before the cobalt film 69 is deposited, the surface of the source / drain diffusion layer 68 and the surface of the gate electrode 65 remain due to the treatment with a chemical such as dilute hydrofluoric acid. After removing a silicon oxide film such as a natural oxide film, a cobalt film 69 is formed.

However, even after the removal of the natural oxide film with dilute hydrofluoric acid or the like, the silicon substrate 61 is conveyed in the atmosphere even if it is quickly introduced into a vacuum apparatus for forming the cobalt film 69 by sputtering. In the meantime, a natural oxide film having a thickness of about several angstroms grows.

This slight natural oxide film is a cobalt film 6
9 is mixed by the kinetic energy of the cobalt atoms at the time of the sputter formation, and the thickness 2 is formed at the interface between the sputter-formed cobalt film 69 and the silicon regions 65 and 68.
An amorphous layer of cobalt, silicon and silicon oxide of about nm is formed.

Therefore, the cobalt film 6 is heat-treated.
9 reacts with the underlying silicon regions 65 and 68,
At the interface between the cobalt film 69 and the silicon regions 65 and 68, a cobalt silicide film is formed.

However, in the silicon region where the growth rate of the native oxide film is high, such as on the source / drain diffusion layer 68 and the gate electrode 65 into which n-type impurity atoms are introduced at a high concentration, room temperature sputtering is performed. As described above, when the substrate temperature is low, the cobalt film 69 and the silicon regions 65, 68
Insufficient energy to mix the interface with the interface.

Therefore, a region where the reaction between the cobalt film 69 and the silicon regions 65 and 69 is inhibited is partially formed. As a result, as shown in FIG. 17, when the gate length is reduced, a problem arises that the sheet resistance of the gate electrode 65 increases. A similar problem also occurs in the source / drain diffusion layer 69.

On the other hand, when the substrate temperature at the time of forming the cobalt film is increased, the following problem occurs. For example, when the thickness of the deposited cobalt film is 16 nm and the temperature of the silicon substrate at the time of depositing the cobalt film is 400 ° C., as shown in the scanning electron microscope (SEM) photograph of FIG. Agglomeration of the cobalt film occurs on the surface of the silicon oxide film which is the film.

When the cobalt salicide process is performed under the condition where such agglomeration occurs, as shown in FIG. 19, the cobalt agglomerated on the element isolation insulating film (SiO ₂ film) 62 around the source / drain diffusion layer 68. The membrane 69 '
The cobalt silicide film 71 'is gathered at the boundary with the source / drain diffusion layer 68, and the thickness of the cobalt silicide film 71' at the boundary with the element isolation insulating film (SiO ₂ film) 62 is larger than other portions.

Such an element isolation insulating film (SiO ₂ film)
By increasing the thickness of the cobalt silicide film 69 at the boundary with the element 62, the penetration of the cobalt silicide film 71 at the boundary with the element isolation insulating film (SiO ₂ film) 62 increases.

The large bite of the cobalt silicide film 71 caused by such a cause causes the occurrence of a bonding failure similarly to the bite of the cobalt silicide film 71 caused by the crystal defect caused by the above-described ion implantation.

In the conventional method shown in FIG.
The cobalt film 69 is exposed to the air after the step of forming the cobalt film 69 in FIG. 1D, and the oxygen mixed in the atmosphere of the heat treatment step for silicidation in FIG. The surface and grain boundary of 69, and the interface between the cobalt film 69 and the silicon region values 65 and 68 are oxidized. Therefore, there is a problem that formation of a uniform cobalt silicide film is hindered and sheet resistance increases.

In order to solve such a problem, a method of forming a cobalt silicide film using a titanium nitride film or a titanium film as a cap film is often used.

FIG. 20 is a process sectional view of a method of forming a cobalt silicide film using a titanium nitride film as a cap film (titanium nitride cap). In the titanium nitride cap, a cobalt film 82 is formed on a silicon substrate 81, a titanium nitride film 83 is formed thereon, and then a cobalt silicide (CoSi ₂ ) film 84 is formed by heat treatment.

If a titanium nitride cap is used, the surface and grain boundaries of the cobalt film 82, the cobalt film 82 and the silicon substrate 8
Oxidation at the boundary with 1 can be suppressed, so that an increase in the sheet resistance of the CoSi ₂ film 84 can be suppressed.

However, the cobalt film 82 and the silicon substrate 8
1 (Co + Si → CoSi) _xIn the case of Silico
Film on the substrate 81 (cobalt silicide formation area)
Stress is applied and the silicidation reaction proceeds unevenly
Increase the junction leakage current.
Occur.

FIG. 21 is a process sectional view showing a method of forming a cobalt silicide film using a titanium film as a cap film (titanium cap). In the titanium cap, a cobalt film 92 is formed on a silicon substrate 91, a titanium film 93 is formed thereon, and then a cobalt silicide (CoSi ₂ ) film 94 is formed by heat treatment.

The titanium cap is characterized in that oxidation of the surface and grain boundaries of the cobalt film 92 and the interface between the cobalt film 92 and the silicon substrate 91 can be suppressed, and unlike the titanium nitride cap, the film stress is not large. Have.

Further, the titanium cap has the following effects. Titanium has a strong reducing power. Therefore, when the titanium atoms in the titanium film 93 diffuse to the interface between the cobalt film 92 and the silicon substrate 91, the titanium atoms reduce a silicon oxide film such as a natural oxide film remaining at the interface between the cobalt film 92 and the silicon substrate 91. I do.

As a result, a substance that hinders the reaction between the cobalt film 92 and the silicon substrate 91 is eliminated, and a uniform cobalt silicide film 94 can be formed, thereby suppressing the occurrence of a junction leak current.

When a titanium cap is used, a heat treatment for reacting the cobalt film 92 and the silicon substrate 91 causes the cobalt and titanium to be removed at the interface between the titanium film 93 and the cobalt film 92 as shown in FIG. An alloy layer 95 is formed by the alloying reaction of the above, and the amount of cobalt contributing to the silicide reaction is reduced, and the thickness of the completed cobalt silicide film 94 is reduced. Such inconvenience can be solved by increasing the amount of deposited cobalt by the amount lost by the alloy layer 95 in advance.

However, when a titanium cap is used, if the heat treatment for reacting the cobalt film 92 with the silicon substrate 91 is performed in a nitrogen atmosphere, the nitridation reaction of the titanium film 93 proceeds from the surface.

As a result, the titanium film 93 is in a state of competition between the nitriding reaction and the alloying reaction, and the thickness of the completed cobalt silicide film 94 varies due to a slight variation in the heat treatment temperature, or the nitriding reaction occurs. Due to the film stress of the titanium nitride film formed by
Since a large film stress is applied to the (silicide formation region) and the silicidation reaction proceeds non-uniformly, a problem that the junction leakage current increases may occur.

The titanium film 93 has a characteristic that it can reduce a silicon oxide film and is very easily oxidized by oxygen present in the atmosphere. Therefore, the surface of the titanium film 93 is easily oxidized by oxygen in the air when these are exposed to the air after the deposition of the cobalt film 92 and the titanium film 93, and oxygen mixed in a thermal process atmosphere for reacting cobalt and silicon. Will be done.

Although the oxide of titanium (TiO ₂ ) is easily formed in this way, it is very difficult to remove the titanium oxide once formed. Therefore, when the titanium cap is applied to the process shown in FIG.
When the unreacted cobalt film 69 is selectively removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide described in (e), the titanium film, titanium nitride film, and titanium-cobalt alloy film can be simultaneously removed by etching. However, titanium oxide remains because it cannot be completely removed by etching.

As a result, an unnecessary conductive film such as a cobalt film or a titanium film remains in a region covered with the titanium oxide, and a short circuit may occur between elements or between a source / drain / gate. .

Therefore, in the case of using a structure in which a titanium film is deposited on a cobalt film, it is necessary to control the temperature of the thermal process for silicidation with high precision. To prevent oxidation before the film is selectively removed, minimize the elapsed time from film formation to heat treatment, reduce the amount of oxygen in the storage atmosphere, reduce the amount of residual oxygen in the heat treatment atmosphere, etc. , The accuracy of the process must be improved. However, these solutions are problematic in that they increase manufacturing costs.

[0053]

SUMMARY OF THE INVENTION As described above, the present inventors have developed an MO using a conventional cobalt salicide process.
It has been clarified that the manufacturing method of the S-type FET device has some important steps that have not been optimized, and as a result, problems such as an increase in junction leakage current will occur when miniaturization is advanced. I made it.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a method in which even if the element is miniaturized, the electrical characteristics are not deteriorated and the silicide is formed on the impurity diffusion region. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a film.

[0055]

[Means for Solving the Problems] [Structure] In order to achieve the above object, in the first method for manufacturing a semiconductor device according to the present invention (claim 1), the temperature of the silicon region is maintained at -100 ° C or lower. Forming an impurity diffusion region by implanting impurity ions into the silicon region and then performing a heat treatment on the silicon region, and forming a silicide film on the surface of the impurity diffusion region. It is characterized by the following.

A preferred embodiment of the first method for manufacturing a semiconductor device according to the present invention is as follows.

(1) The silicide film is a CoSi ₂ film.

(2) In the above (1), the step of forming the CoSi ₂ film includes the step of forming a cobalt film on the surface of the impurity diffusion layer and the step of reacting the cobalt film with the impurity diffusion layer by a first heat treatment. Forming a CoSi film;
Reacting the CoSi film with the impurity diffusion layer by the heat treatment to convert the CoSi film into a CoSi ₂ film.

(3) In the above (3), the temperature of the first heat treatment is 400 ° C. or more and 500 ° C. or less.

(4) In the above (3), the temperature of the second heat treatment is 800 ° C. or more and 900 ° C. or less.

(5) In the above (3), the rate of temperature rise in the second heat treatment is 30 ° C./sec or more.

(6) In the above (1) to (5), the silicon region is a silicon substrate, and the impurity diffusion region is at least one of a source diffusion layer and a drain diffusion layer.

(7) The impurity diffusion layer includes a polysilicon film doped with an impurity as a gate electrode, in addition to that described in (6) above.

Further, in a second method of manufacturing a semiconductor device according to the present invention (claim 8), there is provided a step of forming a metal film in contact with a predetermined region of a silicon region; Reacting with a film to form a silicide film, setting the temperature of the silicon region at 100 ° C. or higher and lower than the temperature at which the metal film starts to aggregate, and forming the metal film by a sputtering method. It is characterized by doing.

A preferred embodiment of the second method for manufacturing a semiconductor device according to the present invention is as follows.

(1) The metal film is a cobalt film, a nickel film or a palladium film, and the silicide film is a cobalt silicide film, a nickel silicide film or a palladium silicide film.

(2) Keep the temperature of the silicon region at 100 ° C. or higher2
The temperature is set to 50 ° C. or lower, and the metal film is formed by a sputtering method.

In a third method of manufacturing a semiconductor device according to the present invention (claim 11), there is provided a step of forming a cobalt film in contact with a predetermined region of a silicon region, wherein a titanium film and a titanium nitride film are formed on the cobalt film. Are sequentially formed, and a step of reacting a predetermined region of the silicon region with the cobalt film by heat treatment to form a cobalt silicide film.

In the method of manufacturing the second semiconductor device according to the present invention and its preferred embodiment, and in the method of manufacturing the third semiconductor device according to the present invention, the silicon region is a silicon substrate, and the predetermined regions are a source diffusion layer and a drain layer. At least one. The predetermined region may also include a polysilicon film into which an impurity as a gate electrode has been introduced.

[Operation] According to the present invention (claim 1), the impurity diffusion region is formed by ion implantation and heat treatment while the silicon region is kept at -100 ° C. or lower, so that the silicide film bites. It is possible to effectively prevent the generation of crystal defects in the impurity diffusion region which causes the above. This point will be further described in the embodiment section. Therefore, according to the present invention, even if the element is miniaturized, the electrical characteristics such as bonding failure do not deteriorate,
A silicide film can be formed on a silicon region.

According to the present invention (claim 8), by increasing the temperature of the silicon region to 100 ° C. or more and forming a metal film serving as a metal supply source of the silicide film, the sheet resistance can be effectively increased. Can be prevented. This point will be further described in the embodiment section. Therefore, according to the present invention, it is possible to form a silicide film on a silicon region without deteriorating electrical characteristics such as an increase in sheet resistance even if the element is miniaturized.

Further, according to the present invention (claim 11), a cap film of a titanium film and a titanium nitride film is used as a cap film of a cobalt film serving as a cobalt supply source of the cobalt silicide film. Can solve the problem of the conventional method using a single-layer film of a titanium film or a titanium nitride film. This point will be further described in the embodiment section. Therefore, according to the present invention, it is possible to form a silicide film on a silicon region without deteriorating electrical characteristics such as an increase in sheet resistance even if the element is miniaturized. This point will be further described in the embodiment section.

[0073]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) As described in the section of the prior art, in the method of forming a diffusion layer using ion implantation, particularly the method of forming a high concentration source / drain diffusion layer using arsenic, Crystal defects of (111) plane orientation are generated in the source / drain diffusion layers.

This crystal defect is formed at the interface between the amorphous region and the crystalline silicon region when the amorphous silicon region on the substrate surface is recrystallized by the implantation energy (thermal energy) during the ion implantation. And grows during subsequent annealing for impurity activation.

Therefore, as shown in FIG. 1, by cooling the substrate temperature of the silicon substrate to 100 ° C. or less at the time of ion implantation, the amorphous region on the surface of the substrate which has become amorphous by the implantation of arsenic ions is recrystallized. If the thermal energy for the activation is not obtained, it is possible to suppress the generation of minute crystal defects immediately after the ion implantation, and it is possible to suppress the occurrence of (111) even after annealing for impurity activation. No crystal defects in the plane orientation are formed.

The reason for setting the substrate temperature to a low temperature of -100 ° C. or less is that when the temperature was -100 ° C. or less, it was found that the defect density by ion implantation was 0% in the range of the measurement accuracy. is there.

In a state where the formation of crystal defects caused by such ion implantation is suppressed, the improvement of the flatness of the silicide-silicon interface by optimizing the heat treatment step of silicidation has a great significance.

In the salicide process using cobalt, Co + Si → CoSi explained in FIG.
The flatness of the silicide film changes depending on the annealing temperature in the first RTA process for causing a reaction.

According to the experiments by the present inventors, in the case of high-temperature annealing in which the annealing temperature in the first RTA step exceeds 550 ° C., the reaction between the cobalt film and the silicon substrate occurs rapidly, and the annealing is performed in a short time of about 30 seconds. Even it has been found that a portion of the CoSi film changes to CoSi ₂ , degrading the morphology of the film.

In the first RTA step, it is also known that the morphology of the cobalt silicide film is improved as the annealing temperature is lowered, even in a temperature range of 550 ° C. or lower where CoSi ₂ is not formed.

However, if the annealing temperature in the first RTA step is lower than 400 ° C., the deposited cobalt film does not completely react with silicon in the short annealing time of about 30 seconds, and as shown in FIG. Since the cobalt film deposited on the source / drain diffusion layer is also etched during the selective etching process using the mixed solution of sulfuric acid and hydrogen peroxide, a problem occurs that a desired sheet resistance cannot be obtained. The annealing temperature must be 400 ° C. or higher.

FIG. 2 shows the annealing temperature in the first RTA step (the annealing time was all 30 seconds; the second RTA step was 800
(30 ° C., 30 seconds) to change the junction leakage current characteristics (when a reverse bias of 5 V is applied) when a cobalt silicide film is formed on the source / drain diffusion layer (n ⁺ / p junction) of the n-channel MOSFET device. Is shown in FIG.

As can be seen from the figure, as the annealing temperature decreases,
The frequency at which a large junction leak current flows (the frequency of occurrence of defects) becomes smaller.
In the case of 0 ° C., it can be seen that the frequency of occurrence of bonding failure is significantly reduced. Therefore, it is desirable that the annealing temperature in the first RTA step be suppressed to 500 ° C. or less.

The profile of the diffusion layer of cobalt atoms spreading around the cobalt silicide film is mainly shown in FIG.
It is also known that the change is caused by the annealing (second RTA step) for changing the CoSi film to the CoSi ₂ film described in (f).

In the second RTA step, the CoSi film is
In order to completely convert to an OSi ₂ film, at least 6
A heating step (thermal budget) at 50 ° C. for 30 seconds or more is required.

However, when the annealing temperature in the second RTA step is low, particularly when the annealing temperature is 700 ° C. or less, it becomes possible for cobalt atoms to elute around the cobalt silicide (CoSi, CoSi 2) film. The diffusion layer of Kovardo atoms spreading around the film becomes deep, and there is a possibility that poor bonding may occur.

Therefore, when the annealing temperature in the second RTA step is high, cobalt silicide (CoSi, CoSi
Since the cobalt atoms that have melted around the Si ₂ ) film immediately react with silicon and change to CoSi ₂ , the diffusion layer of the cobalt atoms spreading around the cobalt silicide film becomes shallower.

FIG. 3 shows the annealing temperature in the second RTA step (the annealing time was all 30 seconds; the first RTA step was 500
(30 ° C., 30 seconds) to change the junction leakage current characteristic when a silicide film is formed on the source / drain diffusion layer (n ⁺ / p junction) of the n-channel MOSFET element (junction when applying a reverse bias of 5 V). (Probability frequency distribution of leak current). The p-channel MOSFET device was similarly examined. FIG. 4 shows the result.

From the figure, it can be seen that as the annealing temperature increases,
The frequency at which a large junction leak current flows (the frequency of occurrence of defects) becomes smaller.
In the case of 0 ° C., it can be seen that the frequency of occurrence of bonding failure is low. Therefore, the annealing temperature of the second RTA is 80
It is desirable to keep the temperature at 0 ° C. or higher.

However, if the annealing temperature is 950 ° C. or higher, agglomeration of the cobalt silicide (CoSi ₂ ) film occurs and the sheet resistance increases. Therefore, a temperature of 900 ° C. or lower is actually used. .

In the second RTA step, the rate of temperature increase until the annealing temperature is reached is also important. This is because, when the rate of temperature rise is small, when the temperature is 700 ° C. or less at which the cobalt atoms are easily melted into the silicon substrate during the temperature rise, the diffusion of the cobalt atoms proceeds.

FIG. 5 shows the temperature increase rate in the second RTA step,
FIG. 5 shows a measurement result obtained by examining a relationship with a diffusion depth of cobalt atoms (a depth from a cobalt silicide / silicon interface to a cobalt atom density of 1 × 10 ¹⁸ cm ⁻³ or less).
Here, the temperature and the time of the second RTA process are each 800.
° C for 30 seconds.

From the figure, it can be seen that the heating rate of the second RTA is about 30.
It can be seen that the diffusion of cobalt atoms into the silicon substrate can be suppressed by setting the temperature to at least ° C / sec.

Summarizing the above, in order to effectively suppress the occurrence of a junction failure such as an increase in junction leakage current even if the miniaturization is advanced, it is necessary to optimize the cobalt salicide process as follows. good.

(1) At the time of ion implantation (particularly arsenic ion implantation in nM0SPET) when forming the source / drain diffusion layers, the temperature of the silicon substrate is kept at -100 ° C. or lower.

(2) The annealing temperature in the first RTA step for changing the cobalt film to the CoSi film is 400 ° C. or more and 50 ° C.
Keep below 0 ° C.

(3) The annealing temperature in the second RTA step for changing the CoSi film to the CoSi ₂ film is 800 ° C. or more.
Keep below 00 ° C.

(4) The rate of temperature increase in the second RTA step is 3
0 ° C / sec or more.

(Second Embodiment) As described in the section of the prior art, in the cobalt salicide step, if the substrate temperature (film formation temperature) when forming a cobalt film by sputtering is too high, the device Coagulation of the cobalt film occurs on the silicon oxide film, which is the isolation insulating film, and as a result, the thickness of the cobalt silicide film locally increases at the peripheral portion of the source / drain diffusion layer, and a bonding failure is likely to occur. On the other hand, if the gate length is too low, there is a problem that the sheet resistance of the gate electrode increases when the gate length becomes short.

FIG. 6 shows the result of examining the effective range of the substrate temperature during the sputtering of the cobalt film. From the figure, it can be seen that when the thickness of the cobalt film is as thick as 18 nm, the film does not agglomerate even at a substrate temperature of 300 ° C., but as the film thickness decreases, the agglomeration occurs at a lower substrate temperature. ,
It can be seen that aggregation occurs at about 250 ° C. for 10 nm and about 200 ° C. for 8 nn.

In a fine element having a gate length of 0.15 μm or later, the source / drain diffusion layer becomes very shallow to suppress the short channel effect of the transistor. Since the defect is likely to occur, the thickness of the cobalt film is considered to be about 12 nm or less.

When the thickness of the cobalt film is reduced to 6 nm, the sheet resistance of the cobalt silicide film becomes 12 to 1
Since it rises to about 3Ω, it is difficult to further reduce the thickness from the viewpoint of reducing the parasitic resistance.

Therefore, the substrate temperature during the sputter deposition of the cobalt film is set to 100 ° C. to 250 ° C., which does not cause an increase in the sheet resistance in the fine line gate pattern due to the presence of the natural oxide film.
Using a temperature in the range of ° C. will give the best properties.

(Third Embodiment) As described in the section of the prior art, in the process of forming a cobalt salicide film, the cap film used so far has advantages and disadvantages, and although it is an optimum cap film. Absent.

However, according to the study of the present inventors, it has been found that when a laminated film of a titanium film and a titanium nitride film is used as the cap film, the problem of the conventional cap film can be solved.

That is, the problem of non-uniform growth of the cobalt silicide film due to the film stress of the titanium nitride film directly applied to the cobalt film when the titanium nitride film is used as the cap film, and the problem of the titanium film when the titanium film is used as the cap film. Problems such as increased film stress due to the progress of nitridation from the surface and variations in the finished cobalt silicide film thickness, titanium oxide is easily formed by oxidation of the titanium film, and etching residue is likely to occur in selective etching, resulting in short circuit failure. It is possible to solve all the problems that are more likely to occur. Of course, the problem of an increase in the thickness of the oxide film at the interface between the cobalt film and the silicon substrate due to the atmosphere after the deposition of the cobalt film when the cap film is not used can also be solved.

The reason for obtaining such an effect is that the titanium nitride film prevents oxidation and nitridation from the surface of the titanium film, the titanium film relieves the film stress of the titanium nitride film, and the titanium atoms in the titanium film are reduced. This is considered to be due to diffusion to the interface between the cobalt film and the silicon substrate and the like, reducing the natural oxide film and the like existing at the interface and the like.

FIG. 7 is a process sectional view showing a method of forming a cobalt silicide film using a cap film according to the present invention. In this forming method, first, a cobalt film 2 is formed on a silicon substrate 1.
Then, a titanium film 3 as a cap film and a titanium nitride film 4 are sequentially formed on the cobalt film 2 by sputtering.

Next, the silicon substrate 1 and the cobalt film 2 are reacted with each other by heat treatment to form a cobalt silicide film 5. At this time, since the cobalt film 2 reacts with the titanium film 3, an alloy layer 6 of cobalt and titanium is formed between the titanium film 3 and the cobalt silicide film 5. A MOS-type FET device was formed by using a cobalt salicide process in which a laminated structure of 3 / titanium nitride film 4 was introduced, and the sheet resistance of the polysilicon gate electrode was measured. As shown in FIG.
It can be formed without variation even with a gate length of 12 microns,
In addition, as shown in FIG. 9, the occurrence of defective junction can be easily suppressed as shown in FIG. 9, and the stability of the salicide process is also improved.

(Fourth Embodiment) As described above, the cobalt salicide process for self-aligning a cobalt silicide film on the surface of the source / drain diffusion layers and the polysilicon gate electrode of a MOS FET device includes: There were a number of optimization points. An example of the manufacturing process of the MOS FET device when these points are optimized will be described with reference to the process cross-sectional view of FIG.

First, as shown in FIG.
0) An element isolation insulating film (silicon oxide film) 12 and a p-type well diffusion layer 13 are formed on an n-type silicon substrate 11 having a plane orientation.

Next, as shown in FIG. 10B, after a gate oxide film 14 is formed, a polysilicon film for a gate electrode is deposited and patterned to form a polysilicon gate electrode (hereinafter simply referred to as a gate electrode). After the formation of 15), n is implanted by arsenic ion implantation and heat treatment such as PTA.
Shallow source / drain diffusion layer (extension)
16 are formed.

Next, as shown in FIG. 10C, a silicon nitride film is deposited on the entire surface, and anisotropic etching such as RIE is performed on the silicon nitride film to form a silicon nitride film as a gate sidewall insulating film (spacer). 17 is formed.

Next, as shown in FIG. 13C, while the silicon substrate 11 is kept at −150 ° C. or lower, the source / drain with few crystal defects due to ion implantation is subjected to arsenic ion implantation and heat treatment such as RTA. The diffusion layer 18 is formed.

Next, as shown in FIG. 10D, a silicon oxide film such as a natural oxide film remaining on the surface of the source / drain diffusion layer 18 and the surface of the gate electrode 15 using dilute hydrofluoric acid or the like. Is removed, the temperature of the silicon substrate is raised to 150
A cobalt film 1 having a thickness of 12 nm
9, a titanium film 20, and a titanium nitride film 21 are sequentially formed by sputtering.

By forming the cobalt film 19 by sputtering at such a substrate temperature, the aggregation of the cobalt film 19 on the element isolation insulating film 12 can be prevented. Further, a silicon oxide film such as a natural oxide film re-formed on a silicon region (a surface portion of the source / drain diffusion layer 18 and the gate electrode 5) on which the cobalt film 19 is deposited is mixed by (thermal) energy during sputtering. Therefore, the non-uniform reaction between cobalt and silicon is effectively suppressed.

Next, as shown in FIG.
The source / drain diffusion layer 18 and the gate electrode 15 are formed by lamp annealing (first RTA step) at 30 ° C. for 30 seconds.
Are reacted with the cobalt film 19, respectively.
An i film 22 is formed.

At this time, the titanium nitride film 21 serving as the cap film prevents oxidation and nitridation from the surface of the titanium film 20,
The titanium film 20 relieves the film stress of the titanium oxide film 21 and diffuses in the cobalt film 19 to form the cobalt film 1.
It functions to reduce a natural oxide film existing between the surface 9 and the surface of the silicon region (source / drain diffusion layer 18, gate electrode 15).

The upper third of the cobalt film 19 reacts with a part of the titanium film 20 to become an alloy layer (not shown) of cobalt and titanium, and becomes an element isolation insulating film (silicon oxide film).
The cobalt film 19 deposited on the silicon nitride film 17 and the silicon nitride film 17 does not react and remains in a cobalt film state.

Next, as shown in FIG. 10F, the unreacted cobalt film 19, the alloy layer (not shown), and the titanium film 1 are etched using an etching solution such as a mixture of sulfuric acid and hydrogen peroxide.
2 and an unnecessary film such as the titanium nitride film 13 are removed by etching, and then lamp annealing (800R, 30 seconds) is performed.
TA process), the CoSi film 22 is changed to a low-resistance CoSi film.
_It is changed to _two films 23.

The temperature rise during this lamp annealing is 30 ° C. /
The heating is performed at a heating rate of not less than seconds, more preferably at a heating rate of not less than 50 ° C./sec.

Through the steps described above, a cobalt salicide film having a low resistance and a small junction leakage defect can be stably formed even if the element is miniaturized.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of a cobalt silicide film using a cobalt film was described, but the present invention relates to a nickel silicide film using a nickel film, another high melting point metal film such as a palladium silicide film using a palladium film. It can be applied to the used metal silicide film. In addition, various modifications can be made without departing from the scope of the present invention.

[0125]

As described above in detail, according to the present invention, miniaturization of an element can be promoted by optimizing conditions for forming an impurity diffusion region or ion implantation conditions or by using a predetermined cap film. In addition, the silicide film can be formed on the impurity diffusion region without deteriorating the electrical characteristics.

[Brief description of the drawings]

FIG. 1 is a view for explaining a method for forming an impurity diffusion layer (underlying silicide film) according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a result of examining an effect (junction leak current) due to a difference in annealing temperature in a first RTA step in a method for forming a cobalt silicide film according to a first embodiment of the present invention;

FIG. 3 is a diagram showing a result of examining an effect (junction leakage current at an n ⁺ / p junction) due to a difference in annealing temperature in a second RTA step in a method of forming a cobalt silicide film according to the first embodiment of the present invention;

FIG. 4 is a view showing a result of examining an effect (junction leakage current at ap ⁺ / n junction) due to a difference in annealing temperature in a second RTA step in the method of forming a cobalt silicide film according to the first embodiment of the present invention;

FIG. 5 is a view showing a result of examining an effect (depth of a Co atom diffusion layer) due to a difference in a heating rate in a second RTA step in the method for forming a cobalt silicide film according to the first embodiment of the present invention;

FIG. 6 is a diagram showing a result of examining an effective range of a substrate temperature during Co sputtering in a method of forming a cobalt silicide film according to a second embodiment of the present invention;

FIG. 7 is a process sectional view showing a method for forming a cobalt silicide film according to a third embodiment of the present invention.

FIG. 8 is a diagram for explaining the effect (sheet resistance) of the method for forming a cobalt silicide film according to the third embodiment of the present invention.

FIG. 9 is a diagram for explaining the effect (junction leakage current) of the method for forming a cobalt silicide film according to the third embodiment of the present invention.

FIG. 10 is a process sectional view showing a method for manufacturing a MOS-type FET device using a cobalt salicide process according to a fourth embodiment of the present invention;

FIG. 11 is a process sectional view showing a method for manufacturing a MOS-type FET device using a conventional cobalt salicide process.

FIG. 12 is a diagram showing an arsenic concentration distribution (impurity profile) in a depth direction of a diffusion layer formed by conventional arsenic ion implantation.

FIG. 13 is a view for explaining a problem of a conventional method of forming a diffusion layer using an ion implantation method.

FIG. 14 is a micrograph (cross-sectional TEM photograph) of a diffusion layer formed by using a conventional ion implantation method.

FIG. 15 shows a non-salicide type MOS FET in which source / drain diffusion layers are formed by using a conventional ion implantation method.
Sectional view of element

FIG. 16 shows a MOS FET having a salicide structure in which source / drain diffusion layers are formed by using conventional arsenic ion implantation.
Sectional view of element

FIG. 17 is a diagram for explaining a problem of a conventional method of manufacturing a MOS FET device using a low-temperature cobalt salicide process.

FIG. 18 is a micrograph (SEM) of a cobalt film formed by increasing the substrate temperature during sputtering.

FIG. 19 is a diagram for explaining a problem of a conventional method for manufacturing a MOS FET device using a high-temperature cobalt salicide process.

FIG. 20 is a process sectional view showing a conventional method of forming a cobalt silicide film using a titanium nitride film as a cap film.

FIG. 21 is a process sectional view showing a conventional method for forming a cobalt silicide film using a titanium film as a cap film.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 cobalt film 3 titanium film 4 titanium nitride film 5 cobalt silicide film 6 alloy layer 11 silicon substrate 12 element isolation insulating film (silicon oxide film) 13 well diffusion layer 14 gate oxide Film 15 Gate electrode 16 Extension 17 Gate sidewall insulating film (silicon nitride film) 18 Source / drain diffusion layer 19 Cobalt film 20 Titanium film 21 Titanium nitride film 22 Cobalt monosilicide (CoSi) film 23 Cobalt disilicide (CoSi ₂ ) film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB20 BB21 BB23 DD26 DD37 DD79 DD80 DD84 GG09 GG10 GG14 HH04 5F040 DA20 EC01 EC07 EC13 EF02 EF09 FA07 FB02 FB04 FC19

Claims (13)

[Claims] An impurity is implanted into the silicon region while maintaining the temperature of the silicon region at -100 ° C. or lower, and then a heat treatment is performed on the silicon region.
A method for manufacturing a semiconductor device, comprising: forming an impurity diffusion region; and forming a silicide film on a surface of the impurity diffusion region. 2. The method according to claim 1, wherein said impurity ions are arsenic ions. 3. The method according to claim 1, wherein the silicide film is a CoSi ₂ film. 4. The step of forming the CoSi ₂ film includes a step of forming a cobalt film on a surface of the impurity diffusion layer and a step of reacting the cobalt film and the impurity diffusion layer by a first heat treatment to form a CoSi film. 4. The semiconductor device according to claim 3, further comprising: forming a CoSi film into a CoSi ₂ film by reacting the CoSi film and the impurity diffusion layer by a second heat treatment. 5. Manufacturing method. 5. The method according to claim 4, wherein the temperature of the first heat treatment is 400 ° C. or more and 500 ° C. or less. 6. The method according to claim 4, wherein the temperature of the second heat treatment is not lower than 800 ° C. and not higher than 900 ° C. 7. The heating rate of the second heat treatment is 30 ° C.
5. The method according to claim 4, wherein the rate is not less than / sec. 8. The semiconductor device according to claim 1, wherein said silicon region is a silicon substrate, and said impurity diffusion region is at least one of a source diffusion layer and a drain diffusion layer. Production method. 9. The method according to claim 1, further comprising: forming a metal film in contact with a predetermined region of the silicon region; and reacting the predetermined region of the silicon region with the metal film by heat treatment to form a silicide film. A method for manufacturing a semiconductor device, comprising: setting a temperature of a region to 100 ° C. or higher and lower than a temperature at which the metal film starts to aggregate, and forming the metal film by a sputtering method. 10. The method according to claim 9, wherein the metal film is a cobalt film, a nickel film or a palladium film, and the silicide film is a cobalt silicide film, a nickel silicide film or a palladium silicide film. Method. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the temperature of said silicon region is set to 100 ° C. or more and 250 ° C. or less, and said metal film is formed by a sputtering method. 12. A step of forming a cobalt film in contact with a predetermined region of the silicon region, a step of sequentially forming a titanium film and a titanium nitride film on the cobalt film, and a heat treatment to heat the predetermined region of the silicon region and the cobalt film. And forming a cobalt silicide film. 13. The semiconductor device according to claim 9, wherein said silicon region is a silicon substrate, and said predetermined region is at least one of a source diffusion layer and a drain layer.
The method for manufacturing a semiconductor device according to any one of the above.