JP2009182071A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, capable of balancing prevention of generation of a leak current, with a reduction in the resistance in a diffusion region, in manufacturing a semiconductor device that include the diffusion region having a step. <P>SOLUTION: Active regions 2 extending in X-direction, control gate electrodes 7 extending in Y-direction and floating gate electrodes 5 located at intersection parts between both of these are respectively formed on a semiconductor substrate 1; embedded insulating films 3, in trenches related to the inside of a source formation planned region crossing the plurality of active regions 2, are removed; and source regions 9b, having steps and flat drain regions 9a, are formed by carrying out impurity ion implantation by using the control gate electrodes 7 as a mask. Thereafter, a Co film 10, a Ti film 11 and a TiN film 12 are formed, in this order, on the entire surface of the semiconductor substrate 1 so that the ratio of the film thickness of the Ti film 11 to that of the Co film 10 is set to 1.0-1.4, and thereafter, contact regions among the control gate electrodes 7 and the source/drain diffusion regions 9, and the Co films 10 are silicided by carrying out an annealing process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a transition metal silicide film in a self-aligned manner on a source / drain diffusion region and a gate electrode of a transistor.

In recent miniaturized semiconductor devices, especially NOR flash memories for high-speed random access, in order to reduce the parasitic resistance of the element, the surface of the source / drain diffusion region and the gate electrode is self-aligned. A method of forming a refractory metal such as cobalt (silicidation) is generally used. As the refractory metal silicide film, cobalt silicide (CoSi ₂ ) is mainly used.

  Hereinafter, a method of manufacturing a flash memory using a conventional silicide technique will be described with reference to the drawings. FIG. 7 is a schematic process cross-sectional view showing a manufacturing process when a flash memory is manufactured using a conventional method, and is divided into FIGS. 7A to 7G for each process.

  First, as shown in FIG. 7A, an active region 2 and an element isolation region 3 are divided on a semiconductor substrate 1 using an STI (Shallow Trench Isolation) method, and a gate oxide film 4 and a floating region are formed on the active region 2. A gate electrode 5, a three-layer film (ONO film) 6 made of an oxide film, a nitride film, and an oxide film, and a control gate electrode 7 are sequentially formed. Then, a sidewall insulating film 8 is formed on the outer wall of the laminated structure including the floating gate electrode 5 and the control gate electrode 7.

Next, as shown in FIG. 7B, impurity ions are implanted into the active region 2 and then thermal diffusion is performed to form source / drain diffusion regions 9. At this time, N-type ions (for example, As ⁺ ) are implanted into the region for forming the N-channel transistor, and P-type ions (for example, BF ²⁺ ) are implanted into the region for forming the P-channel transistor.

Next, as shown in FIG. 7C, ion implantation (for example, Ar ⁺ ) is performed on the entire surface of the semiconductor substrate 1 to form an amorphous layer 16.

  Next, as shown in FIG. 7D, a cobalt (Co) film 10 and a titanium nitride (TiN) film 12 are sequentially deposited on the entire surface of the semiconductor substrate 1 by sputtering. The TiN film 12 plays a role of preventing the Co film 10 from being oxidized in a heat treatment performed later.

  Next, as shown in FIG. 7E, a first heat treatment is performed at 475 to 550 ° C. for 60 seconds by a lamp annealing method. By this step, on the control gate electrode 7 and the source / drain diffusion region 9, Si constituting the semiconductor substrate 1 reacts with the Co film 10 to form a CoSi film 14.

  Next, as shown in FIG. 7F, the TiN film 12 and the unreacted Co film 10 are removed using an aqueous sulfuric acid solution.

Next, as shown in FIG. 7G, a second heat treatment is performed at 750 to 850 ° C. for 30 seconds by a lamp annealing method. Through this step, the CoSi film 14 is phase-shifted to the low-resistance CoSi ₂ film 15. From the above steps, the resistance of the control gate electrode 7 and the source / drain diffusion region 9 can be lowered to a sheet resistance of 10 [Ω / □] or less necessary for speeding up the MOS type semiconductor device.

  However, when the above process is applied to the manufacture of a nonvolatile semiconductor memory device in which memory cells are arranged in a matrix, the following problems occur.

  FIG. 8 is a plan view showing the structure of a typical NOR flash memory (see Patent Document 1 below). In the memory cell array of the flash memory 30, a plurality of active regions 2 and element isolation regions 3 extending in the X direction in the drawing are alternately formed in parallel in the Y direction. Further, a part of the active region 2 is formed by extending in the Y direction so as to cross the plurality of element isolation regions 3.

  A word line 7 functioning as a control gate is formed extending in the Y direction so as to cross the plurality of active regions 2 and element isolation regions 3.

  In a region where the word line 7 and the active region 2 intersect, an ONO film 6, a floating gate electrode 5, and a gate oxide film 4 are sequentially stacked from the top under the word line (control gate electrode) 7 ( This constitutes the memory cell 31 (not shown in FIG. 8).

  A drain contact 21 for electrical connection is formed in a portion of the active region 2 that is used as the drain diffusion region 9a of the memory cell 31. A source diffusion region 9b extending in the Y direction so as to cross the plurality of element isolation regions 3 is formed on the opposite side of the drain diffusion region 9a via the word line 7. A source contact 22 for electrical connection is formed in the source diffusion region 9b.

  As shown in FIG. 8, when forming the source diffusion region 9b formed so as to cross the plurality of element isolation regions 3, the active regions 2 and the element isolation regions 3 extending in the X direction in advance are alternately arranged in the Y direction. After forming in parallel, the element isolation region (element isolation insulating film) 3 in a predetermined source formation planned region is removed, thereby forming an active region continuous in the Y direction in the source formation planned region. Thereafter, impurity ion implantation is performed to form the source diffusion region 9b.

  That is, by removing the insulating film embedded in the trench in order to form the element isolation region 3, an active region having a high height outside the trench and an active region having a low height in the trench are formed. The source diffusion region 9b is formed by being in contact and implanting impurity ions under such a state. That is, the source diffusion region 9b has a configuration in which stepped shapes having different height positions are continuously provided in the Y direction.

  When the flash memory 30 shown in FIG. 8 is manufactured based on the method referred to in FIG. 7, silicidation is performed on the surfaces of the drain diffusion region 9 a, the source diffusion region 9 b, and the word line 7. At this time, since the source diffusion region 9b has a stepped shape as described above, there is a problem that resistance is easily increased as compared with the flat drain diffusion region 9a.

For example, in order to reduce the resistance (10Ω / □) of the flat drain diffusion region 9a so as to increase the speed of the semiconductor device, it can be realized by forming 400 CoSi ₂ films 15 in the same region. However, since the source diffusion region 9b having a step shape has a coverage of about 10% as compared with the drain diffusion region 9a having a flat shape, the source diffusion region 9b having a step shape is formed under the above film thickness conditions. Only about 40 mm of CoSi ₂ film 15 is formed inside. For this reason, the resistance in the source diffusion region 9b cannot be sufficiently reduced (about 6000Ω / □). It has been found that when the source resistance exceeds 4000 Ω / □, a delay problem occurs in the access time of the semiconductor device, and it is necessary to set the resistance further lower than that in consideration of the variation in mass production. That is, the conventional method has a problem in the delay time during access.

Therefore, in order to sufficiently reduce the resistance of the source diffusion region 9b, it is necessary to form the CoSi ₂ film 15 having a sufficient thickness in the step portion where the region is formed. However, as described above, the source diffusion region 9b having a stepped shape has a coverage of about 10% as compared with the drain diffusion region 9a, and therefore the film thickness required for realizing a low resistance (10Ω / □). In order to form the CoSi ₂ film 15 (for example, 100Å), it is necessary to form a silicide film of 1000Å or more in the flat drain diffusion region 9a. That is, the Co film 10 necessary for forming the silicide film needs to be formed sufficiently thick, and the Co film 10 and Si (semiconductor substrate) 1 must be reacted to form the thick CoSi film 14. is there.

  However, if the amount of Si consumed increases with the formation of the thick CoSi film 14, the pn junction on the substrate may be destroyed and a leakage current may be generated. For this reason, there is an upper limit to the thickness value of the silicide film that can be formed.

  That is, in the case of a structure having an active region having a step shape as shown in FIG. 8, the silicide film is formed under a film thickness condition that can achieve both a reduction in resistance of the step portion and avoidance of leakage current. Has a problem that it is difficult to form.

  Conventionally, as a method of suppressing the growth of a silicide film and avoiding the occurrence of a leak current, a method of performing silicidation after sequentially forming a Co film and a Ti film has been disclosed (see Patent Documents 2 and 3 below). .

JP 2006-54283 A JP-A-8-288241 JP 2001-15453 A

  Patent Document 1 discloses an example in which silicidation is performed after forming a Co film with a thickness of 10 to 30 nm and a Ti film with a thickness of 10 nm. Patent Document 2 shows an example in which silicidation is performed after forming a Co film with a thickness of 10 nm and a Ti film with a thickness of 20 nm. However, even when the flash memory 30 having the structure shown in FIG. 8 is manufactured under the film thickness conditions disclosed in both documents, the above-described problems cannot be solved.

  In view of the above problems, the present invention provides a semiconductor device capable of avoiding the occurrence of leakage current and reducing resistance in the diffusion region when manufacturing a semiconductor device including a diffusion region having a step shape. It aims to provide a method.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: a trench for element isolation extending on a semiconductor substrate extending in a first direction parallel to the substrate surface; and perpendicular to the first direction. Forming a plurality of rows in parallel in two directions; and forming a buried insulating film in the trench, thereby forming a plurality of rows of active regions extending in the first direction outside the trench in parallel in the second direction. Forming a first electrode film extending in the first direction on the active region in parallel with the second direction through a gate oxide film; and forming the first electrode film on the active region; After forming the second electrode film on the upper layer via the inter-gate insulating film, a stacked structure including the second electrode film, the inter-gate insulating film, the first electrode film, and the gate oxide film is formed in the second direction. Stretching in the second direction by patterning Forming a control gate electrode and a matrix-like floating gate electrode vertically via the inter-gate insulating film, forming a sidewall insulating film on an outer wall of the control gate electrode and the floating gate electrode, Removing the buried insulating film formed in the trench in the source formation planned region crossing the plurality of active regions arranged in parallel in the second direction, and performing impurity ion implantation using the control gate electrode as a mask Forming a source diffusion region in the source formation planned region and a drain diffusion region in the active region outside the source diffusion region, and a cobalt film, a titanium film, and a titanium nitride film on the entire surface of the semiconductor substrate. Are deposited in this order, and then annealed to control the control gate electrode. Siliciding the source diffusion region and the contact region between the drain diffusion region and the cobalt film, and the film thickness ratio of the titanium film to the cobalt film during film formation is 1.0. The above is 1.4 or less.

  According to the configuration of the present invention, it is possible to suppress the occurrence of leakage current while simultaneously reducing the resistance in the flat drain diffusion region and the source diffusion region having a step shape.

  In the following, embodiments of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “method of the present invention” as appropriate) will be described with reference to the drawings.

  The method of the present invention assumes a method of manufacturing a semiconductor device having a planar shape schematically shown in FIG. Below, it demonstrates with reference to the schematic plan view and schematic sectional drawing for every process.

  In addition, each schematic plan view and schematic sectional view shown below are schematically illustrated, and the dimensional ratio on the drawing does not necessarily match the actual dimensional ratio. In the following drawings, the same components as those in FIGS. 7 and 8 are denoted by the same reference numerals.

  FIG. 1 is a schematic plan view showing a manufacturing process when a semiconductor device is manufactured by the method of the present invention, and the process is divided into FIGS. 1A to 1E. 2 and 3 are schematic cross-sectional views showing a manufacturing process when a semiconductor device is manufactured by the method of the present invention. FIG. 2 (a) to FIG. 3 (d) and FIG. 3 (a) to FIG. (It is divided into two drawings for the sake of space). FIG. 4 is a flowchart showing the manufacturing process of the method of the present invention, and each step # 1 to # 17 in the following sentence represents each step of the flowchart shown in FIG.

  First, a plurality of trenches extending in a predetermined first direction (X direction in the drawing) parallel to the substrate surface on the semiconductor substrate 1 are arranged in parallel in a second direction (Y direction in the drawing) orthogonal to the first direction. A row is formed (step # 1). Next, by forming a buried insulating film in the trench, an element isolation region 3 extending in the X direction is formed, thereby forming an active region 2 extending in the X direction outside the trench (step #). 2). Thereby, as shown in FIG. 1A, the active regions 2 and the element isolation regions 3 extending in the X direction are alternately arranged in a stripe shape in the Y direction. In the drawing, in order to form a source contact in a later step, the formation width of a part of the active region 2 is expanded in order to secure the contact region. However, each active region 2 is formed with the same width. You may do it.

  Next, after the surface of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 4 (step # 3, not shown in FIG. 1), a first electrode film (polysilicon film) that becomes a floating gate electrode is formed on the entire surface. ) 5 is deposited (step # 4). Thereafter, as shown in FIG. 1B, the first electrode film 5 and the gate oxide film 4 are patterned so as to extend in the X direction on the active region 2 (step # 5). As a result, the first electrode films 5 and the element isolation regions 3 extending in the X direction are alternately arranged in stripes in the Y direction.

  Next, after an inter-gate insulating film (ONO film) 6 is formed on the entire surface (step # 6, not shown in FIG. 1), a second electrode film (polysilicon) that becomes a control gate electrode (word line) is formed on the entire surface. Film) 7 is formed (step # 7). Thereafter, as shown in FIG. 1C, the laminated structure including the second electrode film 7, the intergate insulating film 6, the first electrode film 5, and the gate oxide film 4 is patterned in the Y direction (step # 8). Thereby, a second electrode film (control gate electrode) 7 extending in the Y direction is formed so as to cross the plurality of active regions 2 and element isolation regions 3. In addition to the region where the drain contact is to be formed, the first electrode film (floating gate electrode) is formed in a matrix form below the control gate electrode 7 via the intergate insulating film 6 at the intersection of the control gate electrode 7 and the active region 2. ) 5 is formed.

  Next, a sidewall insulating film 8 is formed on the outer walls of the floating gate electrode 5 and the control gate electrode 7 through a silicon oxide film forming process and an etch back process (step # 9, not shown in FIG. 1). .

  Next, the element isolation region (buried insulating film) 3 in the trench in the predetermined source formation scheduled region 9bf formed in the Y direction is removed (step # 10). Thereby, in the source formation scheduled region 9bf, the active region having a high height outside the trench is connected to the active region having a low height in the trench, and the active region 2 showing a step shape continuous in the Y direction. Is formed (FIG. 1D, FIG. 2A). 2 and 3 are divided into X1-X2 sectional view, Ys1-Ys2 sectional view, and Yd1-Yd2 sectional view in FIG.

Next, impurity ion implantation is performed using the control gate electrode 7 as a mask (step # 11). At this time, N-type ions (for example, As ⁺ ) are implanted into the region for forming the N-channel transistor, and P-type ions (for example, BF ²⁺ ) are implanted into the region for forming the P-channel transistor.

  As shown in FIGS. 1E and 2B, in step # 11, a source diffusion region 9b having a step difference continuous in the Y direction is formed in the source formation scheduled region 9bf. A drain diffusion region 9a is formed in the active region 2 opposite to the source diffusion region 9b with the control gate electrode 7 interposed therebetween.

Next, as shown in FIG. 2C, ion implantation (for example, Ar ⁺ ) is performed to form an amorphous layer 16 over the entire surface of the semiconductor substrate 1 to form an amorphous layer 16 (step # 12). . Even after step # 12, the source diffusion region 9b is naturally formed in the Ys1-Ys2 cross section, and the drain diffusion region 9b is formed in the Yd1-Yd2 cross section. However, in FIG. In order to avoid complication, the diffusion region is not shown in both cross-sectional views. Also in the subsequent process cross-sectional views, illustration of the source diffusion region 9b in the Ys1-Ys2 cross section and the drain diffusion region 9a in the Yd1-Yd2 cross section is omitted for the same reason.

  Next, as shown in FIG. 2D, a Co film 10 is formed on the entire surface of the semiconductor substrate 1 with a thickness of 10 to 30 nm, a Ti film 11 with a thickness of 10 to 40 nm, a TiN film 12 with a thickness of 35 to 45 nm, and a sputtering method. Films are sequentially formed (step # 13). In step # 13, the film thickness ratio of the Ti film 11 to the Co film 10 is set to be within a predetermined range. This film thickness ratio will be described later.

  Next, as shown in FIG. 3A, a first heat treatment is performed by lamp annealing at about 475 to 550 ° C. for about 60 seconds (step # 14). By this step # 14, on the control gate electrode 7 and the source / drain diffusion region 9, the semiconductor substrate 1 (Si) and the Co film 10 react to form the CoSi film 14.

  Next, as shown in FIG. 3B, the TiN film 12 and the Ti film 11 are removed using an aqueous sulfuric acid solution (step # 15), and further generated using an aqueous ammonia aqueous solution in the process of step # 14. The Ti—Co alloy and the unreacted Co film 10 are removed (step # 16).

Next, as shown in FIG. 3C, a second heat treatment is performed at about 800 ° C. for about 30 seconds by a lamp annealing method (step # 17). By this step # 16, the CoSi film 14 undergoes phase transition to the lower resistance CoSi ₂ film 15, and the film is formed with a film thickness of about 40 to 60 nm.

  Thereafter, after forming an interlayer insulating film on the entire surface, a drain contact 21 for forming electrical connection with the drain diffusion region 9a and a source contact 22 for forming electrical connection with the source diffusion region 9b are formed. Thereafter, a wiring layer is formed on the interlayer insulating film. Thus, a nonvolatile semiconductor memory device having a plurality of memory cells in a matrix is manufactured.

  FIG. 5 shows the characteristics of the semiconductor device manufactured through steps # 1 to # 16 under the same conditions other than the film thickness ratio of the Co film 10 and the Ti film 11 formed in step # 13, and the film thickness described above. It is a graph which shows the relationship of a ratio. FIG. 5A shows the relationship between the film thickness ratio and the resistance in the source diffusion region 9b. FIG. 5B shows the relationship between the film thickness ratio and the breakdown voltage in the drain diffusion region 9a (the breakdown voltage when a constant current is passed through the drain diffusion region 9b). FIG. 5C shows the relationship between the film thickness ratio and the charge loss occurrence probability (the charge loss occurrence probability from the floating gate electrode 5 when a constant voltage is applied in the drain diffusion region 9a). FIG. 6 shows the graph shown in FIG. 5 in a table format.

  According to FIG. 5A, when the film thickness ratio of the Ti film 11 to the Co film 10 (hereinafter simply referred to as “Ti / Co film thickness ratio”) is increased, the Ti / Co film thickness ratio becomes 1. .4 or more, the upper limit value of resistance in the source diffusion region 9b is 2500Ω / □, and when the film thickness ratio is 1.5 or more, the resistance value in the source 9b increases rapidly. I understand. It has been found that if the source resistance exceeds 4000Ω / □, a delay problem occurs in the access time of the semiconductor device. In consideration of variations in mass production, the sheet resistance is set to 2500Ω / □ in order to prevent the delay time from occurring. The following is desirable.

  As can be seen from FIG. 5B, when the Ti / Co film thickness ratio is decreased, the breakdown voltage in the drain diffusion region 9a rapidly decreases at 1.0 or less. Thereby, the tendency for leak current to occur is seen. This can also be seen from the fact that in FIG. 5C, as the Ti / Co film thickness ratio is decreased, the charge loss occurrence probability increases rapidly at 1.0 or less. When the Ti / Co film thickness ratio is 1.0 or less, the value exceeds 15.0%, which is the upper limit value of the charge loss occurrence probability. A semiconductor device having a charge loss occurrence probability exceeding 15.0% has been empirically known to cause a market failure, and in order not to cause a market failure, the charge loss occurrence probability is 15.0%. It is desirable to suppress to the following.

  That is, it can be seen that the Ti / Co film thickness ratio needs to be 1.4 or less in order to suppress the resistance value in the source diffusion region 9b to 2500Ω / □ or less which is the upper limit value. Further, it is understood that the Ti / Co film thickness ratio needs to be 1.0 or more in order to suppress the leakage current and suppress the charge loss occurrence probability to the upper limit of 15.0% or less. As described above, in step # 13, the Co film 10 and the Ti film 11 are formed by controlling the thickness ratio of the Ti film 11 to the Co film 10 to be 1.0 or more and 1.4 or less. It is possible to realize a semiconductor device that suppresses the occurrence of leakage current while maintaining the inside of the drain diffusion region 9a and the source diffusion region 9b having a step shape in a low resistance state.

The schematic plan view which shows the manufacturing process at the time of manufacturing a semiconductor device by the method of this invention Schematic sectional view showing a part of the manufacturing process when manufacturing a semiconductor device by the method of the present invention Schematic sectional view showing another part of the manufacturing process when manufacturing a semiconductor device by the method of the present invention The flowchart which shows the manufacturing process at the time of manufacturing a semiconductor device using the method of this invention in process order The graph which shows the relationship between the film thickness ratio of Co film | membrane and Ti film | membrane, and each characteristic of the manufactured semiconductor device Table showing the relationship between the film thickness ratio of the Co film and the Ti film and the characteristics of the manufactured semiconductor device Schematic process cross-sectional view showing a manufacturing process when manufacturing a flash memory using a conventional method A plan view showing the structure of a typical NOR flash memory

Explanation of symbols

1: Semiconductor substrate 2: Active region 3: Element isolation region 4: Gate oxide film 5: Floating gate electrode 6: ONO film (inter-gate insulating film)
7: Control gate electrode, word line 8: Side wall insulating film 9: Source / drain diffusion region 9a: Drain diffusion region 9b: Source diffusion region 9bf: Source formation planned region 10: Co film 11: Ti film 12: TiN film 14 : CoSi film 15: CoSi ₂ film 16: Amorphous layer 21: Drain contact 22: Source contact 30: Flash memory cell array 31: Memory cell

Claims (1)

Forming a plurality of rows of trenches for element isolation extending in a first direction parallel to the substrate surface on a semiconductor substrate in parallel in a second direction orthogonal to the first direction;
Forming a plurality of rows of active regions extending in the first direction outside the trench in parallel with the second direction by forming a buried insulating film in the trench;
Forming a plurality of rows of first electrode films extending in the first direction on the active region in parallel with the second direction through a gate oxide film;
A stacked structure comprising the second electrode film, the inter-gate insulating film, the first electrode film, and the gate oxide film after forming a second electrode film over the first electrode film via an inter-gate insulating film Forming a control gate electrode extending in the second direction and a matrix-like floating gate electrode vertically through the inter-gate insulating film by patterning in the second direction;
Forming a sidewall insulating film on an outer wall of the control gate electrode and the floating gate electrode;
Removing the buried insulating film formed in the trench in the source formation planned region that crosses the plurality of active regions arranged in parallel in the second direction;
Performing impurity ion implantation using the control gate electrode as a mask to form a source diffusion region in the source formation planned region and a drain diffusion region in the active region outside the source diffusion region;
A cobalt film, a titanium film, and a titanium nitride film are formed in this order on the entire surface of the semiconductor substrate, and then annealed to form the control gate electrode, the source diffusion region, the drain diffusion region, and the cobalt film. Siliciding the contact region, and
A method of manufacturing a semiconductor device, wherein a film thickness ratio of the titanium film to the cobalt film during film formation is 1.0 or more and 1.4 or less.

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