JP2007294641A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce parasitic resistance by forming a silicide layer without such disadvantages as crystal defect, device characteristic deterioration, and leak current increase. <P>SOLUTION: In an Ar ion implantation step, ion implantation conditions (1.0×10<SP>14</SP>ions/cm<SP>2</SP>or less, at 10 keV) are provided not for making noncrystalline but for reforming near the surface of a source/drain region 9 and the surface of a polycrystalline silicon control gate 7. Through subsequent high fusing point metal film formation and silicide formation steps, CoSi<SB>2</SB>formed on the polycrystalline silicon control gate 7 is made into a flat film without including any projection toward a gate oxide film 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and as an example, relates to a method for manufacturing a semiconductor device including a step of forming a transition metal silicide layer in a self-aligned manner on the source and drain diffusions of a transistor and on a gate electrode.

In the recent miniaturization of semiconductor devices, especially in the manufacture of NOR type flash memory for the purpose of high-speed random access, the surface of the source / drain diffusion layer and the gate electrode is formed on the surface in order to reduce the parasitic resistance of the element. It is necessary to use a so-called salicide technique in which a refractory metal such as cobalt is affixed in a consistent manner. As this refractory metal silicide layer, cobalt silicide (CoSi ₂ ) is mainly used.

  However, in the manufacturing method using the salicide technique, as illustrated in FIG. 7, the silicide layer 415B formed on the source / drain region 409 of the silicon substrate 401 has irregularities, and as a result, the silicide layer Layer 415B approaches the location of the PN junction. For this reason, it has been pointed out that there is a drawback that the junction leakage current increases and varies more than when there is no silicide layer 415B.

  Further, as shown in FIG. 7, the diffusion of the silicide of the silicide layer 415A into the polycrystalline silicon of the polycrystalline silicon gate 407 proceeds along the grain boundary, so that the diffusion is performed at the grain boundary of the polycrystalline silicon gate 407. It progresses remarkably at the silicide interface in contact with. As a result, the diffusion proceeds non-uniformly at the interface between the polycrystalline silicon and the silicide, and the silicide layer 415A locally grows in a solid phase and reaches the interface with the gate insulating layer 404. Therefore, it has been pointed out that it causes a gate leak.

  Thus, as a technique for improving the PN junction leakage of silicide, for example, there is a technique described in Japanese Patent Application Laid-Open No. 10-242079 (Patent Document 1). Further, for example, a technique described in Japanese Patent Application Laid-Open No. 6-232390 (Patent Document 2) relates to a technique in which silicide on polycrystalline silicon locally suppresses solid phase growth.

Both of the above two conventional techniques solve the problem by setting the ion implantation for amorphization of silicon and polycrystalline silicon to a critical dose amount of 1.0 × 10 ¹⁴ ions / cm ² or more and an energy of 30 keV or more. It is carried out.

  Hereinafter, the conventional silicide technique described above will be described with reference to FIGS. 6A to 6G.

  6A to 6G are process cross-sectional views sequentially showing a conventional salicide process.

  First, as shown in FIG. 6A, an activation region 502 and an element isolation region 503 are formed in a silicon substrate 501 by using an STI (Shallow Trench Isolation) method. Further, on the silicon substrate 501, a gate oxide film 504, a polycrystalline silicon floating gate 505 having a sidewall 508 made of an insulating material on its side surface, a three-layer film (ONO film made of an oxide film, a nitride film, and an oxide film) 506, a polycrystalline silicon control gate 507 is formed.

Next, as shown in FIG. 6B, the source / drain region is formed by ion-implanting As + into a region where the N-channel transistor is to be formed later, and performing carrier activation heat treatment. 509 is formed. In the region where the P-channel transistor is to be formed, the source / drain region 509 is formed by implanting BF ₂ + ions into the portion that will later become the source / drain region and performing heat treatment for activating carriers.

Next, as shown in FIG. 6C, ion implantation of As +, Ar +, or Ge + is performed on the entire surface of the semiconductor device at 1.0 × 10 ¹⁴ ions / cm ² for the amorphization. Ions are implanted with the above dose and energy of 30 keV or more, and an amorphous layer 516 is formed. Thereafter, as shown in FIG. 6D, a cobalt (Co) film 511 and a titanium nitride (TiN) film 512 are sequentially deposited on the entire surface of the semiconductor device by sputtering. Note that the titanium nitride film 512 plays a role of preventing the cobalt film 511 from being oxidized during the subsequent heat treatment.

  Further, as shown in FIG. 6E, as the first heat treatment, heat treatment is performed at 500 to 550 ° C. for 60 seconds by a lamp annealing method. By this first heat treatment, silicon and cobalt react to form CoSi crystal layers 514A and 514B only on the polycrystalline silicon control gate 507 and the source / drain regions 509.

Thereafter, as shown in FIG. 6F, the TiN film 512 is removed by using a mixed solution of sulfuric acid and overwater. Finally, as shown in FIG. 6G, as the second heat treatment, heat treatment is performed at 750 to 850 ° C. for 30 seconds by a lamp annealing method. By this second heat treatment, the CoSi crystal layers 514A and 514B are phase-shifted to lower resistance CoSi ₂ crystal layers 515A and 515B.

  Through the above steps, the source / drain region 509 and the gate electrode (polycrystalline silicon gate 507) can be reduced to a sheet resistance of 10Ω / □ or less necessary for speeding up the MOS semiconductor device.

However, in the above-described conventional technique, a projection defect of the CoSi crystal layer 514A, which is cobalt silicide on the polycrystalline silicon control gate 507, cannot be avoided by making it amorphous. In addition, deterioration of device characteristics during high energy implantation and crystal defects remaining in silicon are unavoidable.
Japanese Patent Laid-Open No. 10-242079 Japanese Patent Laid-Open No. 06-232390

  Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of reducing a parasitic resistance by forming a silicide layer without incurring defects such as crystal defects, deterioration of device characteristics, and increase of leakage current. .

In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention provides an energy and a dose that modify a surface portion including a silicon region but do not make it amorphous with respect to a semiconductor substrate having a silicon region. And an ion implantation step of ion implantation into the surface portion,
A refractory metal film forming step of forming a refractory metal film on the surface portion after the ion implantation step;
And a silicide formation step of forming a silicide layer by reacting the refractory metal film with the surface portion.

  According to the method for manufacturing a semiconductor device of the present invention, in the ion implantation step, the surface portion including the silicon region is modified but not made amorphous. Therefore, according to the present invention, the silicide layer can be formed without incurring defects such as crystal defects, deterioration of device characteristics, and increase of leakage current caused by amorphizing silicon on the surface portion including the silicon region. A semiconductor device that can be formed and can reduce parasitic resistance can be manufactured.

  In one embodiment of the semiconductor device manufacturing method, the surface portion has a polycrystalline silicon portion.

  According to this embodiment, by performing ion implantation so that the polycrystalline silicon portion on the surface portion does not become amorphous, it is possible to avoid the protrusion defect of the silicide layer formed on the polycrystalline silicon portion, and to increase the leakage current. Parasitic resistance can be reduced without incurring such disadvantages.

  In one embodiment, the refractory metal film is a cobalt film.

  According to this embodiment, the cobalt silicide layer can be formed by reacting the cobalt film with the silicon on the surface portion on the surface portion including the silicon region.

  In one embodiment of the method of manufacturing a semiconductor device, the ion species for the ion implantation is argon or an inert element.

  According to this embodiment, since the ion species of the ion implantation is an inert element, the above-described crystal defect and protrusion defect can be further prevented from occurring.

In one embodiment of the semiconductor device manufacturing method, the ion implantation is performed with an energy of 30 keV or less and a dose of 1.0 × 10 ¹⁴ ions / cm ² or less.

  According to this embodiment, the above-mentioned crystal defects and projection defects can be avoided more reliably.

  In one embodiment of the semiconductor device manufacturing method, in the refractory metal film forming step, a titanium film and a titanium nitride film are sequentially deposited on the cobalt film, and then the silicide forming step is performed.

  According to this embodiment, the titanium film and the titanium nitride film can prevent the cobalt film from being oxidized during the heat treatment in the silicide formation step.

  In one embodiment of the method for manufacturing a semiconductor device, the film thickness of cobalt silicide formed in the silicide formation step is 30 to 70 nm.

  According to the method for manufacturing a semiconductor device of the present invention, in the ion implantation process, the surface portion including the silicon region is amorphized by modifying the surface portion including the silicon region but not amorphizing it. The silicide layer can be formed and the parasitic resistance of the semiconductor device can be reduced without incurring defects such as crystal defects, deterioration of device characteristics, and increase of leakage current.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. In this embodiment, a source / drain region and a polycrystalline silicon gate will be described as an example of a region where silicide is formed.

  A manufacturing method of a NOR type flash memory as a first embodiment of a manufacturing method of a semiconductor device of the present invention will be described with reference to process cross-sectional views shown in FIGS. 1A to 1G.

  First, as shown in FIG. 1A, an activation region 2 and an element isolation region 3 are formed on a silicon substrate 1 by using an STI (Shallow Trench Isolation) method. Further, on the silicon substrate 1, a gate oxide film 4, a polycrystalline silicon floating gate 5 having a side wall 8 made of an insulating material on its side surface, a three-layer film (ONO film made of an oxide film, a nitride film, and an oxide film) 6) A polycrystalline silicon control gate 7 is formed as a polycrystalline silicon portion.

Next, as shown in FIG. 1B, the source / drain region 9 is formed by implanting ions into a portion to be the source / drain region which is a silicon region and performing heat treatment for activating carriers. Here, the region for forming the N- channel transistor, the As + ions are implanted into the region for forming the P- channel transistor, a BF 2 ₊ ion implantation. The source / drain region 9 and the polycrystalline silicon control gate 7 form a surface portion.

Next, as shown in FIG. 1C, Ar (argon) + is ion-implanted at an energy of 10 keV with a dose amount of 1.0 × 10 ¹⁴ ions / cm ² or less over the entire surface of the semiconductor device including the silicon substrate 1. (Ion implantation process). In this ion implantation, the surface of the source / drain region 9 and the vicinity of the surface of the polycrystalline silicon control gate 7 that react later when the silicide layer is formed are not made amorphous but are modified. In this ion implantation, it is not always necessary to perform ion implantation using Ar + as an ion species, and an inert element of a rare gas may be used.

  Thereafter, as shown in FIG. 1D, a cobalt (Co) film 10 having a film thickness of 15 to 25 nm and a titanium (Ti) film 11 having a film thickness of 10 to 24 nm are formed on the entire surface of the semiconductor device including the silicon substrate 1. A titanium nitride (TiN) film 12 having a thickness of ˜45 nm is sequentially deposited by a sputtering method (a refractory metal film forming step).

  Next, the process proceeds to a silicide formation process, and as shown in FIG. 1E, heat treatment is performed at 500 to 550 ° C. for 60 seconds by a lamp annealing method (first heat treatment process). By this first heat treatment step, the silicon in the polycrystalline silicon control gate 7 and the source / drain region 9 reacts with the cobalt (Co) in the cobalt (Co) film 10, and the polycrystalline silicon control gate 7 and the source / drain are CoSi crystal films 14A and 14B are formed only on region 9.

After that, as shown in FIG. 1F, the TiN film 12 and the Ti film 11 are removed using a mixed solution of sulfuric acid and perwater, and further, a Ti / Co alloy film 13 is mixed using a mixed solution of ammonia and perwater. Remove. Finally, as shown in FIG. 1G, heat treatment is performed at 800 ° C. for 30 seconds by the lamp annealing method (second heat treatment step). By this second heat treatment, the CoSi crystals 14A and 14B are phase-transformed to the CoSi ₂ crystal films 15A and 15B having lower resistance. The CoSi ₂ crystal films 15A and 15B are formed with a film thickness of about 40 to 60 nm.

  This makes it possible to reduce the parasitic resistance of the source / drain regions and the gate electrode in the NOR flash memory intended for high-speed random access.

  Next, FIG. 2B shows a cross section of the semiconductor device manufactured in the above embodiment, and FIGS. 2A, 2C, and 2D show the semiconductor devices manufactured in Comparative Example 1, Comparative Example 2, and Comparative Example 3, respectively.

In the semiconductor device manufactured in the above embodiment shown in FIG. 2B, the surface of the source / drain region 9 and the vicinity of the surface of the polycrystalline silicon control gate 7 are not made amorphous in the ion implantation process shown in FIG. Ion implantation conditions (1.0 × 10 ¹⁴ ions / cm ² or less, 10 keV). Therefore, the CoSi ₂ crystal film 15 A formed on the polycrystalline silicon control gate 7 does not have a protrusion toward the gate oxide film 4 and is a flat film.

On the other hand, FIG. 2A does not have the ion implantation process of FIG. 1C in the above embodiment, does not perform Ar + implantation, and modifies the surface of the source / drain region 9 and the surface of the polycrystalline silicon gate 7 by making it amorphous. The semiconductor device manufactured by the manufacturing method (Comparative Example 1) which does not exist is shown. In the semiconductor device manufactured in Comparative Example 1, the CoSi ₂ crystal film 115 A formed on the polycrystalline silicon control gate 7 has a protrusion T 1 that faces the gate oxide film 4. Protrusion T1 of the CoSi ₂ crystal film 115A has the cause gate leakage.

On the other hand, FIG. 2C shows a manufacturing method in which Ar + implantation is performed to make the surface of the source / drain region 9 and the surface of the polycrystalline silicon control gate 7 amorphous in the ion implantation step of FIG. The semiconductor device manufactured in Example 2) is shown. Ion implantation conditions in this Comparative Example 2, the energy is 10 keV, the dose amount is 5.0 × ^{10 14} ions number / cm ^2. In the semiconductor device manufactured in Comparative Example 2, the CoSi ₂ crystal film 215 A formed on the polycrystalline silicon control gate 7 has a protrusion T _{2 that} faces the gate oxide film 4. This protrusion T2 is longer than the protrusion T1 in FIG. 2A.

FIG. 2D shows that in the ion implantation step, Ar + with an energy of 15 keV larger than that of Comparative Example 2 in FIG. 2C and a dose amount of 2.0 × 10 ¹⁵ ions / cm ² larger than that of Comparative Example 2 described above. The semiconductor device manufactured by the manufacturing method (Comparative Example 3) which performs ion implantation is shown. In the semiconductor device manufactured in Comparative Example 3, the CoSi ₂ crystal film 315A formed on the polycrystalline silicon control gate 7 has a protrusion T3 facing the gate oxide film 4, and this protrusion T3 is more than the protrusion T2 in FIG. 2C. Is also getting longer.

Thus, if there is no ion implantation step of FIG. 1C (FIG. 2A), CoSi ₂ crystal film 115A formed on the polysilicon control gate 7 has a projection T1 toward the gate oxide film 4. Further, even in the case where the ion implantation process is performed, the ion implantation conditions in which the surface of the source / drain region 9 and the surface of the polycrystalline silicon control gate 7 are made amorphous are compared with those in FIGS. 2C and 2D. As in Examples 2 and 3, the CoSi ₂ crystal films 215A and 315A were found to have protrusions T2 and T3 facing the gate oxide film 4.

On the other hand, as in this embodiment, in the ion implantation process, the surface of the source / drain region 9 and the vicinity of the surface of the polycrystalline silicon control gate 7 are not amorphized but modified so as to be modified ( 1.0 × ^{10 14} ions number / cm ² or less, by which the 10 keV), CoSi ₂ crystal film 15A formed on the polysilicon control gate 7, flat no projections toward the gate oxide film 4 It is a perfect film.

  Although the detailed cause of the defective protrusion of the silicide as in Comparative Examples 1, 2, and 3 in FIGS. 2A, 2C, and 2D has not been grasped, it can be considered as follows.

  As in Comparative Example 1 in FIG. 2A, the polycrystalline silicon control gate is not formed without the ion implantation process of this embodiment and the surface of the source / drain region 9 and the surface of the polycrystalline silicon control gate 7 are not made amorphous at all. 7 has a high concentration of arsenic, oxygen, and etching damage, and is bonded to Si with a high binding energy. If silicide formation is performed in this state, it may be considered that silicide with large unevenness is locally formed.

  On the other hand, as in Comparative Examples 2 and 3 of FIGS. 2C and 2D, the ion implantation process is performed, but the surface of the source / drain region 9 and the surface of the polycrystalline silicon control gate 7 are made amorphous by ion implantation. As a result, defects and oxygen knock-on occur in the polycrystalline silicon, and cobalt, which is a diffusing species, diffuses into the polycrystalline silicon during the silicidation and does not cause solid phase growth locally. It is thought.

  On the other hand, in the present embodiment, in the ion implantation step of FIG. 1C, Ar implantation conditions that do not amorphize but modify the surface of the source / drain region 9 and the vicinity of the surface of the polycrystalline silicon control gate 7. It was. With this non-amorphous ion implantation condition, even if arsenic or etching damage on the surface of the polycrystalline silicon is diffused into the silicon, the silicide grows uniformly in the formation of the silicide without inducing defects or oxygen knock-on. It is thought that.

  Next, FIG. 3 shows the defect rate in the charge retention characteristics by the polycrystalline silicon control gate 7. In FIG. 3, the rhombus marks indicate the defect rate of the semiconductor device manufactured in Comparative Example 3 in FIG. 2D, and in FIG. 3, the square mark (□) indicates the defect rate of the semiconductor device manufactured in the present embodiment in FIG. 2B. Indicates. This failure was determined by whether or not the charge retention state deteriorated when a voltage of 8.5 V was applied to the polycrystalline silicon control gate 7 for the voltage application time (seconds) indicated on the horizontal axis.

  As can be seen from the results shown in the characteristic diagram of FIG. 3, when the voltage for determination is applied for 10 seconds, the defect rate of the semiconductor device according to the present embodiment is 0 ppm, whereas that of Comparative Example 3 is 0. The defect rate tended to be 1000 ppm or more. That is, it was found that the charge retention state deteriorates in the semiconductor device according to Comparative Example 3 in FIG. 2D in which silicide protrusions are generated.

  Next, another embodiment of the present invention will be described with reference to a list shown in FIG. The columns No. 3 and No. 5 in the list of FIG. 4 correspond to other embodiments of the present invention. The column of No. 4 corresponds to the above-described embodiment. All the columns other than the columns No. 3 to No. 5 correspond to comparative examples in which the ion implantation conditions in the ion implantation step in the above-described embodiment are changed. For example, the column of No. 1 corresponds to the above-described comparative example 1, and the columns of No. 7 and No. 8 correspond to the above-described comparative example 2 and comparative example 3. Moreover, in the list of FIG. 4, the columns of No. 17 to No. 20 in which the ion species in the ion implantation step is As all show other comparative examples.

In the table of FIG. 4, “E + 13”, “E + 14”, and “E + 15” in the “dose amount (cm ⁻² )” are “× 10 ¹³ ”, “× 10 ¹⁴ ”, and “× 10 ¹⁵ ”, respectively. ". Further, in the list of FIG. 4, the “x” mark in the “protrusion defect” section indicates that a protrusion as shown in FIGS. 2A, 2C, and 2D has occurred, and the ◯ mark indicates that the above protrusion does not occur. ing. In the table of FIG. 4, the term “amorphization” is blank because the silicon is not amorphized in the ion implantation process, and the item “amorphization” is marked with a circle. This indicates that silicon is amorphized in the ion implantation process. In addition, the fact that the term “amorphization” is indicated by Δ indicates that both the case where silicon is amorphized and the case where silicon is not amorphized are observed in the ion implantation process. .

In the list of FIG. 4, the term “drain portion withstand voltage” represents the withstand voltage (V) of the drain portion when a constant current is applied to the drain portion. In the table of FIG. 4, the term “drive current” represents a read current when a voltage of 1.6 V is applied to the polycrystalline silicon control gate and 1.0 V is applied to the drain portion, and (E-05A) is × 10 ⁻⁵ A). In the list of FIG. 4, the term “silicide resistance” represents the silicide resistance of the source region.

Next, FIG. 5 is a graph in which the horizontal axis is ion implantation energy (keV) and the vertical axis is dose (cm ⁻² ), and the ion species in the list of FIG. .16 is shown. Note that “E + 13”, “E + 14”, “E + 15”, and “E + 16” on the vertical axis in FIG. 5 represent “× 10 ¹³ ”, “× 10 ¹⁴ ”, “× 10 ¹⁵ ”, and “× 10 ¹⁶ ”, respectively. ing. Further, No. 8 to No. 11 in the region R1 surrounded by the alternate long and short dash line in FIG. 5 indicate that the projection failure occurred, and No. 8 in the region R2 surrounded by the alternate long and short dashed line in FIG. Nos. 12 to 16 indicate that no defective protrusion occurred. Further, a curve G in FIG. 5 represents an amorphization boundary line. Amorphization occurs on the upper side of the curve G, but no amorphization occurs on the lower side of the curve G. In addition, a broken line arrow F in FIG. 5 indicates the direction of ion implantation conditions that improve the electrical characteristics of the manufactured semiconductor device.

  In the above embodiment, the refractory metal film is a cobalt film, but other refractory metal films such as a tungsten film, a titanium film, and a nickel film may be used. Moreover, in the said embodiment, although the ion seed | species of an ion implantation process was argon, it is good also as another inactive element.

It is sectional drawing which shows one manufacturing process of embodiment of the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1A. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1B. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1C. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1D. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1E. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 1F. 6 is a cross-sectional view showing a semiconductor device manufactured in Comparative Example 1. FIG. It is sectional drawing which shows the semiconductor device manufactured by the said embodiment. 6 is a cross-sectional view showing a semiconductor device manufactured in Comparative Example 2. FIG. 10 is a cross-sectional view showing a semiconductor device manufactured in Comparative Example 3. FIG. It is a characteristic view which shows the defect rate of the semiconductor device manufactured by the said embodiment, and the defect rate of the semiconductor device manufactured by the said comparative example 3. It is a figure which shows the list of the characteristics of the semiconductor device produced on each ion implantation conditions including the said embodiment and Comparative Examples 1-3. FIG. 5 is a graph showing the ion implantation conditions shown in FIG. 4 in a graph where the vertical axis represents the dose and the horizontal axis represents the implantation energy. It is sectional drawing which shows one manufacturing process of the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6A. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6B. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6C. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6D. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6E. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. 6F. It is a figure which shows typically the cross section which shows the protrusion of the silicide layer at the time of manufacturing with the conventional salicide technique.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Activation region 3 Element isolation region 4 Gate oxide film 5 Polycrystalline silicon floating gate 6 ONO film 7 Polycrystalline silicon control gate 8 Side wall 9 Source / drain region 10 Cobalt film (Co)
11 Titanium (Ti) film 12 Titanium nitride (TiN) film 13 Ti / Co alloy film 14A, 14B CoSi crystal film 15A, 15B CoSi ₂ crystal film 16 Amorphous layer

Claims (7)

An ion implantation step of ion-implanting the surface portion with energy and dose so as to modify the surface portion including the silicon region but not to make it amorphous with respect to a semiconductor substrate having a silicon region;
A refractory metal film forming step of forming a refractory metal film on the surface portion after the ion implantation step;
A method of manufacturing a semiconductor device, comprising: a silicide formation step of forming a silicide layer by reacting the refractory metal film with the surface portion. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the surface portion has a polycrystalline silicon portion. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device manufacturing method, wherein the refractory metal film is a cobalt film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the ion species of the ion implantation is argon or an inert element. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the ion implantation is performed with an energy of 30 keV or less and a dose of 1.0 × 10 ¹⁴ ions / cm ² or less. In the manufacturing method of the semiconductor device according to claim 3,
A method of manufacturing a semiconductor device, comprising: sequentially depositing a titanium film and a titanium nitride film on the cobalt film in the refractory metal film forming step, and then performing the silicide forming step. In the manufacturing method of the semiconductor device according to claim 3,
A method of manufacturing a semiconductor device, wherein a film thickness of cobalt silicide formed in the silicide forming step is 30 to 70 nm.

Images