JP2005260123A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device having an MIS transistor capable of decreasing a junction capacitance without lowering a resistance properties against a short channel effect, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device has a second conductive source/drain diffusion layers 36 arranged within a semiconductor substrate 10 by sandwiching a first conductive channel region, and a first conductive pocket region 24 formed between at least one of the source/drain diffusion layers 36 and the channel region. An effective impurity concentration of the source/drain diffusion layer 36 at the depth in which the pocket region 24 is formed is lower than the effective impurity concentration of the pocket region 24 at the same depth. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MIS transistor with a reduced junction capacitance in a source / drain region and a manufacturing method thereof.

  Along with miniaturization and high integration of semiconductor devices, it is required to increase the speed of MIS transistors. In order to improve the switching speed of the MIS transistor, it is necessary not only to shorten the gate length and increase the on-current, but also to reduce the gate capacitance. However, since the short channel effect becomes remarkable when the gate length is shortened, it is necessary to increase the well concentration and the pocket (halo) concentration as a countermeasure. As a result, the junction capacitance between the source / drain diffusion layer and the substrate increases, and sufficient characteristics cannot be obtained.

  As a method for reducing the junction capacitance, a method is known in which a low-concentration diffusion layer having a conductivity type opposite to that of the source / drain diffusion layer is formed immediately below the source / drain diffusion layer (see, for example, Patent Documents 1 to 3). ).

  A structure of a conventional semiconductor device will be described with reference to FIG.

  As shown in FIG. 14A, an element isolation film 102 is formed on the first conductivity type silicon substrate 100. A gate electrode 106 is formed on the element region defined by the element isolation film 102 with a gate insulating film 104 interposed therebetween. A source / drain diffusion layer 108 of the second conductivity type is formed in the silicon substrate 100 on both sides of the gate electrode 106. A pocket region 110 of the first conductivity type is formed on the channel region side of the source / drain diffusion layer 108. A low-concentration impurity layer 112 of the first conductivity type is formed below the bottom surface of the source / drain diffusion layer 108. Note that the semiconductor device illustrated in FIG. 14B has a structure in which the low-concentration impurity layer 112 is not formed.

When the low-concentration impurity layer 112 is formed below the bottom surface of the source / drain diffusion layer 108 as in the structure shown in FIG. 14A, the depletion layer 114 spreads in the substrate direction. Compared to the structure shown in FIG. 14B in which the low-concentration impurity layer 112 is not formed, the depletion layer 114 extends more in the substrate direction when the low-concentration impurity layer 112 is formed, and the junction capacitance is increased. Can be reduced.
JP 09-232444 A JP 2000-031479 A JP 2001-077361 A JP 2002-043567 A

  As shown in FIG. 15A, the junction capacitance between the source / drain diffusion layer 108 and the silicon substrate 100 exists in the area component (Cj) existing at the bottom of the source / drain diffusion layer and in the gate end region. And the gate end component (Cjg).

  FIG. 15B is a graph showing the relationship between the width of the source / drain diffusion layer and the junction capacitance in the structure shown in FIG. In FIG. 15B, the slope of the graph corresponds to the junction capacitance Cj of the area component, and the y-intercept corresponds to the junction capacitance Cjg of the gate end component. As is clear from the relationship of FIG. 15B, when the area of the source / drain diffusion layer is reduced (the interval d is reduced) as the element is miniaturized, the junction capacitance Cj of the area component is reduced. This means that as the MIS transistor is miniaturized, the ratio of the junction capacitance Cjg to the whole increases.

  The junction capacitance Cj of the area component can be reduced by the structure of the conventional semiconductor device shown in FIG. On the other hand, in the conventional semiconductor device shown in FIG. 14A, in order to reduce the junction capacitance of the gate end component, a low-concentration impurity layer of the second conductivity type is formed in the pocket region 110 and a depletion layer is formed in the channel direction. It needs to be stretched. However, the formation of the second conductivity type low-concentration impurity layer in the pocket region 110 means that the concentration of the pocket region 110 is lowered, and the short channel resistance is deteriorated.

  As described above, in the conventional semiconductor device, it is difficult to effectively reduce the junction capacitance Cjg of the gate end component that should be reduced most in the fine transistor without deteriorating the resistance to the short channel effect.

  An object of the present invention is to provide a semiconductor device capable of reducing the junction capacitance without reducing the resistance to the short channel effect and a method for manufacturing the same.

  According to an aspect of the present invention, a source / drain diffusion layer of a second conductivity type disposed in a semiconductor substrate with a channel region of the first conductivity type interposed therebetween, at least one of the source / drain diffusion layer, and the A pocket region of the first conductivity type formed between the channel region and the effective impurity concentration of the source / drain diffusion layer at a depth where the pocket region is formed is equal to the pocket region at the same depth. A semiconductor device having a lower effective impurity concentration is provided.

  According to another aspect of the present invention, a second conductivity type source / drain diffusion layer disposed in a semiconductor substrate with a first conductivity type channel region interposed therebetween, and at least one of the source / drain diffusion layers A pocket region of a first conductivity type formed between the first and the channel region, and the source / drain diffusion layer and the source / drain diffusion layer when the semiconductor substrate and the source / drain diffusion layer have the same potential A semiconductor device is provided in which the depletion layer formed between the pocket regions has a wider width extending toward the source / drain diffusion layer than the width extending toward the pocket region.

  According to the present invention, since the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is lower than the effective impurity concentration of the pocket region at the same depth, the junction capacitance Cjg of the gate end component is reduced. It can be greatly reduced. In such an impurity concentration profile, since the depletion layer extends to the source / drain diffusion layer side rather than the pocket region side, the short channel effect resistance is not deteriorated. Therefore, the parasitic capacitance can be reduced without deteriorating the short channel effect resistance.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.

  1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIG. 2 is a graph showing the distribution of effective impurity concentration in the depth direction, and FIG. 3 is a diagram showing the relationship of the depletion layer width in the semiconductor device according to the present embodiment. 4 is a diagram showing the spread of the depletion layer into the source / drain diffusion layer, FIG. 5 is a diagram showing the result of calculation of the spread of the depletion layer into the source / drain diffusion layer and the junction position by simulation, and FIG. A graph showing the relationship between the junction capacitance and the width of the source / drain diffusion layer, FIGS. 7 and 8 are process cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  An element isolation film 12 is formed on the first conductivity type silicon substrate 10. A gate electrode 20 is formed on the element region defined by the element isolation film 12 via a gate insulating film 18. A sidewall insulating film 30 is formed on the sidewall portion of the gate electrode 20. A source / drain diffusion layer 36 of the second conductivity type is formed in the silicon substrate 100 on both sides of the gate electrode 20. The source / drain diffusion layer 36 includes a shallow and high-concentration impurity diffusion region 22 whose end on the gate electrode 20 side extends to the lower side of the gate electrode 20 and a deeper end on the side of the gate electrode 20 that extends to the lower side of the sidewall insulating film 30. And a low-concentration impurity diffusion region 32. A pocket region 24 of the first conductivity type is formed on the channel region side of the source / drain diffusion layer 36.

  Here, the semiconductor device according to the present embodiment is mainly characterized by the impurity concentration distribution of the impurity diffusion region 32.

The effective impurity concentration distribution in the depth direction (impurity concentration distribution along the solid line arrow in FIG. 1) at the end of the gate electrode 20 is indicated by a solid line in FIG. In addition, the effective impurity concentration distribution in the depth direction (impurity concentration distribution along the dotted arrow in FIG. 1) at the end of the sidewall insulating film 30 is indicated by a dotted line in FIG. The effective impurity concentration means the concentration of impurities that effectively function as carriers,
Effective impurity concentration = | (acceptor concentration) − (donor concentration) |
Represented as:

  As is clear from the comparison between the solid line and the dotted line in FIG. 2A, in the semiconductor device according to the present embodiment, the second conductivity type impurity at the end of the sidewall insulating film 30 at the depth where the pocket region 24 is formed. The effective impurity concentration is lower than the effective impurity concentration of the first conductivity type impurity at the end of the gate electrode 20.

  That is, in the semiconductor device according to the present embodiment, the impurity diffusion region 32 has a depth at which the pocket region 24 is formed such that the effective impurity concentration of the impurity diffusion region 32 is lower than the effective impurity concentration of the pocket region 24. Impurity concentration is lowered. Alternatively, from the viewpoint of the depletion layer width, as shown in FIG. 3, the impurity concentration of the impurity diffusion region 32 is such that the depletion layer width on the source / drain region side is wider than the depletion layer width on the pocket region side. Is lowered.

  In the conventional semiconductor device, as shown in FIG. 2B, the effective impurity concentration of the impurity diffusion region 32 is higher than the effective impurity concentration of the pocket region 24 at the depth where the pocket region 24 is formed. ing. In this case, as shown in FIG. 4B, the depletion layer 42 formed between the pocket region 24 and the source / drain diffusion layer 36 does not spread so much on the source / drain diffusion layer 36 side.

  On the other hand, when the effective impurity concentration of the impurity diffusion region 32 is made lower than the effective impurity concentration of the pocket region 24 as in the semiconductor device according to the present embodiment, as shown in FIG. The depletion layer 42 formed between the drain diffusion layer 36 also extends to the source / drain diffusion layer 36 side.

FIG. 5 is a diagram showing an effective impurity concentration distribution in the vicinity of the drain of the N-type transistor calculated by a process simulator (manufactured by Synopsys, TSUPREM4). In the figure, the position of the PN junction is indicated by a solid line, and the position of the depletion layer is indicated by a dotted line. FIG. 5A shows a conventional structure using phosphorus ions, 10 keV, and 2 × 10 ¹⁵ cm ⁻² as ion implantation for forming the impurity diffusion region 32, and FIG. 5B shows impurity diffusion. This is the case of the first structure of the present invention using phosphorus ions, 10 keV, and 1 × 10 ¹⁴ cm ⁻² as ion implantation for forming the region 32. FIG. 5C shows the second structure of the present invention in which the side wall insulating film has a width of 45 nm. In the conventional structure and the first structure of the present invention, the width of the sidewall insulating film is 70 nm.

  From a comparison between FIG. 5A and FIG. 5B, it can be seen that the depletion layer spreads in the direction of the source / drain region by using the structure of the present invention. On the other hand, in the structure of the present invention, since the dose amount for forming the source / drain diffusion layer is small, it can be seen that the junction position also moves in the direction of the source / drain diffusion layer. This means that the parasitic capacitance immediately below the extension region increases and the junction capacitance Cjg is not sufficiently reduced. As shown in FIG. 5C, by thinning the sidewall insulating film from 70 nm to 45 nm, a junction is formed at a position substantially equal to that in the conventional structure, and the end of the depletion layer is expanded in the direction of the source / drain diffusion layer. Is possible.

  FIG. 6 is a graph showing the results of calculating the junction capacitance using a device simulator (Medici, manufactured by Synopsys). The terminal voltage was 0V. In the figure, the horizontal axis represents the width d of the source / drain diffusion layer similar to that shown in FIG. 15, and the vertical axis represents the junction capacitance C. Further, in the case of the conventional structure corresponding to FIG. 5A, the mark ◯ indicates the book corresponding to FIG. 5C in the case of the first structure of the present invention corresponding to FIG. 5B. This is the case of the second structure of the invention.

  As shown in FIG. 6, by applying the structure of the present embodiment (□ mark and Δ mark), the junction capacity can be reduced as compared with the conventional structure (◯ mark). Further, the junction capacitance can be further reduced by reducing the width of the sidewall insulating film from 70 nm (□ mark) to 45 nm (Δ mark).

As a result of linear approximation of each plot in FIG. 6, regarding the conventional structure, the first structure of the present invention, and the second structure of the present invention,
C = 1.67x + 0.36
C = 1.50x + 0.37,
C = 1.50x + 0.27,
Was obtained. When the junction capacitance C is represented by a linear function of C = Ad + B, the slope A represents the junction capacitance Cj (fF / μm ² ) of the area component, and the intercept B represents the junction capacitance Cjg (fF / μm) of the gate end component. . Therefore, from the above formula, when the first structure of the present invention is applied, the junction capacitance of the gate end component is slightly increased. It can be seen that the junction capacity of the end component can be reduced by about 25%. It can also be seen that by applying the first structure and the second structure of the present invention, the junction capacity of the area component can be reduced by about 10% compared to the conventional structure.

  Thus, according to the semiconductor device of this embodiment, the junction capacitance Cjg of the gate end component is significantly reduced, and the parasitic capacitance can be reduced without degrading the short channel effect resistance.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, a silicon oxide film having a film thickness of, for example, 400 nm is buried in the silicon substrate 10 by, eg, STI method to form an element isolation film 12 made of a silicon oxide film. In the figure, it is assumed that the left element region is an N-type transistor formation region and the right element region is a P-type transistor formation region.

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, using this photoresist film as a mask, for example, boron ions (B ⁺ ) are applied with acceleration energy. Ions are implanted at 150 keV and a dose of 3 × 10 ¹³ cm ⁻² to form a P well 14 in the N-type transistor formation region of the silicon substrate 10.

Subsequently, using the same photoresist film as a mask, for example, boron ions are ion-implanted with an acceleration energy of 30 keV and a dose of 1 × 10 ¹³ cm ⁻² . Thereby, threshold voltage control of the N-type transistor is performed.

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, for example, phosphorus ions (P ⁺ ) and acceleration energy are set to 300 keV using the photoresist film as a mask. Then, ions are implanted at a dose of 3 × 10 ¹³ cm ⁻² to form an N well 16 in the P-type transistor formation region of the silicon substrate 10.

Subsequently, using the same photoresist film as a mask, for example, arsenic ions (As ⁺ ) are ion-implanted with an acceleration energy of 100 keV and a dose of 1 × 10 ¹³ cm ⁻² . Thereby, the threshold voltage control of the P-type transistor is performed (FIG. 7A).

  Next, the silicon substrate 10 is thermally oxidized by, for example, a dry oxidation method, and a silicon oxide film having a thickness of, for example, 2 nm is formed on the element region. Thereby, a gate insulating film 18 made of a silicon oxide film is formed.

  Next, a 200 nm-thick non-doped polysilicon film is deposited on the gate insulating film 18 by CVD.

  The polysilicon film is patterned by photolithography and dry etching to form a gate electrode 20 made of the polysilicon film and having a gate length of, for example, 100 nm (FIG. 7B).

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, using this photoresist film and the gate electrode 20 as a mask, for example, arsenic ions are applied with acceleration energy. Ion implantation is performed with 3 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² to form an impurity diffusion region 22 that becomes an extension region of the N-type transistor.

Next, using the same photoresist film and gate electrode 22 as a mask, for example, boron ions, acceleration energy of 10 keV, dose amount of 1 × 10 ¹³ cm ⁻² , tilt angle with respect to the substrate normal of 30 degrees, and from four directions Ion implantation is performed to form a pocket region 24 in the N-type transistor formation region.

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, using this photoresist film and the gate electrode 20 as a mask, boron ions, for example, are applied with acceleration energy. Ion implantation is performed with 0.5 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form an impurity diffusion region 26 that becomes an extension region of the P-type transistor.

Next, using the same photoresist film and gate electrode 20 as a mask, for example, arsenic ions, acceleration energy of 40 keV, dose amount of 1 × 10 ¹³ cm ⁻² , tilt angle with respect to the substrate normal of 30 degrees, and four directions Each ion is implanted to form a pocket region 28 in the P-type transistor formation region (FIG. 7C).

  Next, after depositing, for example, a 100 nm-thickness silicon oxide film by the CVD method, this silicon oxide film is etched back by dry etching to form a sidewall insulating film 30 on the sidewall portion of the gate electrode 20. When a silicon oxide film having a thickness of 100 nm is used, the width of the sidewall insulating film 30 is, for example, 80 nm.

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, phosphorous ions, for example, are formed using the photoresist film, the gate electrode 20 and the sidewall insulating film 30 as a mask. Then, ion implantation is performed with an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁴ cm ⁻² , and an impurity diffusion region 32 having an impurity concentration lower than that of the pocket region 24 in a region deeper than the impurity diffusion region 22 of the N-type transistor formation region. Form. The ion implantation conditions for forming the impurity diffusion region 32 are appropriately set so that the effective impurity concentration is lower than the effective impurity concentration of the pocket region 24 at the same depth.

In the conventional process, for example, phosphorus ions are ion-implanted with an acceleration energy of 10 keV and a dose of 2 × 10 ¹⁵ cm ⁻² , and the ion implantation conditions used in the method for manufacturing the semiconductor device according to the present embodiment are as follows. Compared to the conditions, the concentration is one digit or more lower.

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, using this photoresist film, the gate electrode 20 and the sidewall insulating film 30 as a mask, for example, boron ions Is implanted with an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² , and an impurity diffusion region having a lower impurity concentration than the pocket region 28 in a region deeper than the impurity diffusion region 26 of the P-type transistor formation region. 34 is formed (FIG. 8A). The ion implantation conditions for forming the impurity diffusion region 34 are appropriately set so that the effective impurity concentration is lower than the effective impurity concentration of the pocket region 28 at the same depth.

In the conventional process, for example, boron ions are ion-implanted with an acceleration energy of 5 keV and a dose of 2 × 10 ¹⁵ cm ⁻² , and the ion implantation conditions used in the method for manufacturing the semiconductor device according to the present embodiment are as follows: Compared with conventional conditions, the concentration is one digit or more lower.

  Next, for example, a short-time heat treatment at 1050 ° C. for 1 second is performed to activate the implanted impurities. Thus, the source / drain diffusion layer 36 having the extension source / drain structure including the impurity diffusion regions 22 and 32 is formed in the N-type transistor formation region, and the extension source including the impurity diffusion regions 26 and 34 is formed in the P-type transistor formation region. A source / drain diffusion layer 38 having a drain structure is formed (FIG. 8B).

  Next, a silicide film 40 of, eg, a 30 nm-thickness is selectively formed on the source / drain diffusion layers 36 and 38 and the gate electrode 20 by a salicide process (FIG. 8C). For example, a cobalt film is deposited by sputtering, and this cobalt film is reacted with a silicon exposed portion by heat treatment to selectively form a cobalt silicide film, and then the unreacted cobalt film is removed to form a cobalt silicide film. Selectively form.

  Thus, according to the present embodiment, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is made lower than the effective impurity concentration of the pocket region at the same depth. The junction capacitance Cjg can be greatly reduced. In such an impurity concentration profile, since the depletion layer extends to the source / drain diffusion layer side rather than the pocket region side, the short channel effect resistance is not deteriorated. Therefore, the parasitic capacitance can be reduced without deteriorating the short channel effect resistance.

[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. Components similar to those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 9 is a diagram for explaining the problem of the semiconductor device according to the first embodiment, FIG. 10 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 11 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment. FIG.

  In the semiconductor device according to the first embodiment, by reducing the impurity concentration of the impurity diffusion region 32, the depletion layer 42 formed between the pocket layer 24 and the source / drain diffusion layer 36 becomes the source / drain diffusion layer 36 side. To spread. However, when the silicide film 40 is formed on the source / drain diffusion layer 36, it is assumed that the following problems occur as the element is miniaturized.

  That is, when the impurity diffusion region 22 serving as the extension region becomes shallow, as shown in FIG. 9, the depletion layer 42 and the source / drain diffusion layer 36 formed between the pocket region 24 and the source / drain diffusion layer 36 are formed. The distance from the silicide film 40 to be formed becomes extremely short. For this reason, in the worst case, the depletion layer 42 reaches the silicide film 40, and there is a possibility that the leakage current increases due to lattice defects (regions marked with ◯ in the figure). Further, since the impurity concentration in the vicinity of the interface between the silicide film 40 and the source / drain diffusion layer 36 decreases, there is a possibility that the contact resistance between the silicide film 40 and the source / drain diffusion layer 36 increases.

  In the present embodiment, a structure of a semiconductor device and a method for manufacturing the same that can suppress an increase in leakage current and contact resistance as described above are provided.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  As shown in FIG. 10, the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. The main feature of the semiconductor device according to the present embodiment is that the semiconductor layer 46 is formed on the source / drain diffusion layer 36 and the electrical connection portion between the silicide film 40 and the source / drain diffusion layer 36 is raised. It is in. The semiconductor layer 46 is a layer epitaxially grown on the source / drain diffusion layer 36, and the surface thereof is located higher than the surface of the silicon substrate 10, that is, the position of the interface between the silicon substrate 10 and the gate insulating film 18. Yes. By configuring the semiconductor device in this manner, the distance between the depletion layer 42 and the silicide film 40 can be increased, and leakage current due to lattice defects can be suppressed.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the element isolation film 12, the P well 14 and the N well 16 are formed in the silicon substrate 10 in the same manner as in the method for manufacturing the semiconductor device according to the first embodiment shown in FIG.

  Next, the silicon substrate 10 is thermally oxidized by, for example, a dry oxidation method, and a silicon oxide film having a thickness of, for example, 2 nm is formed on the element region. Thereby, a gate insulating film 18 made of a silicon oxide film is formed.

  Next, a 200 nm-thick non-doped polysilicon film is deposited on the gate insulating film 18 by CVD.

  Next, a silicon oxide film of, eg, a 5 nm-thickness is deposited on the polysilicon film by, eg, CVD, and a cap film 44 made of the silicon oxide film is formed.

  Next, the cap film 44 and the polysilicon film are patterned by photolithography and dry etching, and the upper surface is covered with the cap film 44, made of the polysilicon film, and the gate electrode 20 having a gate length of, for example, 100 nm is formed (FIG. 11 ( a)).

  Next, the pocket regions 24 and 28, the sidewall insulating film 30, and the source / drain diffusion layers 36 and 38 are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. Form.

  Next, a semiconductor layer 46 made of, for example, silicon having a thickness of 50 nm is selectively epitaxially grown on the source / drain diffusion layers 36 and 38 by CVD (FIG. 11B). At this time, since the cap film 44 is formed on the gate electrode 20, the semiconductor layer 46 is not formed on the gate electrode 20.

  Next, the silicon oxide film corresponding to, for example, 10 nm is etched by wet etching, for example, and the cap film 44 on the gate electrode 20 is removed.

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, phosphorous ions, for example, are formed using the photoresist film, the gate electrode 20 and the sidewall insulating film 30 as a mask. Then, ion implantation is performed with an acceleration energy of 6 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . This ion implantation is compensation ion implantation for the gate electrode 20 and the source / drain diffusion layer 36 of the N-type transistor, prevents depletion of the gate electrode 20, and contact resistance between the semiconductor layer 46 and the silicide layer 42. There is a reduction effect.

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, using this photoresist film, the gate electrode 20 and the sidewall insulating film 30 as a mask, for example, boron ions Are ion-implanted with an acceleration energy of 3 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . This ion implantation is compensation ion implantation for the gate electrode 20 and the source / drain diffusion layer 38 of the P-type transistor, prevents depletion of the gate electrode 20, and contact resistance between the semiconductor layer 46 and the silicide layer 42. There is a reduction effect.

  Next, for example, a short-time heat treatment at 1050 ° C. for 1 second is performed to activate the implanted impurities.

  Next, for example, a silicide film 40 of, eg, a 30 nm-thickness is selected on the semiconductor layer 46 and the gate electrode 20 by the salicide process in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. (FIG. 11C).

  Thus, according to the present embodiment, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is made lower than the effective impurity concentration of the pocket region at the same depth. The junction capacitance Cjg can be greatly reduced. In such an impurity concentration profile, since the depletion layer extends to the source / drain diffusion layer side rather than the pocket region side, the short channel effect resistance is not deteriorated. Therefore, the parasitic capacitance can be reduced without deteriorating the short channel effect resistance.

  In addition, the semiconductor layer is grown on the source / drain diffusion layer to raise the electrical connection between the silicide film and the source / drain diffusion layer, so that the distance between the depletion layer and the silicide film can be increased, and the lattice defect Leakage current due to can be suppressed.

[Third Embodiment]
A method for fabricating a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 11 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In the present embodiment, another method for manufacturing the semiconductor device according to the second embodiment shown in FIG. 10 will be described. FIG. 12 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, in the same way as in the method of manufacturing the semiconductor device according to the second embodiment shown in FIG. 11A, an element isolation film 12, a P well 14, an N well 16, a gate insulating film 18 and a top surface are cap films. The gate electrode 20 covered with 44 is formed (FIG. 12A).

  Next, after depositing, for example, a silicon nitride film having a thickness of 100 nm by the CVD method, the silicon nitride film is etched back by dry etching to form a sidewall insulating film 48 on the sidewall portion of the gate electrode 20.

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, phosphorus ions, for example, are formed using the photoresist film, the gate electrode 20 and the sidewall insulating film 48 as a mask. The impurity diffusion region 32 is formed by ion implantation with an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁴ cm ⁻² .

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, using this photoresist film, the gate electrode 20 and the sidewall insulating film 48 as a mask, for example, boron ions Are implanted with an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² to form an impurity diffusion region 34 (FIG. 12B).

  Next, a semiconductor layer 46 made of silicon having a film thickness of, for example, 50 nm is selectively epitaxially grown on the impurity diffusion regions 32 and 34 by CVD. At this time, since the cap film 44 is formed on the gate electrode 20, the semiconductor layer 46 is not formed on the gate electrode 20 (FIG. 12C).

Note that the semiconductor device manufacturing method according to the present embodiment is characterized in that the semiconductor layer 46 is formed before the impurity diffusion layers 22 and 26 and the pocket regions 24 and 28 serving as extensions are formed. This is because if the surface concentration of the silicon substrate 10 during the epitaxial growth of the semiconductor layer 46 is too high, the speed of the epitaxial growth becomes slow. For this purpose, in order to form the semiconductor layer 46 in a state where the surface concentration of the silicon substrate 10 is 1 × 10 ¹⁹ cm ⁻² or less, the impurity diffusion layers 22 and 26 that become extensions after the formation of the semiconductor layer 46 and pockets are formed. The regions 24 and 28 are formed.

  From the viewpoint of reducing the surface concentration of the silicon substrate 10 and improving the growth rate of the semiconductor layer 46, it is desirable to form the impurity diffusion layers 32 and 34 after the growth of the semiconductor layer 46. However, when the thickness of the semiconductor layer 46 is large, it is necessary to increase the ion implantation energy when forming the impurity diffusion layers 32 and 34. As a result, the implanted ions penetrate through the gate insulating film, resulting in the impurity concentration of the channel. May change. Accordingly, whether the semiconductor layer 46 is formed first or the impurity diffusion layers 32 and 34 is formed first depends on the film thickness and growth rate of the semiconductor layer 46, the implantation energy when forming the impurity diffusion layers 32 and 34, and the like. Accordingly, it is desirable to select appropriately.

  Next, the silicon oxide film corresponding to, for example, 10 nm is etched by wet etching, for example, and the cap film 44 on the gate electrode 20 is removed.

Next, after forming a photoresist film (not shown) that exposes the N-type transistor formation region and covers the P-type transistor formation region, phosphorus ions, for example, are formed using the photoresist film, the gate electrode 20 and the sidewall insulating film 48 as a mask. Then, ion implantation is performed with an acceleration energy of 6 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . This ion implantation is compensation ion implantation for the gate electrode 20 and the source / drain diffusion layer 36 of the N-type transistor, prevents depletion of the gate electrode 20, and contact resistance between the semiconductor layer 46 and the silicide layer 42. There is a reduction effect.

Next, after forming a photoresist film (not shown) that exposes the P-type transistor formation region and covers the N-type transistor formation region, using this photoresist film, the gate electrode 20 and the sidewall insulating film 48 as a mask, for example, boron ions Are ion-implanted with an acceleration energy of 3 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . This ion implantation is compensation ion implantation for the gate electrode 20 and the source / drain diffusion layer 38 of the P-type transistor, prevents depletion of the gate electrode 20, and contact resistance between the semiconductor layer 46 and the silicide layer 42. There is a reduction effect.

  Next, for example, a short-time heat treatment at 1050 ° C. for 1 second is performed to activate the implanted impurities. In the semiconductor device manufacturing method according to the present embodiment, the impurity diffusion layers 22 and 26 and the pocket regions 24 and 28 that become extensions during the active heat treatment process are not formed. In the manufacturing method, heat treatment can be performed at a higher temperature or for a longer time than the heat treatment performed after the step shown in FIG. Therefore, activation of impurities, particularly activation of impurities in the gate electrode can be sufficiently performed.

  Next, the sidewall insulating film 48 is removed by, eg, wet etching (FIG. 13A).

  Next, impurity diffusion regions 22 and 26 and pocket regions 24 and 28 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIG. 7C (FIG. 13B).

  Next, short-time heat treatment is performed at 1025 ° C. for 1 second, for example, to activate the implanted impurities. Thus, the source / drain diffusion layer 36 having the extension source / drain structure including the impurity diffusion regions 22 and 32 is formed in the N-type transistor formation region, and the extension source including the impurity diffusion regions 26 and 34 is formed in the P-type transistor formation region. A source / drain diffusion layer 38 having a drain structure is formed.

  Next, after depositing, for example, a 100 nm-thickness silicon oxide film by the CVD method, this silicon oxide film is etched back by dry etching to form a sidewall insulating film 30 on the sidewall portion of the gate electrode 20.

  Next, a silicide film 40 of, eg, a 30 nm-thickness is selectively formed on the semiconductor layer 46 and the gate electrode 20 by a salicide process in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIG. (FIG. 13C).

  Thus, according to the present embodiment, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is made lower than the effective impurity concentration of the pocket region at the same depth. The junction capacitance Cjg can be greatly reduced. In such an impurity concentration profile, since the depletion layer extends to the source / drain diffusion layer side rather than the pocket region side, the short channel effect resistance is not deteriorated. Therefore, the parasitic capacitance can be reduced without deteriorating the short channel effect resistance.

  In addition, since the semiconductor layer is grown on the source / drain region and the gate electrode and the semiconductor layer are doped before the extension and pocket regions are formed, the gate electrode and the gate region are not affected without affecting the profile of the extension and pocket regions. Impurities doped in the semiconductor layer can be sufficiently activated.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above embodiment, paying attention to the junction capacitance Cjg of the gate end component, the effective impurity concentration of the source / drain diffusion layer at the depth where the pocket region is formed is set to be larger than the effective impurity concentration of the pocket region at the same depth. Although the junction capacitance Cjg is reduced by setting it low, a configuration that can further reduce the junction capacitance Cj of the area component is also possible. For example, in the semiconductor device according to the first embodiment shown in FIG. 1, the effective conditions in the vicinity of the bottom surfaces of the source / drain diffusion layers 36 and 38 are optimized by optimizing the implantation conditions of the impurity diffusion regions 32 and 34 in FIG. By making the impurity concentration lower than the effective impurity concentration of the well, the depletion layer at the bottom also extends to the source / drain diffusion layer side, and the junction capacitance Cj of the area component can also be reduced.

  In the first to third embodiments, the gate electrode 20 is simultaneously doped by ion implantation for forming the impurity diffusion regions 22, 26, 32, and 34. For this reason, if the dose amount of the ion implantation for forming the impurity diffusion regions 32 and 34 is reduced in order to reduce the junction capacitance of the gate end component, the dose amount implanted into the gate electrode 20 is also reduced. If the dose amount injected into the gate electrode 20 is small, the impurity concentration of the gate electrode 20 is lowered, so that the gate electrode 20 at the interface with the gate insulating film 18 is depleted and the drain current is reduced. On the other hand, if the dose of ion implantation for forming the impurity diffusion regions 22 and 26 is increased instead, the impurity diffusion regions 22 and 26 spread in the depth direction and the lateral direction, and the short channel effect is deteriorated.

In such a case, it is desirable to dope the polysilicon film after deposition of the polysilicon film to be the gate electrode 20 and before patterning. Doping before the patterning of the polysilicon film can increase the ion implantation dose to the gate electrode 20 without affecting the impurity concentration distribution in the source / drain regions. For example, phosphorus ions are ion-implanted into the polysilicon film in the N-type transistor formation region with an acceleration energy of 10 keV and a dose amount of 2 × 10 ¹⁵ cm ⁻² , and the polysilicon film in the P-type transistor formation region is For example, boron ions are ion-implanted with an acceleration energy of 5 keV and a dose of 2 × 10 ¹⁵ cm ⁻² .

  Moreover, in the said embodiment, although the pocket area | region was provided in the source diffusion layer side and the drain diffusion layer side, respectively, you may make it provide only in any one (for example, drain diffusion layer side). In this case, at least the effective impurity concentration of the source / drain diffusion layer (for example, the drain diffusion layer) on the side where the pocket region is formed may be lower than the effective impurity concentration of the pocket region at the same depth.

  As detailed above, the characteristics of the present invention are summarized as follows.

(Supplementary Note 1) A source / drain diffusion layer of a second conductivity type disposed in a semiconductor substrate with a channel region of the first conductivity type interposed therebetween,
A pocket region of a first conductivity type formed between at least one of the source / drain diffusion layers and the channel region;
An effective impurity concentration of the source / drain diffusion layer at a depth where the pocket region is formed is lower than an effective impurity concentration of the pocket region at the same depth.

(Additional remark 2) The source / drain diffused layer of the 2nd conductivity type arrange | positioned on both sides of the channel region of the 1st conductivity type in the semiconductor substrate,
A pocket region of a first conductivity type formed between at least one of the source / drain diffusion layers and the channel region;
The depletion layer formed between the source / drain diffusion layer and the pocket region when the semiconductor substrate and the source / drain diffusion layer are at the same potential has a width larger than the width extending toward the pocket region. / A semiconductor device characterized by having a wide width extending toward the drain diffusion layer.

(Appendix 3) In the semiconductor device according to Appendix 1 or 2,
An effective impurity concentration of the source / drain diffusion layer on the surface side of the semiconductor substrate is higher than an effective impurity concentration at a depth where the pocket region is formed.

(Appendix 4) In the semiconductor device according to any one of appendices 1 to 3,
A semiconductor device further comprising a semiconductor layer grown on the semiconductor substrate in a region where the source / drain diffusion layer is formed.

(Additional remark 5) The 2nd conductivity type 1st impurity is introduce | transduced into the 1st conductivity type area | region of a semiconductor substrate, The 2nd conductivity type source / drain diffusion arrange | positioned on both sides of the said 1st conductivity type channel area | region Forming a layer;
Introducing a second impurity of the first conductivity type into the semiconductor substrate, and forming a pocket region of the first conductivity type between at least one of the source / drain diffusion layers and the channel region. And
In the step of forming the source / drain diffusion layer and the step of forming the pocket region, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is equal to that of the pocket region at the same depth. A method for manufacturing a semiconductor device, wherein conditions for introducing the first impurity and the second impurity are controlled so as to be lower than an effective impurity concentration.

(Additional remark 6) The process of forming a gate electrode on the area | region of the 1st conductivity type of a semiconductor substrate,
Introducing a first conductivity type first impurity into the semiconductor substrate using the gate electrode as a mask to form a first impurity diffusion layer;
Introducing a second impurity of the first conductivity type into the semiconductor substrate using the gate electrode as a mask to form a second impurity diffusion layer;
Forming a sidewall insulating film on the sidewall portion of the gate electrode;
A step of introducing a third impurity of the second conductivity type into the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask to form a third impurity diffusion layer;
The source / drain diffusion layer of the second conductivity type comprising the first impurity diffusion layer and the third impurity diffusion layer and disposed with the channel region of the first conductivity type interposed therebetween, the channel region, A method of manufacturing a semiconductor device, wherein a pocket region of the first conductivity type is formed between a source / drain diffusion layer,
In the step of forming the second impurity diffusion layer and the step of forming the third impurity diffusion layer, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is the same depth. The method for manufacturing a semiconductor device, wherein the introduction conditions of the second impurity and the third impurity are controlled so as to be lower than the effective impurity concentration of the pocket region in

(Supplementary note 7) In the method for manufacturing a semiconductor device according to supplementary note 6,
The method of manufacturing a semiconductor device, further comprising a step of growing a semiconductor layer on the third impurity diffusion layer after the step of forming the sidewall insulating film.

(Appendix 8) In the method for manufacturing a semiconductor device according to Appendix 7,
A step of introducing a fourth impurity of the second conductivity type into the semiconductor layer using the gate electrode and the sidewall insulating film as a mask after the step of forming the semiconductor layer. Production method.

(Appendix 9) In the method for manufacturing a semiconductor device according to any one of appendices 6 to 8,
After the step of forming the third impurity diffusion layer, the method further includes the step of removing the sidewall insulating film,
The method of manufacturing a semiconductor device, wherein the step of forming the first impurity diffusion layer and the step of forming the second impurity diffusion layer are performed after the step of removing the sidewall insulating film.

(Additional remark 10) In the manufacturing method of the semiconductor device of Additional remark 9,
A semiconductor device characterized by further comprising a heat treatment step for activating the third impurity after the step of forming the third impurity diffusion layer and before the step of removing the sidewall insulating film. Production method.

(Appendix 11) In the method for manufacturing a semiconductor device according to any one of appendices 6 to 10,
The step of forming the gate electrode includes a step of introducing a fifth impurity of the second conductivity type after deposition of the semiconductor layer to be the gate electrode and before patterning.

It is a schematic sectional drawing which shows the structure of the semiconductor device by 1st Embodiment of this invention. It is a graph which shows the depth direction distribution of effective impurity concentration. It is a figure which shows the relationship of the depletion layer width in the semiconductor device by 1st Embodiment of this invention. It is a figure explaining the spread of the depletion layer in a source / drain diffused layer. It is a figure which shows the result of having calculated the spread of the depletion layer to the source / drain diffused layer, and the junction position by simulation. It is a graph which shows the relationship between junction capacity | capacitance and the width | variety of a source / drain diffused layer. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. FIG. 9 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is a figure explaining the subject of the semiconductor device by a 1st embodiment. It is a schematic sectional drawing which shows the structure of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the conventional semiconductor device. It is a figure which shows the relationship between refinement | miniaturization of an element and junction capacitance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation film 14 ... P well 16 ... N well 18 ... Gate insulating film 20 ... Gate electrodes 22, 26, 32, 34 ... Impurity diffusion regions 24, 28 ... Pocket regions 30, 48 ... Side wall insulating films 36, 38 ... Source / drain diffusion layer 40 ... Silicide film 42 ... Depletion layer 44 ... Cap film 46 ... Semiconductor layer 100 ... Silicon substrate 102 ... Element isolation film 104 ... Gate insulating film 106 ... Gate electrode 108 ... Source / drain diffusion layer 110 ... pocket region 112 ... low-concentration impurity layer 114 ... depletion layer

Claims (5)

A second conductivity type source / drain diffusion layer disposed in the semiconductor substrate with the first conductivity type channel region interposed therebetween;
A pocket region of a first conductivity type formed between at least one of the source / drain diffusion layers and the channel region;
An effective impurity concentration of the source / drain diffusion layer at a depth where the pocket region is formed is lower than an effective impurity concentration of the pocket region at the same depth. A second conductivity type source / drain diffusion layer disposed in the semiconductor substrate with the first conductivity type channel region interposed therebetween;
A pocket region of a first conductivity type formed between at least one of the source / drain diffusion layers and the channel region;
The depletion layer formed between the source / drain diffusion layer and the pocket region when the semiconductor substrate and the source / drain diffusion layer are at the same potential has a width larger than the width extending toward the pocket region. / A semiconductor device characterized by having a wide width extending toward the drain diffusion layer. The semiconductor device according to claim 1 or 2,
A semiconductor device further comprising a semiconductor layer grown on the semiconductor substrate in a region where the source / drain diffusion layer is formed. A second conductivity type first impurity is introduced into the first conductivity type region of the semiconductor substrate to form a second conductivity type source / drain diffusion layer disposed with the first conductivity type channel region interposed therebetween. Process,
Introducing a second impurity of the first conductivity type into the semiconductor substrate, and forming a pocket region of the first conductivity type between at least one of the source / drain diffusion layers and the channel region. And
In the step of forming the source / drain diffusion layer and the step of forming the pocket region, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is equal to that of the pocket region at the same depth. A method for manufacturing a semiconductor device, wherein conditions for introducing the first impurity and the second impurity are controlled so as to be lower than an effective impurity concentration. Forming a gate electrode on the first conductivity type region of the semiconductor substrate;
Introducing a first conductivity type first impurity into the semiconductor substrate using the gate electrode as a mask to form a first impurity diffusion layer;
Introducing a second impurity of the first conductivity type into the semiconductor substrate using the gate electrode as a mask to form a second impurity diffusion layer;
Forming a sidewall insulating film on the sidewall portion of the gate electrode;
A step of introducing a third impurity of the second conductivity type into the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask to form a third impurity diffusion layer;
The source / drain diffusion layer of the second conductivity type comprising the first impurity diffusion layer and the third impurity diffusion layer and disposed with the channel region of the first conductivity type interposed therebetween, the channel region, A method of manufacturing a semiconductor device, wherein a pocket region of the first conductivity type is formed between a source / drain diffusion layer,
In the step of forming the second impurity diffusion layer and the step of forming the third impurity diffusion layer, the effective impurity concentration of the source / drain diffusion layer at the depth at which the pocket region is formed is the same depth. The method for manufacturing a semiconductor device, wherein the introduction conditions of the second impurity and the third impurity are controlled so as to be lower than the effective impurity concentration of the pocket region in

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