JP2000174270A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the parastic resistance of an impurity diffusion layer and reduce the depth thereof. SOLUTION: A gate oxide film 601 and a gate electrode 602 are formed on a P-type semiconductor substrate 600 in sequence, and an oxide film 603 is formed on the entire surface of the semiconductor 600. After a sidewall 604 is formed on both side surfaces of the gate electrode 602, an N-type impurity is applied thereto through ion implantation by using the gate electrode 602 and sidewall 604 as a mask, and the entire substrate is heated so as to form an N-type first impurity diffusion layer 605. The oxide film 603 exposing over the semiconductor substrate 600 is removed, and a silicide film 607 is formed on the surfaces of the gate electrode 602 and first impurity diffusion layer 605, and then the sidewall 604 is removed. An N-type impurity is applied through ion implantation by using the gate electrode 602 as a mask, and the entire substrate is heated so as to form an N-type second impurity diffusion layer 608 in a shallower area than the first impurity diffusion layer 605.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS type semiconductor device which realizes high speed and low power consumption while achieving ultra-high integration of an integrated circuit.

[0002]

2. Description of the Related Art With the ultra-high integration of integrated circuits, MOS
There is a demand for miniaturization of type transistors. In order to realize the miniaturization of the MOS transistor, it is necessary to suppress the short channel effect.
It is necessary to reduce the depth of the impurity diffusion layer in the type transistor.

[0003] Hereinafter, a method of manufacturing a conventional MOS type semiconductor device will be described with reference to FIGS. 14 (a) to 14 (c) and 15 (a).
This will be described with reference to FIG.

First, as shown in FIG. 14A, a gate insulating film 11 and a gate electrode 12 are sequentially formed on a semiconductor substrate 10 of a first conductivity type.

Next, as shown in FIG. 14B, a second conductivity type impurity is ion-implanted into the semiconductor substrate 10 using the gate electrode 12 as a mask to form a first impurity layer 13A.
To form

Next, at a temperature of about 700.degree.
After a nitride film is deposited over the entire surface of the gate electrode 12, anisotropic etching is performed on the nitride film to form sidewalls 1 on both side surfaces of the gate electrode 12, as shown in FIG.
4 is formed.

Next, as shown in FIG. 15A, a second conductivity type impurity is ion-implanted into the semiconductor substrate 10 by using the gate electrode 12 and the side wall 14 as a mask to form a first impurity layer 13A. A second impurity layer 15A of the second conductivity type is formed in a deeper region. After that, about 900
The first impurity layer 13A and the second impurity layer 15A are activated by performing a short-time heat treatment at a temperature of about 1000 ° C. for about 10 seconds, so that the first impurity diffusion layer 13 and the second impurity diffusion The layer 15 is formed (see FIG. 15B).

Next, after depositing a cobalt film having a thickness of about 10 nm over the entire surface of the semiconductor substrate 10 by, for example, a sputtering method, a titanium nitride film having a thickness of about 20 nm is further deposited. Then, about 55
A heat treatment is performed at a temperature of 0 ° C. for about 10 seconds. Next, after selectively removing the titanium nitride film present on the semiconductor substrate 10 and the unreacted cobalt film present on the sidewalls 14 using an etching solution such as sulfuric acid and hydrogen peroxide solution, A heat treatment is performed at a temperature of about 800 ° C. for about 10 seconds, and as shown in FIG.
A cobalt silicide film 16 having a thickness of about 30 nm is formed in a self-aligned manner on each surface of the source / drain regions.

Although the nitride film is used for forming the side wall, an oxide film may be used instead of the nitride film, and the cobalt film is used for forming the silicide film. May be used.

[0010]

By the way, the conventional MO
In the manufacturing method of the S-type semiconductor device, the depth of the impurity diffusion layer is made shallow, so that the implantation energy at the time of impurity ion implantation is reduced, and the parasitic energy resulting from the shallow depth of the impurity diffusion layer is reduced. In order to suppress an increase in resistance, the implantation dose at the time of ion implantation of impurities tends to be increased.

However, as the implantation energy of the impurity is reduced and the implantation dose is increased, the depth of the impurity diffusion layer cannot be reduced as designed or the increase in the parasitic resistance of the impurity diffusion layer cannot be suppressed. Problems have arisen.

In view of the foregoing, it is an object of the present invention to reduce the depth of an impurity diffusion layer while suppressing an increase in parasitic resistance of the impurity diffusion layer.

[0013]

According to the present invention, as the impurity implantation energy is reduced and the implantation dose is increased, the depth of the impurity diffusion layer cannot be reduced as designed, or the impurity diffusion layer cannot be reduced. In order to investigate the cause of an increase in the parasitic resistance of the semiconductor device, the impurity concentration distribution of the impurity diffusion layer was examined.

The results will be described below with reference to FIGS.
7 (a) and 7 (b).

FIG. 16 shows a cross-sectional structure of a conventional MOS type semiconductor device, and the conventional MO type semiconductor device shown in FIG.
The same members as those in the cross-sectional view showing one step in the method of manufacturing the S-type semiconductor device are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 17A shows an impurity concentration distribution in the substrate depth direction (XX direction in FIG. 16) in the first impurity diffusion layer 13 shown in FIG. 16, and FIG. ,
The direction of the main surface of the substrate in the first impurity diffusion layer 13 (FIG. 16)
(Y-Y direction). Note that in FIGS. 17 (a) and 17 (b), the vertical axis showing the impurity concentration represents the logarithm log C _A of the impurity concentration C _A.

As shown in FIG. 17A, the characteristic of the impurity concentration distribution in the substrate depth direction in the first impurity diffusion layer 13 is that the rate of change of the impurity concentration with respect to the depth, that is, the gradient of the graph is steep. In other words, the graph has a flared distribution in which the slope of the graph decreases as the depth increases, and an inactive region (inversely, an activation region) indicating an impurity concentration distribution region that does not contribute to the actual operation of the transistor. The region indicates a region of an impurity concentration distribution that contributes to the actual operation of the transistor), that is, the ratio of the amount of impurities activated by the heat treatment to the amount of ion implantation of impurities (hereinafter, referred to as an activation rate). Is low. For this reason, the impurities are distributed to a deep position, so that the depth of the impurity diffusion layer is deep, and the activation concentration of the impurity diffusion layer is reduced overall and the activation rate of the impurity is low. The parasitic resistance of the impurity diffusion layer increases.

The present inventor has further studied the cause of the above-mentioned impurity concentration distribution. As a result, the low-temperature heat treatment or the like for forming the sidewalls 14 performed after the formation of the first impurity layer 13A causes accelerated diffusion of the impurity, so that the impurity moves to a deep position and the impurity concentration distribution is reduced. It has been found that the distribution becomes wider and the activation rate of impurities decreases.

More specifically, for example, in a CMOS transistor having a size of 100 nm, a depth of a portion adjacent to a channel region of a semiconductor substrate in an impurity diffusion layer is required to be 20 to 30 nm, while a sidewall is formed. The low-temperature heat treatment causes accelerated diffusion of the impurities and moves the impurities by several tens of nm, so that a target shallow impurity diffusion layer cannot be formed.

The present invention has been made based on the above findings, and the activation concentration of the impurity diffusion layer is lower than the predetermined activation concentration over the entire region in the substrate depth direction and the substrate main surface direction. It is set high and realizes that the junction region between the impurity diffusion layer and the semiconductor substrate has a steep impurity concentration gradient.

Specifically, the semiconductor device according to the present invention comprises:
A gate electrode formed on a main surface of a semiconductor substrate of a first conductivity type via a gate insulating film, a first impurity diffusion layer of a second conductivity type formed in a source / drain region of the semiconductor substrate; A second impurity diffusion layer of a second conductivity type formed in a region of the substrate closer to the channel region than the first impurity diffusion layer and shallower than the first impurity diffusion layer; The activation concentration is set higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the junction region between the second impurity diffusion layer and the semiconductor substrate has a steep impurity concentration. It has a gradient of Here, the steep impurity concentration gradient specifically means a gradient of 10 ⁶ (atom / cm ³ ) / μm or more.

According to the semiconductor device of the present invention, the activation concentration of the second impurity diffusion layer is set higher than the predetermined activation concentration in the substrate depth direction and the substrate main surface direction. Since the junction region between the second impurity diffusion layer and the semiconductor substrate has a steep impurity concentration gradient, the depth of the second impurity diffusion layer is reduced while suppressing an increase in the parasitic resistance of the second impurity diffusion layer. Can be made shallower.

According to the first method of manufacturing a semiconductor device of the present invention, there is provided a gate electrode forming step of selectively forming a gate electrode on a first conductivity type semiconductor substrate via a gate insulating film; An oxide film deposition step of depositing an oxide film over the entire surface, and ion implantation of a second conductivity type impurity into the semiconductor substrate using the gate electrode as a mask to form a second conductivity type impurity diffusion layer. Forming an impurity diffusion layer.

According to the first method of manufacturing a semiconductor device, an oxide film is deposited over the entire surface of a semiconductor substrate after forming a gate electrode, and then ion implantation of impurities for forming an impurity diffusion layer is performed. Therefore, the depth at which the impurity is implanted can be reduced, and the impurity can be prevented from sneaking under the gate electrode.

In the first method for fabricating a semiconductor device, in the impurity diffusion layer forming step, after the impurity ion implantation step, the semiconductor substrate is heated to a temperature of about 1000 to 1050 ° C. at a rate of about 100 ° C./sec. After the heat treatment, it is preferable to have a heat treatment step of keeping the temperature for about 10 seconds.

According to a second method of manufacturing a semiconductor device according to the present invention, there is provided a gate electrode forming step of selectively forming a gate electrode on a first conductivity type semiconductor substrate via a gate insulating film; An oxide film deposition process of depositing an oxide film over the entire surface, a sidewall formation process of forming sidewalls on both side surfaces of the gate electrode, and a second process using a gate electrode and sidewalls as a mask with respect to the semiconductor substrate. A first impurity diffusion layer forming step of forming a first impurity diffusion layer of a second conductivity type by ion-implanting a conductivity type impurity, and removing the side wall; Ion implantation of impurities of the second conductivity type using the mask as a mask to form a second impurity diffusion layer of the second conductivity type in a region shallower than the first impurity diffusion layer. And a goldenrod forming step.

According to the second method for fabricating a semiconductor device, the side wall is removed to expose the oxide film below the side wall, and thereafter, ion implantation of impurities for forming the second impurity diffusion layer is performed. Is performed, the depth at which the impurity is implanted below the oxide film in the semiconductor substrate can be reduced, and the sneak of the impurity under the gate electrode can be suppressed.

According to the second method for manufacturing a semiconductor device, since the second impurity diffusion layer is formed after the formation of the sidewall, the impurity in the second impurity diffusion layer is formed by a low-temperature heat treatment for forming the sidewall. Can be prevented from occurring.

In the second method for manufacturing a semiconductor device, at least one of the first impurity diffusion layer forming step and the second impurity diffusion layer forming step includes the step of: It is preferable to have a heat treatment step of heating to a temperature of about 1000 to 1050 ° C. at a temperature increasing rate of about 100 ° C./sec and holding the temperature for about 10 seconds.

In the second method for fabricating a semiconductor device, the second impurity diffusion layer forming step preferably includes a step of ion-implanting impurities at a high dose.

In the second method of manufacturing a semiconductor device, after the second impurity diffusion layer forming step, an oxide film removing step of removing an oxide film exposed on the semiconductor substrate, and sidewalls on both side surfaces of the gate electrode are provided. And forming a metal film over the entire surface of the semiconductor substrate, and then reacting the metal film with the semiconductor substrate by heat treatment to form a surface portion of the source / drain region of the semiconductor substrate. And a silicidation step of forming a silicide film in a self-aligned manner.

In the second method of manufacturing a semiconductor device, between the first impurity diffusion layer forming step and the second impurity diffusion layer forming step, an oxide film exposed on the semiconductor substrate is removed. After depositing a metal film over the entire surface of the semiconductor substrate, the metal film and the semiconductor substrate are reacted by heat treatment, and a silicide film is self-aligned on the surface of the source / drain region of the semiconductor substrate. It is preferable that the method further includes a silicidation step of forming.

The metal film deposited in the silicidation step of the second method for manufacturing a semiconductor device is preferably a titanium film or a cobalt film.

The metal film deposited in the silicidation step of the second method for manufacturing a semiconductor device is preferably a laminated film of a titanium film and a cobalt film or an alloy film of titanium and cobalt.

[0035]

(First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1 and 2A and 2B.

FIG. 1 shows a sectional structure of the semiconductor device according to the first embodiment.

As shown in FIG. 1, a P-type semiconductor substrate 10
A gate electrode 102 made of, for example, a polymetal film or a polysilicon film is formed on the main surface of
Are selectively formed. N-type first impurity diffusion layer 10 is formed in the source / drain region of semiconductor substrate 100.
3 is formed, and a second N-type shallower than the first impurity diffusion layer 103 is formed in a region of the semiconductor substrate 100 closer to the channel region than the first impurity diffusion layer 103.
Impurity diffusion layer 104 is formed.

FIG. 2A shows the substrate depth direction (the AA direction in FIG. 1) in the second impurity diffusion layer 104 shown in FIG.
FIG. 2B shows the impurity concentration distribution of the second impurity diffusion layer 104 in the direction of the main surface of the substrate (B-B in FIG. 1).
(B direction). FIG.
In (a) and (b), the vertical axis showing the impurity concentration represents the logarithm log C _A of the impurity concentration C _A.

As shown in FIGS. 2A and 2B, the second
The feature of the impurity concentration distribution of the impurity diffusion layer 104 is that the impurity concentration is higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction.
Of the impurity concentration in the junction region with the semiconductor substrate 100 at a steep slope, specifically, 10 ⁶ (atom / cm ³ )
/ Μm or more, and the inactive region is smaller and the impurity activation rate is higher than the activated region. Here, the predetermined activation concentration refers to the activation concentration that the impurity diffusion layer should have in order for the semiconductor device to exhibit the designed performance.

According to the first embodiment, the impurity concentration of the second impurity diffusion layer 104 is set higher than the predetermined activation concentration in the substrate depth direction and the substrate main surface direction. Substrate 1 in impurity diffusion layer 104 of FIG.
Since the junction region with the second impurity diffusion layer has a steep impurity concentration gradient, the depth of the second impurity diffusion layer 104 is reduced while suppressing an increase in the parasitic resistance of the second impurity diffusion layer 104. Can be.

Although the P-type semiconductor substrate 100 is used in the first embodiment, an equivalent effect can be obtained by using an N-type semiconductor substrate instead.

(Second Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIG.

FIGS. 3A to 3C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 4 is a sectional view showing the semiconductor device according to the second embodiment. FIG. 7 is a diagram showing a temperature change in an impurity activation heat treatment used in the manufacturing method.

First, as shown in FIG. 3A, a gate oxide film 201 having a thickness of, for example, about 5 nm and a polycrystalline silicon film, for example, are formed on a P-type semiconductor substrate 200. A gate electrode 202 having a thickness is sequentially formed, and then an oxide film 203 having a thickness of, for example, about 10 nm is formed on the entire surface of the semiconductor substrate 200.

Next, as shown in FIG. 3B, the semiconductor substrate 200 is
After implanting impurities of the type, for example, As ions at an implantation energy of 10 KeV and a dose of 3 × 10 ¹⁴ cm ⁻² , the semiconductor substrate 200 is, for example, about 100 ° C. /
The substrate is heated to a temperature of about 1025 ° C. at a rate of temperature increase of sec, and then the n-type first impurity diffusion layer 204 is formed by a heat treatment held at the temperature for about 10 seconds.

Next, after depositing a silicon nitride film having a thickness of, for example, about 50 nm over the entire surface of the semiconductor substrate 200, the silicon nitride film is subjected to strong anisotropic etching in the vertical direction. , As shown in FIG.
Sidewalls 205 are formed on both side surfaces of the gate electrode 202. At this time, the oxide film 203 exposed on the surface of the gate electrode 202 and the surface of the source / drain regions is removed by etching. Next, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 200 using the gate electrode 202 and the sidewall 205 as a mask at an implantation energy of 30 KeV and a dose of 3 × 10 ¹⁵ cm ^−2. For example, as shown in FIG. 4, the substrate 200 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, and thereafter, the first impurity diffusion layer 204 is heat-treated at the temperature for about 10 seconds. N in deeper area
A second impurity diffusion layer 206 is formed.

According to the second embodiment, the gate electrode 20
2 is formed, an oxide film 203 is formed over the entire surface of the semiconductor substrate 200, and thereafter, the depth at which impurities are implanted into the semiconductor substrate 200 is reduced to perform ion implantation into the semiconductor substrate 200. In addition, since the impurity can be prevented from sneaking into the lower side of the gate electrode 202, the depth of the first impurity diffusion layer 204 can be reduced while preventing a decrease in channel length.

According to the second embodiment, the heat treatment rate for activating the ion-implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. Therefore, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 204 can be prevented.
Alternatively, the impurity concentration of the second impurity diffusion layer 206 can be set higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the first impurity diffusion layer 204 or The junction region between the second impurity diffusion layer 206 and the semiconductor substrate 200 can have a steep impurity concentration gradient, specifically, a gradient of 10 ⁶ (atom / cm ³ ) / μm or more. As a result, the first impurity diffusion layer 204 or the second impurity diffusion layer 206
Impurity diffusion layer 20 while suppressing an increase in parasitic resistance of
The depth of the fourth or second impurity diffusion layer 206 can be reduced.

In the second embodiment, a polycrystalline silicon film is used to form the gate electrode 202.
Instead, a polymetal film may be used.

Although the P-type semiconductor substrate 200 is used in the second embodiment, an equivalent effect can be obtained by using an N-type semiconductor substrate instead.

(Third Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (d).

FIGS. 5A to 5D are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to the third embodiment.

First, as shown in FIG. 5A, a gate oxide film 301 having a thickness of, for example, about 5 nm and a polysilicon film, for example, having a thickness of about 5 nm, are formed on a P-type semiconductor substrate 300. A gate electrode 302 having a thickness is sequentially formed, and thereafter, an oxide film 303 having a thickness of, for example, about 10 nm is formed over the entire surface of the semiconductor substrate 300.

Next, after a silicon nitride film having a thickness of, for example, about 50 nm is deposited over the entire surface of the semiconductor substrate 300, strong anisotropic etching is performed on the silicon nitride film in the vertical direction. , As shown in FIG.
Sidewalls 304 are formed on both side surfaces of the gate electrode 302. At this time, the oxide film 303 exposed on the surface of the gate electrode 302 and the surface of the source / drain regions is removed by etching.

Next, as shown in FIG. 5C, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 300 with an implantation energy of 30 KeV and 3 × 10 3 using the gate electrode 302 and the sidewall 304 as a mask. ¹⁵ cm ^-2
After the implantation at a dose of
The substrate is heated to a temperature of about 1025 ° C. at a rate of temperature rise of about 10 ° C./sec, and thereafter, an N-type first impurity diffusion layer 305 is formed by a heat treatment held at the temperature for about 10 seconds.

Next, as shown in FIG. 5D, the side wall 3 is etched using an etching solution such as hydrofluoric acid and hot phosphoric acid.
After removing 04, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 300 using the gate electrode 302 as a mask at an implantation energy of 10 KeV and 3 × 10 ¹⁴ cm.
Inject at a dose of ^-2 . Next, the semiconductor substrate 300 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, and thereafter, is heat-treated at the temperature for about 10 seconds to be shallower than the first impurity diffusion layer 305. N in area
A second impurity diffusion layer 306 of a mold is formed.

According to the third embodiment, the oxide film 303 under the sidewall 304 is exposed by removing the sidewall 304, and then the semiconductor substrate 300 is formed to form the second impurity diffusion layer 306. Since ion implantation is performed on the semiconductor substrate 300, the depth of the impurity implanted below the oxide film 303 in the semiconductor substrate 300 can be reduced, and the impurity can be prevented from flowing under the gate electrode 302. The depth of the second impurity diffusion layer 306 can be reduced while preventing a decrease in length.

According to the third embodiment, since the second impurity diffusion layer 306 is formed after the formation of the side wall 304, the second impurity diffusion layer 306 is formed by a low-temperature heat treatment for forming the side wall 304. Since the accelerated diffusion of the impurity can be prevented, the depth of the second impurity diffusion layer 306 can be kept shallow at the depth at which the impurity is implanted by ion implantation.

Further, according to the third embodiment, the heat treatment rate for activating the ion-implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. Therefore, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 305 can be formed.
Alternatively, the impurity concentration of the second impurity diffusion layer 306 can be higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the first impurity diffusion layer 305 or The junction region between the second impurity diffusion layer 306 and the semiconductor substrate 300 can have a steep impurity concentration gradient, specifically, a gradient of 10 ⁶ (atom / cm ³ ) / μm or more. As a result, the first impurity diffusion layer 305 or the second impurity diffusion layer 306
Impurity diffusion layer 30 while suppressing an increase in parasitic resistance of
The depth of the fifth or second impurity diffusion layer 306 can be reduced.

In the third embodiment, a polycrystalline silicon film is used to form the gate electrode 302.
Instead, a polymetal film may be used.

In the third embodiment, the heat treatment for activating the ion-implanted impurities is performed twice when forming the first impurity diffusion layer 305 and when forming the second impurity diffusion layer 306. Alternatively, it may be performed only once when forming the second impurity diffusion layer 306.

Although the P-type semiconductor substrate 300 is used in the third embodiment, an equivalent effect can be obtained by using an N-type semiconductor substrate instead.

(Fourth Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 7 (a) to (c).

FIGS. 6A to 6C and FIGS.
6C is a cross-sectional view illustrating each step of the method for manufacturing a semiconductor device according to the fourth embodiment, and each step of the manufacturing method illustrated in FIGS. 6A to 6C and FIG. , FIG.
This is the same as each step of the method for manufacturing the semiconductor device according to the third embodiment shown in FIG.

First, as shown in FIG. 6A, a gate oxide film 401 having a thickness of, for example, about 5 nm and a polysilicon film, for example, having a thickness of about 5 nm are formed on a P-type semiconductor substrate 400. A gate electrode 402 having a thickness is sequentially formed, and an oxide film 403 having a thickness of, for example, about 10 nm is formed over the entire surface of the semiconductor substrate 400.

Next, after depositing a silicon nitride film having a thickness of, for example, about 50 nm over the entire surface of the semiconductor substrate 400, the silicon nitride film is subjected to strong anisotropic etching in the vertical direction. As shown in FIG.
The first sidewall 40 is provided on both side surfaces of the gate electrode 402.
4 is formed. At this time, the oxide film 403 exposed on the surface of the gate electrode 402 and the surfaces of the source / drain regions is removed by etching.

Next, as shown in FIG. 6C, an N-type impurity such as A is added to the semiconductor substrate 400 using the gate electrode 402 and the first sidewall 404 as a mask.
The implantation energy of s ions is 30 KeV and 3 × 10 ¹⁵
After the implantation at a dose of cm ⁻² , the semiconductor substrate 400 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, and then N-type is heat-treated at a temperature of about 1025 ° C. A first impurity diffusion layer 405 is formed.

Next, as shown in FIG. 7A, after removing the first side wall 404 using an etching solution such as hydrofluoric acid and hot phosphoric acid, the semiconductor substrate 400 is formed using the gate electrode 402 as a mask. On the other hand, an N-type impurity such as As ions is implanted at an implantation energy of 10 KeV and 3 × 10
^{Implant at} a dose of ¹⁴ cm ^-2 . Next, the semiconductor substrate 40
0 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, and then is heat-treated at the temperature for about 10 seconds to form an N-type region in a region shallower than the first impurity diffusion layer 405. A second impurity diffusion layer 406 is formed.

Next, after depositing a silicon nitride film having a thickness of, for example, about 50 nm over the entire surface of the semiconductor substrate 400, the silicon nitride film is subjected to strong anisotropic etching in the vertical direction. , As shown in FIG.
The second sidewall 40 is provided on both side surfaces of the gate electrode 402.
7 is formed.

Next, after a titanium film having a thickness of about 30 nm is deposited over the entire surface of the semiconductor substrate 400 by, for example, a sputtering method, the titanium film is deposited at a temperature of about 680 ° C. for about 1 hour.
A 0 second heat treatment is performed. Next, the second sidewall 4
After selectively removing the unreacted titanium film present on the substrate 07 using an etching solution such as sulfuric acid and hydrogen peroxide, about 9
By performing a heat treatment at a temperature of 00 ° C. for about 10 seconds, FIG.
As shown in (c), a silicide film 408 having a thickness of about 50 nm is formed in a self-alignment manner on the surface of the gate electrode 402 and the source / drain regions.

According to the fourth embodiment, the oxide film 403 under the first sidewall 404 is exposed by removing the first sidewall 404, and then the second impurity diffusion layer 406 is formed. Semiconductor substrate 40
0, the semiconductor substrate 400
The depth at which impurities are implanted below oxide film 403 can be reduced, and impurity gate electrode 40 can be formed.
2 can be suppressed from going down, so that the depth of the second impurity diffusion layer 406 can be reduced while preventing a decrease in channel length.

According to the fourth embodiment, the second impurity diffusion layer 40 is formed after the first side wall 404 is formed.
6, the impurity can be prevented from being accelerated and diffused by the low-temperature heat treatment for forming the first sidewall 404, and thus the second impurity diffusion layer 40 can be formed.
6 can be kept shallow at the depth at which the impurities are implanted by ion implantation.

According to the fourth embodiment, the heat treatment rate for activating the ion-implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. Therefore, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 405 can be formed.
Alternatively, the impurity concentration of the second impurity diffusion layer 406 can be higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the first impurity diffusion layer 405 or The junction region between the second impurity diffusion layer 406 and the semiconductor substrate 400 can have a steep impurity concentration gradient, specifically, a gradient of 10 ⁶ (atom / cm ³ ) / μm or more. As a result, the first impurity diffusion layer 405 or the second impurity diffusion layer 406
Impurity diffusion layer 40 while suppressing an increase in parasitic resistance of
The depth of the fifth or second impurity diffusion layer 406 can be reduced.

According to the fourth embodiment, since the silicide film 408 is formed on each surface of the gate electrode 402 and the source / drain region, the resistance of the gate electrode 402 and the source / drain region can be reduced. it can.

In the fourth embodiment, a polycrystalline silicon film is used to form the gate electrode 402.
Instead, a polymetal film may be used.

In the fourth embodiment, the heat treatment for activating the ion-implanted impurities is performed twice when forming the first impurity diffusion layer 405 and when forming the second impurity diffusion layer 406. Alternatively, it may be performed only once when forming the second impurity diffusion layer 406.

In the fourth embodiment, a titanium film is used for forming the silicide film 408, but a cobalt film may be used instead.

Although the P-type semiconductor substrate 400 is used in the fourth embodiment, an equivalent effect can be obtained by using an N-type semiconductor substrate instead.

(Fifth Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 9 (a) and 9 (b).

FIGS. 8 (a) to 8 (c) and 9 (a),
8B is a cross-sectional view illustrating each step of the method for manufacturing a semiconductor device according to the fifth embodiment, and each step of the manufacturing method illustrated in FIGS. 8A to 8C is illustrated in FIG. The third shown in (c)
This is the same as each step of the method for manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 8A, on a P-type semiconductor substrate 500, a gate oxide film 501 having a thickness of, for example, about 5 nm, and a polycrystalline silicon film, for example, are formed. A gate electrode 502 having a thickness is sequentially formed, and then an oxide film 503 having a thickness of, for example, about 10 nm is formed over the entire surface of the semiconductor substrate 500.

Next, after a silicon nitride film having a thickness of, for example, about 50 nm is deposited over the entire surface of the semiconductor substrate 500, strong anisotropic etching is performed on the silicon nitride film in the vertical direction. As shown in FIG.
Side walls 504 are formed on both side surfaces of the gate electrode 502. At this time, the oxide film 503 exposed on the surface of the gate electrode 502 and the surface of the source / drain regions is removed by etching.

Next, as shown in FIG. 8C, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 500 at an implantation energy of 30 KeV and a dose of 3 × 10 5 using the gate electrode 502 and the sidewall 504 as a mask. ¹⁵ cm ^-2
After the implantation at a dose of
The substrate is heated to a temperature of about 1025 ° C. at a rate of temperature rise of about 10 ° C./sec, and thereafter, an N-type first impurity diffusion layer 505 is formed by a heat treatment held at the temperature for about 10 seconds.

Next, the oxide film 503 exposed on the surface of the gate electrode 502 and the surface of the first impurity diffusion layer 505 is completely removed by anisotropic etching.
A titanium film having a thickness of about 30 nm is deposited over the entire surface of the metal layer 00 by, for example, a sputtering method.
A heat treatment is performed at a temperature of about 680 ° C. for about 10 seconds. Next, after the unreacted titanium film present on the sidewall 504 is selectively removed using an etching solution such as aqueous sulfuric acid and hydrogen peroxide, a heat treatment is performed at a temperature of about 900 ° C. for about 10 seconds. Then, as shown in FIG.
02 and the surface of the first impurity diffusion layer 505
A silicide film 506 having a thickness of m is formed in a self-aligned manner.

Next, as shown in FIG. 9B, the side walls 5 are etched using an etching solution such as hydrofluoric acid and hot phosphoric acid.
After removing 04, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 500 using the gate electrode 502 as a mask at an implantation energy of 10 KeV and 3 × 10 ¹⁴ cm.
Inject at a dose of ^-2 . Next, after the semiconductor substrate 500 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, a region shallower than the first impurity diffusion layer 505 is formed by a heat treatment held at the temperature for about 10 seconds. Then, an N-type second impurity diffusion layer 507 is formed.

According to the fifth embodiment, the side wall 504 is removed to expose the oxide film 503 under the side wall 504, and then the semiconductor substrate 500 is formed to form the second impurity diffusion layer 507. On the other hand, since the ion implantation is performed, the depth of the impurity implanted below the oxide film 503 in the semiconductor substrate 500 can be reduced, and the impurity can be prevented from flowing under the gate electrode 502. The depth of the second impurity diffusion layer 507 can be reduced while preventing a decrease in length.

According to the fifth embodiment, the second impurity diffusion layer 507 is formed after the formation of the side wall 504 or the silicide film 506.
04 or the low-temperature heat treatment for forming the silicide film 506 can prevent the accelerated diffusion of impurities from occurring, so that the depth of the second impurity diffusion layer 507 is set to the depth at which the impurities are implanted by ion implantation. It can be kept shallow.

According to the fifth embodiment, the heat treatment rate for activating the ion-implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. Therefore, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 505 can be prevented.
Alternatively, the impurity concentration of the second impurity diffusion layer 507 can be set to have a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the first impurity diffusion layer 5
05 or the second impurity diffusion layer 507 in the junction region with the semiconductor substrate 500 may have a steep impurity concentration gradient, specifically, a gradient of 10 ⁶ (atom / cm ³ ) / μm or more. it can. As a result, it is possible to reduce the depth of the first impurity diffusion layer 505 or the second impurity diffusion layer 507 while suppressing an increase in the parasitic resistance of the first impurity diffusion layer 505 or the second impurity diffusion layer 507. it can.

According to the fifth embodiment, since the silicide film 506 is formed on each surface of the gate electrode 502 and the source / drain region, the resistance of the gate electrode 502 and the source / drain region can be reduced. it can.

In the fifth embodiment, after As ions are implanted to form the second impurity diffusion layer 507, B ions are implanted at an energy of 30 KeV and a dose of 1 × 10 ¹³ cm ⁻² . It may be injected in an amount. In this way, a pocket region for suppressing the short channel effect can be easily formed below the second impurity diffusion layer 507 in a self-aligned manner.

In the fifth embodiment, a polycrystalline silicon film is used to form the gate electrode 502, but a polymetal film may be used instead.

In the fifth embodiment, the heat treatment for activating the ion-implanted impurities is performed twice when forming the first impurity diffusion layer 505 and when forming the second impurity diffusion layer 507. Alternatively, it may be performed only once when the second impurity diffusion layer 507 is formed.

In the fifth embodiment, a titanium film is used for forming the silicide film 506, but a cobalt film may be used instead.

Although the P-type semiconductor substrate 500 is used in the fifth embodiment, an equivalent effect can be obtained by using an N-type semiconductor substrate instead.

(Sixth Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 11 (a) to (c).

FIGS. 10 (a) to 10 (c) and FIGS.
10C is a cross-sectional view illustrating each step of the manufacturing method of the semiconductor device according to the sixth embodiment, and each step of the manufacturing method illustrated in FIGS. 10A to 10C is illustrated in FIG. This is the same as each step of the method for manufacturing the semiconductor device according to the third embodiment shown in FIGS.

First, as shown in FIG. 10A, a gate oxide film 601 having a thickness of, for example, about 5 nm and a polysilicon film, for example, having a thickness of about 5 nm are formed on a P-type semiconductor substrate 600. Gate electrode 602 having thickness
Are sequentially formed, and thereafter, an oxide film 603 having a thickness of, for example, about 10 nm is formed over the entire surface of the semiconductor substrate 600.
To form

Next, after depositing a silicon nitride film having a thickness of, for example, about 50 nm over the entire surface of the semiconductor substrate 600, the silicon nitride film is subjected to strong anisotropic etching in the vertical direction. As shown in FIG. 10B, sidewalls 604 are formed on both side surfaces of the gate electrode 602.
To form At this time, the oxide film 603 exposed on the surface of the gate electrode 602 and the surfaces of the source / drain regions is removed by etching.

Next, as shown in FIG. 10C, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 600 using the gate electrode 602 and the side wall 604 as a mask at an implantation energy of 30 KeV and 3 × 10 3. ¹⁵ cm
After the implantation at a dose of ^-2 , the semiconductor substrate 600 is
The substrate is heated to a temperature of about 1025 ° C. at a temperature increase rate of 0 ° C./sec, and thereafter, an N-type first impurity diffusion layer 605 is formed by a heat treatment held at the temperature for about 10 seconds.

Next, after completely removing the oxide film 603 exposed on the surface of the gate electrode 602 and the surface of the first impurity diffusion layer 605 by anisotropic etching, FIG.
As shown in FIG. 7, a laminated film 606 of a titanium film and a cobalt film having a thickness of about 30 nm is deposited over the entire surface of the semiconductor substrate 600 by, for example, a sputtering method.

Next, after performing a heat treatment at a temperature of about 680 ° C. for about 10 seconds, the unreacted laminated film 606 present on the side wall 604 is etched using an etching solution such as sulfuric acid and hydrogen peroxide. Then, a heat treatment is performed at a temperature of about 900 ° C. for about 10 seconds, so that the surface of the gate electrode 602 and the first impurity diffusion layer 605 is formed as shown in FIG. A silicide film 607 having a thickness of 50 nm is formed in a self-aligned manner.

Next, as shown in FIG. 11C, after removing the sidewalls 604 using an etching solution such as hydrofluoric acid and hot phosphoric acid, the semiconductor substrate 600 is removed from the semiconductor substrate 600 using the gate electrode 602 as a mask. N-type impurities, for example, As
The ions are implanted at an energy of 10 KeV and 3 × 10 ¹⁴ c
^{Implant at} a dose of m- ² . Next, the semiconductor substrate 600 is heated to a temperature of about 1025 ° C. at a rate of about 100 ° C./sec, and then is heat-treated at the temperature for about 10 seconds to form a region shallower than the first impurity diffusion layer 605. Then, an N-type second impurity diffusion layer 608 is formed.

According to the sixth embodiment, the oxide film 603 under the sidewall 604 is exposed by removing the sidewall 604, and then the semiconductor substrate 600 is formed to form the second impurity diffusion layer 608. On the other hand, since the ion implantation is performed, the depth of the impurity implanted below the oxide film 603 in the semiconductor substrate 600 can be reduced, and the sneak of the impurity under the gate electrode 602 can be suppressed. The depth of the second impurity diffusion layer 608 can be reduced while preventing a decrease in length.

According to the sixth embodiment, the second impurity diffusion layer 608 is formed after the formation of the side wall 604 or the silicide film 607.
04 or the low-temperature heat treatment for forming the silicide film 607 can be prevented from causing accelerated diffusion of impurities. Therefore, the depth of the second impurity diffusion layer 608 is set to the depth at which the impurities are implanted by ion implantation. It can be kept shallow.

According to the sixth embodiment, the heat treatment rate for activating the ion-implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. For this reason, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 605 can be formed.
Alternatively, the impurity concentration of the second impurity diffusion layer 608 can be higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the first impurity diffusion layer 605 or the second The junction region between the second impurity diffusion layer 608 and the semiconductor substrate 600 can have a steep impurity concentration gradient, specifically, a gradient of 10 ⁶ (atom / cm ³ ) / μm or more. As a result, the first impurity diffusion layer 605 or the second impurity diffusion layer 608
Impurity diffusion layer 60 while suppressing an increase in parasitic resistance of
The depth of the fifth or second impurity diffusion layer 608 can be reduced.

According to the sixth embodiment, since the silicide film 607 is formed on each surface of the gate electrode 602 and the source / drain region, the resistance of the gate electrode 602 and the source / drain region can be reduced. it can.
Further, since the heat resistance of the silicide film 607 is improved by using a stacked film of a titanium film and a cobalt film for forming the silicide film 607, the heat treatment for activation heat for forming the second impurity diffusion layer 608 to be performed later is performed. The reliability of the silicide film 607 is improved.

In the sixth embodiment, after As ions for forming the second impurity diffusion layer 608 are implanted, B ions are implanted at an energy of 30 KeV and a dose of 1 × 10 ¹³ cm ⁻² . It may be injected in an amount. In this manner, a pocket region for suppressing the short channel effect can be easily formed below the second impurity diffusion layer 608 in a self-aligned manner.

In the sixth embodiment, a polycrystalline silicon film is used to form the gate electrode 602, but a polymetal film may be used instead.

In the sixth embodiment, the heat treatment for activating the ion-implanted impurities is performed twice when forming the first impurity diffusion layer 605 and when forming the second impurity diffusion layer 608. Alternatively, it may be performed only once when forming the second impurity diffusion layer 608.

In the sixth embodiment, the formation of the silicide film 607 is performed by using the laminated film 6 of the titanium film and the cobalt film.
Although 06 was used, an alloy film of titanium and cobalt may be used instead.

Although the P-type semiconductor substrate 600 is used in the sixth embodiment, the same effect can be obtained by using an N-type semiconductor substrate instead.

(Seventh Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 13 (a) to (c).

FIGS. 12 (a) to 12 (c) and FIGS.
12C is a cross-sectional view illustrating each step of the manufacturing method of the semiconductor device according to the seventh embodiment, and is a manufacturing method illustrated in FIGS. 12A to 12C and FIGS. 13A and 13B. Are the same as the respective steps of the method for manufacturing the semiconductor device according to the sixth embodiment shown in FIGS. 10A to 10C and FIGS. 11A and 11B.

First, as shown in FIG. 12A, a gate oxide film 701 having a thickness of, for example, about 5 nm, and a polycrystalline silicon film, for example, are formed on a P-type semiconductor substrate 700 to a thickness of about 250 nm. Gate electrode 702 having thickness
Are sequentially formed, and then over the entire surface of the semiconductor substrate 700, an oxide film 703 having a thickness of, for example, about 10 nm.
To form

Next, a silicon nitride film having a thickness of, for example, about 50 nm is deposited over the entire surface of the semiconductor substrate 700, and then the silicon nitride film is subjected to strong anisotropic etching in the vertical direction. As shown in FIG. 12B, sidewalls 704 are provided on both side surfaces of the gate electrode 702.
To form At this time, the oxide film 703 exposed on the surface of the gate electrode 702 and the surface of the source / drain regions is removed by etching.

Next, as shown in FIG. 12C, an N-type impurity, for example, As ion is implanted into the semiconductor substrate 700 using the gate electrode 702 and the sidewall 704 as a mask at an implantation energy of 30 KeV and 3 × 10 3. ¹⁵ cm
After the implantation at a dose of ^-2 , the semiconductor substrate 700 is
The substrate is heated to a temperature of about 1025 ° C. at a temperature increase rate of 0 ° C./sec, and thereafter, an N-type first impurity diffusion layer 705 is formed by a heat treatment held at the temperature for about 10 seconds.

Next, after completely removing the oxide film 703 exposed on the surface of the gate electrode 702 and the surface of the first impurity diffusion layer 705 by anisotropic etching, FIG.
As shown in (1), a laminated film 706 of a titanium film and a cobalt film having a thickness of about 30 nm is deposited over the entire surface of the semiconductor substrate 700 by, for example, a sputtering method.

Next, after performing a heat treatment at a temperature of about 680 ° C. for about 10 seconds, the unreacted laminated film 706 existing on the side wall 704 is etched using an etching solution such as sulfuric acid and hydrogen peroxide. Then, a heat treatment is performed at a temperature of about 900 ° C. for about 10 seconds, so that a surface of the gate electrode 702 and the first impurity diffusion layer 705 is formed as shown in FIG. A silicide film 707 having a thickness of 50 nm is formed in a self-aligned manner.

Next, as shown in FIG. 13C, after removing the side wall 704 using an etching solution such as hydrofluoric acid and hot phosphoric acid, the semiconductor substrate 700 is removed from the semiconductor substrate 700 using the gate electrode 702 as a mask. N-type impurities, for example, As
The ions are implanted with 10 KeV implantation energy and 5 × 10 ¹⁵ c
By implanting at a high dose of m ^−2, an N-type second impurity diffusion layer 708 is formed in a region shallower than the first impurity diffusion layer 705.

According to the seventh embodiment, the oxide film 703 under the side wall 704 is exposed by removing the side wall 704, and then the semiconductor substrate 700 is formed to form the second impurity diffusion layer 708. On the other hand, since the ion implantation is performed, the depth of the impurity implanted below the oxide film 703 in the semiconductor substrate 700 can be reduced, and the sneak of the impurity under the gate electrode 702 can be suppressed. The depth of the second impurity diffusion layer 708 can be reduced while preventing a decrease in length.

According to the seventh embodiment, the second impurity diffusion layer 708 is formed after the formation of the side wall 704 or the silicide film 707.
04 or the low-temperature heat treatment for forming the silicide film 707 can be prevented from causing accelerated diffusion of impurities. Therefore, the depth of the second impurity diffusion layer 708 is set to the depth at which the impurities are implanted by ion implantation. It can be kept shallow.

Further, according to the seventh embodiment, the heat treatment rate for activating the implanted impurities is set to a high rate of about 100 ° C./sec. It is possible to suppress the accelerated diffusion by accelerating the recovery and to perform the heat treatment for activating the ion-implanted impurities at a high temperature of 1000 ° C. or higher, so that the solid solution limit of the impurities is increased to suppress the clustering. Can be. Therefore, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the first impurity diffusion layer 705 is formed.
Can be made higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the junction region between the first impurity diffusion layer 705 and the semiconductor substrate 700 is reduced. A steep impurity concentration gradient, specifically, a gradient of 10 ⁶ atom / cm ³ μm or more can be provided. As a result, the depth of the first impurity diffusion layer 705 can be reduced while suppressing an increase in the parasitic resistance of the first impurity diffusion layer 705.

According to the seventh embodiment, since the silicide film 707 is formed on each surface of the gate electrode 702 and the source / drain regions, the resistance of the gate electrode 702 and the source / drain regions can be reduced. In addition, since the stacked film of the titanium film and the cobalt film is used for forming the silicide film 707, the heat resistance of the silicide film 707 is improved.

Further, according to the seventh embodiment, since the ion implantation of the impurity for forming the second impurity diffusion layer 708 is performed at a high dose, the second impurity is implanted without performing the heat treatment for activating the impurity. Since the activation concentration of the impurity in the diffusion layer 708 can be increased, the depth of the second impurity diffusion layer 708 can be reduced while suppressing an increase in the parasitic resistance of the second impurity diffusion layer 708. The process can be simplified. Further, since high-temperature activation heat treatment can be prevented from being applied to the silicide film 707, the reliability of the silicide film 707 is improved.

In the seventh embodiment, after As ions are implanted to form the second impurity diffusion layer 708, B ions are implanted at an energy of 30 KeV and a dose of 1 × 10 ¹³ cm ⁻² . It may be injected in an amount. In this way, a pocket region for suppressing the short channel effect can be easily formed below the second impurity diffusion layer 708 in a self-aligned manner.

In the seventh embodiment, a polycrystalline silicon film is used to form the gate electrode 702, but a polymetal film may be used instead.

In the seventh embodiment, the formation of the silicide film 707 is performed by using a laminated film 7 of a titanium film and a cobalt film.
Although 06 was used, an alloy film of titanium and cobalt or a titanium film deposited after sputtering of argon / titanium may be used instead.

Although the silicide film 707 is formed in the seventh embodiment, a polycide film may be formed instead.

Although the P-type semiconductor substrate 700 is used in the seventh embodiment, the same effect can be obtained by using an N-type semiconductor substrate instead.

[0130]

According to the semiconductor device of the present invention, the second
The activation concentration of the impurity diffusion layer is set to be higher than a predetermined activation concentration in the substrate depth direction and the substrate main surface direction, and the junction region between the second impurity diffusion layer and the semiconductor substrate is formed. Because of the steep impurity concentration gradient, the depth of the second impurity diffusion layer can be reduced while suppressing an increase in the parasitic resistance of the second impurity diffusion layer.

According to the first method of manufacturing a semiconductor device of the present invention, after forming a gate electrode, an oxide film is deposited over the entire surface of a semiconductor substrate, and then an impurity film for forming an impurity diffusion layer is formed. Since the ion implantation is performed, the depth at which the impurity is implanted can be reduced, and the impurity can be prevented from sneaking under the gate electrode. Therefore, the depth of the impurity diffusion layer can be reduced while preventing a decrease in channel length. can do.

In the first method for fabricating a semiconductor device, the impurity diffusion layer forming step comprises heating the semiconductor substrate to a temperature of about 1000 to 1050 ° C. at a rate of about 100 ° C./sec after the impurity ion implantation step. After that, if there is a heat treatment step of maintaining the temperature for about 10 seconds, the rate of heat treatment for activating the ion-implanted impurities is a high rate of about 100 ° C./sec. Accelerated diffusion can be suppressed by accelerating the recovery of damage to the semiconductor substrate due to ion implantation, and the heat treatment for activating the ion-implanted impurities is performed at a high temperature of 1000 ° C. or more, so that the solid solubility limit of the impurities is reduced. To suppress clustering. Therefore, it is possible to prevent the impurity from moving to a deep position and to improve the activation rate of the impurity, so that the impurity concentration of the impurity diffusion layer can be increased to a predetermined level in the substrate depth direction and the substrate main surface direction. And the junction region between the impurity diffusion layer and the semiconductor substrate has a steep impurity concentration gradient, specifically 10 ⁶ (atom / cm 2).
³ ) It can have a gradient of / μm or more. As a result, the depth of the impurity diffusion layer can be reduced while suppressing an increase in the parasitic resistance of the impurity diffusion layer.

According to the second method of manufacturing a semiconductor device of the present invention, the oxide film under the sidewall is exposed by removing the sidewall, and then the impurity for forming the second impurity diffusion layer is removed. Ion implantation can reduce the depth at which impurities are implanted below the oxide film in the semiconductor substrate, and can also suppress the impurity from flowing under the gate electrode, thereby reducing the channel length. The depth of the second impurity diffusion layer can be reduced while preventing it.

According to the second method for manufacturing a semiconductor device, since the second impurity diffusion layer is formed after the formation of the sidewall, the impurity in the second impurity diffusion layer is formed by a low-temperature heat treatment for forming the sidewall. Can be prevented from occurring, and the depth of the second impurity diffusion layer can be kept shallow at the depth at which the impurities are implanted by ion implantation.

In the second method for manufacturing a semiconductor device, at least one of the first impurity diffusion layer forming step and the second impurity diffusion layer forming step includes the step of implanting the semiconductor substrate after the impurity ion implantation step. If a heat treatment step of heating to a temperature of about 1000 to 1050 ° C. at a rate of about 100 ° C./sec and maintaining the temperature at that temperature for about 10 seconds is included, it is necessary to activate the ion-implanted impurities. Since the temperature rise rate of the heat treatment is a high temperature rise rate of about 100 ° C./sec, the recovery of damage to the semiconductor substrate due to the ion implantation can be accelerated to suppress the accelerated diffusion and activate the ion implanted impurities. Heat treatment for 100
Since the treatment is performed at a high temperature of 0 ° C. or more, clustering can be suppressed by increasing the solid solution limit of impurities. For this reason, the impurity can be prevented from moving to a deep position and the activation rate of the impurity can be improved, so that the impurity concentration of the first impurity diffusion layer or the second impurity diffusion layer is increased in the substrate depth direction and in the substrate depth direction. The activation concentration can be higher than a predetermined activation concentration in the direction of the main surface of the substrate, and the junction region of the first impurity diffusion layer or the second impurity diffusion layer with the semiconductor substrate has a steep impurity concentration. Gradient, specifically 1
Since the first impurity diffusion layer can have a gradient of not less than 0 ⁶ (atom / cm ³ ) / μm, the first impurity diffusion can be performed while suppressing an increase in the parasitic resistance of the first impurity diffusion layer or the second impurity diffusion layer. The depth of the layer or the second impurity diffusion layer can be reduced.

In the second method for fabricating a semiconductor device, when the step of forming the second impurity diffusion layer includes the step of ion-implanting the impurity at a high dose, the second impurity diffusion layer can be formed without performing the impurity activation heat treatment. Since the activation concentration of the impurity in the diffusion layer can be increased, the depth of the second impurity diffusion layer can be reduced while suppressing an increase in the parasitic resistance of the second impurity diffusion layer, and the process can be simplified. Can be
It is possible to prevent a decrease in reliability due to heat treatment applied to other members.

The method for manufacturing a second semiconductor device may further include, after the second impurity diffusion layer forming step, a silicidation step of forming a silicide film on the surface of the source / drain region of the semiconductor substrate. The resistance of the source / drain regions can be reduced.

In the second method for manufacturing a semiconductor device, a silicide film is formed on the surface of the source / drain region of the semiconductor substrate between the first impurity diffusion layer forming step and the second impurity diffusion layer forming step. If the method further includes a silicidation step, the resistance of the source / drain regions can be reduced, and the low-temperature heat treatment for forming the silicide film is performed because the second impurity diffusion layer is formed after the silicide film is formed. This can prevent the accelerated diffusion of impurities from occurring, so that the depth of the second impurity diffusion layer can be kept shallow at the depth at which the impurities are implanted by ion implantation.

When the metal film deposited in the silicidation step of the second method for manufacturing a semiconductor device is a titanium film or a cobalt film, the silicide film is surely formed on the surface of the source / drain region of the semiconductor substrate. Can be.

If the metal film deposited in the silicidation step of the second semiconductor device manufacturing method is a laminated film of a titanium film and a cobalt film or an alloy film of titanium and cobalt, the source / drain region of the semiconductor substrate Since the heat resistance of the silicide film formed on the surface portion is improved, the reliability of the silicide film with respect to activation heat treatment for forming a second impurity diffusion layer to be performed later is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2A is a diagram illustrating an impurity concentration distribution in a substrate depth direction in an impurity diffusion layer of the semiconductor device according to the first embodiment, and FIG. 2B is a diagram illustrating an impurity concentration distribution of the semiconductor device according to the first embodiment; FIG. 4 is a diagram showing an impurity concentration distribution in a direction of a main surface of a substrate in an impurity diffusion layer.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIG. 4 is a diagram showing a temperature change in an impurity activation heat treatment used in a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 5A to 5D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIGS. 6A to 6C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 7A to 7C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 8A to 8C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 9A and 9B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a sixth embodiment.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a sixth embodiment.

FIGS. 12A to 12C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a seventh embodiment.

FIGS. 13A to 13C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a seventh embodiment.

FIGS. 14A to 14C are cross-sectional views illustrating respective steps of a conventional method for manufacturing a semiconductor device.

FIGS. 15A and 15B are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

FIG. 16 is a sectional view of a conventional semiconductor device.

FIG. 17A is a diagram showing an impurity concentration distribution in a substrate depth direction in an impurity diffusion layer of a conventional semiconductor device;
FIG. 3B is a diagram showing an impurity concentration distribution in a main surface direction of a substrate in an impurity diffusion layer of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor substrate 101 gate oxide film 102 gate electrode 103 first impurity diffused layer 104 second impurity diffused layer 200 semiconductor substrate 201 gate oxide film 202 gate electrode 203 oxide film 204 first impurity diffused layer 205 sidewall 206 second Impurity diffusion layer 300 semiconductor substrate 301 gate oxide film 302 gate electrode 303 oxide film 304 sidewall 305 first impurity diffusion layer 306 second impurity diffusion layer 400 semiconductor substrate 401 gate oxide film 402 gate electrode 403 oxide film 404 first Side wall 405 first impurity diffusion layer 406 second impurity diffusion layer 407 second side wall 408 silicide film 500 semiconductor substrate 501 gate oxide film 502 gate electrode 503 oxide film 504 side wall 5 5 First impurity diffusion layer 506 Silicide film 507 Second impurity diffusion layer 600 Semiconductor substrate 601 Gate oxide film 602 Gate electrode 603 Oxide film 604 Side wall 605 First impurity diffusion layer 606 Laminated film of titanium film and cobalt film 607 Silicide film 608 Second impurity diffusion layer 700 Semiconductor substrate 701 Gate oxide film 702 Gate electrode 703 Oxide film 704 Sidewall 705 First impurity diffusion layer 706 Stacked film of titanium film and cobalt film 707 Silicide film 708 Second impurity diffusion layer

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Shinji Odanaka 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5F040 DA01 DA02 DA13 EC07 EC13 EF02 EH02 EM01 FA07 FA10 FB02 FC11 FC21 FC22

Claims (10)

[Claims] 1. A gate electrode formed on a main surface of a semiconductor substrate of a first conductivity type via a gate insulating film, and a first electrode of a second conductivity type formed in a source / drain region of the semiconductor substrate. An impurity diffusion layer, and a second conductivity type second impurity diffusion layer formed in a region of the semiconductor substrate closer to the channel region than the first impurity diffusion layer and shallower than the first impurity diffusion layer. The activation concentration of the second impurity diffusion layer is set higher than a predetermined activation concentration in a substrate depth direction and a main surface direction of the substrate, and the activation concentration in the second impurity diffusion layer is A semiconductor device, wherein a junction region with a semiconductor substrate has a steep impurity concentration gradient. 2. A gate electrode forming step of selectively forming a gate electrode on a first conductivity type semiconductor substrate via a gate insulating film, and depositing an oxide film over the entire surface of the semiconductor substrate. An oxide film deposition step, and an impurity diffusion layer forming step of forming a second conductivity type impurity diffusion layer by ion-implanting a second conductivity type impurity into the semiconductor substrate using the gate electrode as a mask. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein the impurity diffusion layer forming step comprises:
3. The method for manufacturing a semiconductor device according to claim 2, further comprising a heat treatment step of heating to a temperature of about 1000 to 1050 [deg.] C. at a heating rate of sec and holding the temperature for about 10 seconds. . 4. A gate electrode forming step of selectively forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and depositing an oxide film over the entire surface of the semiconductor substrate. An oxide film depositing step; a side wall forming step of forming side walls on both side surfaces of the gate electrode; and ion implantation of a second conductivity type impurity into the semiconductor substrate using the gate electrode and the side wall as a mask. Thereby, a first impurity diffusion layer forming step of forming a first impurity diffusion layer of a second conductivity type, and after removing the sidewall, a second impurity diffusion layer is formed on the semiconductor substrate using the gate electrode as a mask. A second impurity diffusion layer for forming a second impurity diffusion layer of a second conductivity type in a region shallower than the first impurity diffusion layer by ion-implanting impurities of a conductivity type; The method of manufacturing a semiconductor device characterized by and a forming process. 5. The method according to claim 1, wherein at least one of the first impurity diffusion layer forming step and the second impurity diffusion layer forming step includes the step of: implanting the semiconductor substrate at about 100 ° C./sec after the impurity ion implantation step. About 1000 to 10 at heating rate
5. The method according to claim 4, further comprising a heat treatment step of heating to a temperature of 50 [deg.] C. and maintaining the temperature for about 10 seconds.
13. The method for manufacturing a semiconductor device according to item 5. 6. The method according to claim 4, wherein the step of forming the second impurity diffusion layer includes a step of ion-implanting impurities at a high dose. 7. An oxide film removing step of removing the oxide film exposed on the semiconductor substrate after the second impurity diffusion layer forming step; and forming sidewalls on both side surfaces of the gate electrode again. A sidewall reforming step, and after depositing a metal film over the entire surface of the semiconductor substrate, causing the metal film and the semiconductor substrate to react with each other by a heat treatment, thereby forming a surface portion of a source / drain region of the semiconductor substrate. 5. The method according to claim 4, further comprising a silicidation step of forming a silicide film in a self-aligned manner. 8. An oxide film removing step for removing the oxide film exposed on the semiconductor substrate, between the first impurity diffusion layer forming step and the second impurity diffusion layer forming step. After depositing a metal film over the entire surface of the semiconductor substrate, the metal film and the semiconductor substrate are reacted by heat treatment, and a silicide film is self-aligned on the surface of the source / drain region of the semiconductor substrate. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of forming a silicide. 9. The method according to claim 7, wherein the metal film deposited in the silicidation step is a titanium film or a cobalt film. 10. The semiconductor device according to claim 7, wherein the metal film deposited in the silicidation step is a laminated film of a titanium film and a cobalt film or an alloy film of titanium and cobalt. Manufacturing method.