JP2000509555A - 集積回路において小さな構造物を形成するための像反転技術 - Google Patents
集積回路において小さな構造物を形成するための像反転技術Info
- Publication number
- JP2000509555A JP2000509555A JP9538029A JP53802997A JP2000509555A JP 2000509555 A JP2000509555 A JP 2000509555A JP 9538029 A JP9538029 A JP 9538029A JP 53802997 A JP53802997 A JP 53802997A JP 2000509555 A JP2000509555 A JP 2000509555A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist
- rectile
- patterned
- shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 91
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 203
- 239000000463 material Substances 0.000 claims abstract description 137
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000000059 patterning Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 32
- 238000005498 polishing Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052582 BN Inorganic materials 0.000 claims description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 199
- 239000011229 interlayer Substances 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000005755 formation reaction Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.半導体基板(12)上に形成される材料の層(16)において各々が或るサ イズ、形状および位置を有する開口部(28)をパターニングするために、フォ トレジストの第1の層(18)から形成されるフォトレジストからなるパターニ ングされたセグメント(18)を含むマスクを形成するよう、明るいフィールド のレクティルを用いるための方法であって、前記方法は、 (a) 前記半導体基板(12)上に形成される前記材料の層(16)上に前 記フォトレジストからなる第1の層(18)を形成するステップと、 半導体基板上に形成される層の材料上に、フォトレジストからなる第1の層を 形成するステップと、 (b) 露光された領域(20)になるよう、前記フォトレジストの第1の層 (18)の部分上に光を向ける明るい領域と、露光されない領域(22)のまま 残るよう、前記フォトレジストの第1の層(18)の部分を露光しないようにす る暗い領域とを有する明るいフィールドのレクティルを介して光を透過すること により、前記フォトレジストの第1の層(18)を露光するステップとを含み、 前記露光されない領域(22)は、前記材料の層(16)に形成されることが意 図される前記開口部(28)の前記サイズ、前記形状および位置と実質的に同一 であるサイズ、形状および位置を有し、前記方法はさらに、 (c) 前記フォトレジストの第1の層(18)を現像し、それによって、前 記フォトレジストの第1の層(18)の前記露光された領域(20)を除去する ステップを含み、前記露光されない領域(22)はそのまま残り、それによって 、フォトレジストからなる前記パターニングされたセグメント(18)を形成し 、フォトレジストからなる各前記パターニングされたセグメント(18)は、前 記材料の層(16)に形成されることが意図される前記開口部(28)の前記サ イズ、前記形状および前記位置と実質的に同一なサイズ、形状および位置を有し 、前記方法はさらに、 (d) 前記材料の層(16)をエッチングし、それによって、その中におい て、エッチング中にマスクとして働くフォトレジストの前記パターニングされた セグメント(18)の各々の直下に段差(24)を形成するステップを含み、各 前記段差(24)は、前記材料の層(16)において形成されることが意図され る前記開口部(28)のうちの1つの前記サイズ、前記形状および前記位置と実 質的に同一なサイズ、形状および位置を有し、前記方法はさらに、 (e) 前記フォトレジストの第1の層(18)を除去するステップと、 (f) 前記材料の層(16)上に、平坦化可能な材料からなる層(26)を 堆積させるステップと、 (g) 前記平坦化可能な材料からなる層(26)の或る部分を除去し、それ によって、前記材料の層(16)において各前記段差(24)を露出させるステ ップと、 (h) 前記材料の層(16)ををエッチングしそれによってその中に前記開 口部(28)を形成するステップとを含み、前記平坦化可能な材料からなる層( 26)はエッチング中においてマスクとして働く、明るいフィールドのレクティ ルを用いるための方法。 2.前記平坦化可能な材料からなる層(26)の或る部分を除去するステップは エッチバックまたは研磨によって達成される、請求項1に記載の方法。 3.前記平坦化可能な材料からなる層(26)の或る部分を除去するステップに よって前記平坦化可能な材料からなる層(26)は平坦化される、請求項2に記 載の方法。 4.前記平坦化可能な材料からなる層(26)は、前記材料の層(16)をエッ チングしてその中に前記開口部(28)を形成した後に除去される、請求項1に 記載の方法。 5.前記材料の層(16)は、酸化物、窒化ホウ素およびポリイミドからなる材 料の群から選択される、請求項1に記載の方法。 6.前記平坦化可能な材料からなる層(26)は、フォトレジスト、ポリシリコ ン、ポリイミドおよび酸化物からなる材料の群から選択される、請求項1に記載 の方法。 7.前記平坦化可能な材料からなる層(26)は、フォトレジストからなる第2 の層(26)を含む、請求項6に記載の方法。 8.前記フォトレジストからなる第2の層(26)の或る部分を除去するステッ プはエッチバックによって達成される、請求項7に記載の方法。 9.前記開口部(28)の少なくとも1つは金属で充填される、請求項1に記載 の方法。 10.前記平坦化可能な材料からなる層(26)が前記材料の層(16)におい て各前記段差(24)を覆うよう、前記平坦化可能な材料からなる層(26)は ステップ(f)において前記材料の層(16)上に堆積される、請求項1に記載 の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/635,988 | 1996-04-22 | ||
US08/635,988 US5834159A (en) | 1996-04-22 | 1996-04-22 | Image reversal technique for forming small structures in integrated circuits |
PCT/US1997/000961 WO1997040526A1 (en) | 1996-04-22 | 1997-02-04 | An image reversal technique for forming small structures in integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000509555A true JP2000509555A (ja) | 2000-07-25 |
JP4169785B2 JP4169785B2 (ja) | 2008-10-22 |
Family
ID=24549941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53802997A Expired - Lifetime JP4169785B2 (ja) | 1996-04-22 | 1997-02-04 | 集積回路において小さな構造物を形成するための像反転技術 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5834159A (ja) |
EP (1) | EP0895656B1 (ja) |
JP (1) | JP4169785B2 (ja) |
KR (1) | KR100443064B1 (ja) |
DE (1) | DE69712478T2 (ja) |
WO (1) | WO1997040526A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10229153A (ja) * | 1997-02-13 | 1998-08-25 | Sumitomo Metal Mining Co Ltd | リードフレームの製造方法 |
US5922515A (en) * | 1998-02-27 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approaches to integrate the deep contact module |
DE19829152A1 (de) * | 1998-05-05 | 1999-11-18 | United Microelectronics Corp | Doppeltes Damaszierverfahren |
GB2340302B (en) * | 1998-07-29 | 2000-07-26 | United Microelectronics Corp | Method of manufacture using dual damascene process |
US6221777B1 (en) | 1999-06-09 | 2001-04-24 | Advanced Micro Devices, Inc. | Reverse lithographic process for semiconductor vias |
US6277544B1 (en) * | 1999-06-09 | 2001-08-21 | Advanced Micro Devices, Inc. | Reverse lithographic process for semiconductor spaces |
TW521316B (en) * | 2000-11-09 | 2003-02-21 | Macronix Int Co Ltd | Manufacturing method for reducing critical dimensions |
US6929961B2 (en) * | 2003-12-10 | 2005-08-16 | Hitachi Global Storage Technologies Netherlands B. V. | Dual function array feature for CMP process control and inspection |
US7268080B2 (en) * | 2005-11-09 | 2007-09-11 | Infineon Technologies Ag | Method for printing contacts on a substrate |
US7678704B2 (en) * | 2005-12-13 | 2010-03-16 | Infineon Technologies Ag | Method of making a contact in a semiconductor device |
US20080085600A1 (en) * | 2006-10-10 | 2008-04-10 | Toshiharu Furukawa | Method of forming lithographic and sub-lithographic dimensioned structures |
KR101918945B1 (ko) | 2017-01-17 | 2018-11-15 | 주식회사 동구전자 | 믹싱볼의 증기 배출 장치 |
KR101918946B1 (ko) | 2017-01-17 | 2018-11-15 | 주식회사 동구전자 | 자동판매기의 혼합장치 |
KR102370728B1 (ko) * | 2017-10-17 | 2022-03-07 | 에스케이하이닉스 주식회사 | 반도체 장치의 제조방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5238810A (en) * | 1986-09-22 | 1993-08-24 | Nippon Telegraph And Telephone Corporation | Laser magnetic immunoassay method and apparatus thereof |
US5091342A (en) * | 1989-02-24 | 1992-02-25 | Hewlett-Packard Company | Multilevel resist plated transfer layer process for fine line lithography |
EP0453644B1 (de) * | 1990-04-27 | 1995-05-10 | Siemens Aktiengesellschaft | Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern |
US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US5283208A (en) * | 1992-12-04 | 1994-02-01 | International Business Machines Corporation | Method of making a submicrometer local structure using an organic mandrel |
-
1996
- 1996-04-22 US US08/635,988 patent/US5834159A/en not_active Expired - Lifetime
-
1997
- 1997-02-04 KR KR10-1998-0708413A patent/KR100443064B1/ko not_active IP Right Cessation
- 1997-02-04 JP JP53802997A patent/JP4169785B2/ja not_active Expired - Lifetime
- 1997-02-04 WO PCT/US1997/000961 patent/WO1997040526A1/en active IP Right Grant
- 1997-02-04 DE DE69712478T patent/DE69712478T2/de not_active Expired - Lifetime
- 1997-02-04 EP EP97903893A patent/EP0895656B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR20000010559A (ko) | 2000-02-15 |
EP0895656A1 (en) | 1999-02-10 |
KR100443064B1 (ko) | 2004-09-18 |
US5834159A (en) | 1998-11-10 |
DE69712478T2 (de) | 2003-01-09 |
WO1997040526A1 (en) | 1997-10-30 |
EP0895656B1 (en) | 2002-05-08 |
DE69712478D1 (de) | 2002-06-13 |
JP4169785B2 (ja) | 2008-10-22 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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