JP2000340596A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JP2000340596A
JP2000340596A JP2000077830A JP2000077830A JP2000340596A JP 2000340596 A JP2000340596 A JP 2000340596A JP 2000077830 A JP2000077830 A JP 2000077830A JP 2000077830 A JP2000077830 A JP 2000077830A JP 2000340596 A JP2000340596 A JP 2000340596A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
wiring
plating
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000077830A
Other languages
English (en)
Other versions
JP4000745B2 (ja
Inventor
Yukihiro Maeda
幸宏 前田
Takashi Nagasaka
長坂　　崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2000077830A priority Critical patent/JP4000745B2/ja
Publication of JP2000340596A publication Critical patent/JP2000340596A/ja
Application granted granted Critical
Publication of JP4000745B2 publication Critical patent/JP4000745B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 基板に搭載された半導体チップと該基板の配
線部とをワイヤボンディングしてなる半導体装置の製造
方法において、ボンディング性を確保しつつ、半導体チ
ップ搭載工程前に配線部表面のプラズマクリーニングを
可能とする。 【解決手段】 一面１１上にタングステン配線が形成さ
れたメタライズ基板１０を用意し、Ｃｕめっき２０また
はＣｕ厚膜２１を施す（工程Ｓ１〜Ｓ３）。工程Ｓ４に
て、基板１０の一面１１に、プラズマ放電によって発生
するイオン粒子を衝突させることにより配線部２０、２
１の表面を清浄化し、この後、工程Ｓ５、Ｓ８にて、非
酸化性雰囲気で基板１０の一面１１に半導体チップ５０
を搭載し、続いて、工程Ｓ６にて半導体チップ５０と配
線部２０、２１とをワイヤボンディングにより電気的に
接続する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、基板に搭載された
半導体チップと該基板の配線部とをワイヤボンディング
してなる半導体装置の製造方法に関する。
【０００２】
【従来の技術】従来、この種の一般的な半導体装置の製
造方法を図４に示す。まず、図４（ａ）に示す様に、一
面上にＡｕフラッシュめっきよりなる配線部（ボンディ
ングランド）Ｊ１が形成されたプリント基板Ｊ２を用意
し（図４（ａ）中、Ｊ３はコンデンサ等の部品、Ｊ４は
半田）、図４（ｂ）に示す様に、プリント基板Ｊ２の一
面に半導体チップＪ５を導電性接着剤Ｊ６により接着し
搭載（ダイマウント）した後、図４（ｄ）に示す様に、
半導体チップＪ５と配線部Ｊ１とを、ＡｕやＡｌのワイ
ヤボンディングを行い、ワイヤＪ７で結線するようにし
ている。
【０００３】ここで、ボンディング工程直前に、図４
（ｃ）に示す様に、配線部Ｊ１であるＡｕフラッシュめ
っきの表面を、プラズマ装置を用いてプラズマ放電によ
って発生するイオン粒子を衝突させることにより清浄化
する、つまりプラズマクリーニングを行う方法が知られ
ている（特開平７−２８３１９９号公報、特開平８−１
１５９３６号公報、特開平８−１６２４３８号公報、特
開平１０−５０７５５号公報等）。
【０００４】プリント基板Ｊ２の場合、配線部Ｊ１には
Ｃｕめっき配線が用いられ、酸化防止のため最表面にＡ
ｕフラッシュめっきを施すようにしているが、ＣｕとＡ
ｕは相互拡散するため、間にＮｉめっきを挟む構造とし
ている。しかしながら、上述の半田付工程時あるいは半
導体チップのダイマウント工程時の熱履歴によって、Ｎ
ｉめっきがＡｕめっき上に析出し、ワイヤボンディング
性が低下してしまうため、ワイヤボンディング前にプラ
ズマクリーニングを行うようにしている。
【０００５】
【発明が解決しようとする課題】しかしながら、ボンデ
ィング工程直前でプラズマ中で配線部（ボンディングラ
ンド）Ｊ１表面をプラズマクリーニングする場合、半導
体チップＪ５も同様にプラズマ雰囲気中にある（プラズ
マ中性子にさらされる）ため、その半導体チップＪ５に
ダメージを与える可能性が高い。
【０００６】本発明は上記問題点に鑑み、半導体チップ
にプラズマクリーニングによるダメージを与えることな
く、ワイヤボンディング性を確保することのできる半導
体装置の製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】本発明は、導電性接着剤
の印刷、部品搭載、接着剤硬化、ワイヤボンディングの
一連の工程において、基板素材がプリント基板の場合、
配線のＡｕフラッシュめっきの下地であるＮｉが硬化時
に熱により表面に析出しボンディングを困難にしている
が、例えばセラミック基板のようなＣｕめっき配線で
は、めっきの下地が析出することはなく、半導体チップ
搭載前にプラズマクリーニングすることができるという
点に着目してなされたものである。
【０００８】即ち、請求項１記載の発明では、一面（１
１）上に配線部（２０、２１）が形成された基板（１
０）を用意し、該基板の一面に、プラズマ放電によって
発生するイオン粒子を衝突させることにより該配線部の
表面を清浄化した後、該基板の一面に半導体チップ（５
０）を搭載し、続いて該半導体チップと該配線部とをワ
イヤボンディングにより電気的に接続するようにしたこ
とを特徴としている。本発明によれば、ボンディング性
を確保しつつ、半導体チップ搭載工程（Ｓ５、Ｓ８）前
に配線部表面のプラズマクリーニングを可能とできる。
【０００９】また、請求項２記載の発明では、配線部
（２０、２１）をＣｕ（ＣｕめっきまたはＣｕ厚膜等）
またはＡｇ（Ａｇ厚膜）等により形成しているから、該
配線部表面をプラズマクリーニングした後、半導体チッ
プを搭載しても、従来のプリント基板のＡｕフラッシュ
めっき／Ｎｉめっき／Ｃｕめっき配線構造のように、チ
ップ搭載工程の熱履歴によって配線部の表面に析出物が
生じてその後のボンディング性を損なうことが無い。
【００１０】なお、上記各手段の括弧内の符号は、後述
する実施形態に記載の具体的手段との対応関係を示す一
例である。
【００１１】
【発明の実施の形態】以下、本発明を図に示す実施形態
について説明する。図１は本発明の実施形態に係る半導
体装置の製造方法を示す流れ図であり、図２及び図３
は、その製造方法の工程説明図である。図２及び図３
（ａ）は、最終的に図３（ｂ）に示すワイヤボンディン
グが施された半導体装置１００を製造する途中工程を示
している。以下、本実施形態について製造工程順に説明
していく。
【００１２】まず、基板用意工程Ｓ１では、図２（ａ）
に示す様に、一面に表層配線部を有するセラミック基板
又はプリント基板を用意する。セラミック基板として
は、例えば一面１１上にタングステン等の表層配線１２
が形成されたメタライズ基板（本発明でいう基板）１０
を用意する。プリント基板としては、例えば一面上にＣ
ｕめっき配線が施された配線基板１０を用意する。
【００１３】次に、Ｃｕめっき工程Ｓ２では、図２
（ｂ）に示す様に、メタライズ基板１０の一面１１に形
成された表層配線１２に、電気めっき法等によりＣｕめ
っきを施し、表層配線１２の表面をＣｕめっき層２０に
て被覆する。プリント基板の場合、Ｃｕめっき工程は省
くことができる。
【００１４】なお、図１に示す様に、Ｃｕめっき工程Ｓ
２の後に、Ｃｕ厚膜印刷工程Ｓ３を行っても良い。この
工程Ｓ３は、図２（ｃ）に示す様に、Ｃｕめっき層２０
の表面に印刷によって選択的にＣｕ厚膜２１を形成す
る。ここで、Ｃｕ厚膜印刷工程Ｓ３を行わない場合には
Ｃｕめっき層２０が、Ｃｕ厚膜印刷工程Ｓ３を行う場合
にはＣｕめっき層２０及びＣｕ厚膜２１が、各場合、本
発明でいうＣｕよりなる配線部に相当する。
【００１５】上記工程Ｓ２またはＳ３（配線部形成工
程）の後、プラズマクリーニング工程Ｓ４を行う。プラ
ズマクリーニング装置３０はチャンバ３１内に一対の電
極３２、３３を設け、一方の電極３２にメタライズ基板
１０の他面側を固定するようになっている。そして、例
えば、チャンバ３１内をアルゴンと水素の混合ガス雰囲
気として、一対の電極３２、３３間に電界を印加し（例
えば７５０Ｗ、２分間）、プラズマ放電によって発生す
るイオン粒子（Ａｒ+、Ｈ+等）を基板１０の一面１１に
衝突させ、配線部２０、２１の表面を清浄化する。
【００１６】この工程Ｓ４により、配線部２０、２１の
表面に初期的に存在する汚れ、酸化膜などを除去するこ
とができる。
【００１７】次に、全部品一括組付工程Ｓ５では、図３
（ａ）に示す様に、導電性接着剤４０を使用して、半導
体チップ５０およびコンデンサなどの部品６０を基板１
０の配線部２０、２１上に電気的に接続し搭載する。チ
ップ５０及び部品６０と接続されない配線部２０、２１
はワイヤボンディングのボンディングランドとなる。
【００１８】ここで、導電性接着剤４０は、樹脂中に、
Ａｇ、Ａｇ／Ｐｄ、Ａｇ／Ｐｔ、Ａｕ、Ｃｕ、Ｎｉ等を
フィラーとして混入し、これらの物理的接触によって導
電性を得るための接着剤である。導電性接着剤４０にブ
リード（導電性接着剤４０に含まれる樹脂中の成分が硬
化せずに外に流れ出す現象）の少ない材料を選べば、半
田のようにフラックスが基板上に流出することなく接続
することができるため、近傍にボンディングランドが存
在してもボンディング性を低下させることなく、部品を
接続することができる。
【００１９】また、導電性接着剤の硬化は、低酸素濃度
（１０ｐｐｍ以下）のＮ2雰囲気下で熱処理（例えば１
５０℃、１０分間）して硬化させれば、Ｃｕを用いた配
線部２０、２１であっても、全く酸化しないことが確認
されている。
【００２０】これらの工程Ｓ１〜Ｓ５を経た後、ワイヤ
ボンディング工程Ｓ６を行うことによって、図３（ｂ）
に示す様に、ＡｕあるいはＡｕ合金またはＡｌあるいは
Ａｌ合金のワイヤ７０によって半導体チップ５０と配線
部２０、２１とが電気的に接続された半導体装置１００
が出来上がる。
【００２１】なお、本実施形態においては、図１に示す
様に、Ｃｕめっき工程Ｓ２またはＣｕ厚膜印刷工程Ｓ３
の後に、半導体チップ以外の部品組付工程Ｓ７を行い、
その後、上記プラズマクリーニング工程Ｓ４を行い、次
に、半導体チップ組付工程Ｓ８を行って、上記ワイヤボ
ンディング工程Ｓ６を行っても良い（変形例）。
【００２２】即ち、この変形例においては、工程Ｓ２ま
たはＳ３の後に、半導体チップ以外の部品組付工程Ｓ７
にて、導電性接着剤４０を用いて半導体チップ５０以外
の部品６０を配線部２０、２１上に搭載し、その後、上
記プラズマクリーニング工程Ｓ４を行い、次に、半導体
チップ組付工程Ｓ８にて、導電性接着剤４０を用いて半
導体チップ５０を配線部２０、２１上に搭載し、続い
て、上記ワイヤボンディング工程Ｓ６を行う。ここで、
工程Ｓ７及びＳ８は、例えば、上記工程Ｓ５と同様の条
件（例えばＮ2雰囲気、１５０℃、１０分間）にて行う
ことができる。
【００２３】また、工程Ｓ７においてＣｕ配線部の表層
が酸化されたとしても、その後のプラズマクリーニング
工程Ｓ４で清浄化され、工程Ｓ８を上述の工程Ｓ５と同
様の条件で行えば問題はない。この変形例によっても、
図３（ｂ）に示す半導体装置１００が出来上がる。
【００２４】上記の製造方法においては、工程Ｓ１、Ｓ
２、Ｓ３が、本発明でいう「基板を用意する工程」に相
当し、工程Ｓ４が、本発明でいう「配線部の表面を清浄
化する工程」に相当し、工程Ｓ５、Ｓ８が、本発明でい
う「半導体チップを搭載する工程」に相当し、工程Ｓ６
が、本発明でいう「ワイヤボンディングにより電気的に
接続する工程」に相当する。
【００２５】ところで、上記製造方法によれば、ワイヤ
ボンディングのボンディングランドである配線部をＣｕ
（Ｃｕめっき層２０および／またはＣｕ厚膜２１）によ
り形成しているから、配線部２０、２１表面をプラズマ
クリーニングした後、半導体チップ５０を搭載しても、
従来のＡｕフラッシュめっきを用いたプリント基板のよ
うにＮｉめっきを必要とせず、チップ搭載工程Ｓ５、Ｓ
８の熱履歴によって配線部の表面に析出物が生じボンデ
ィング性を損なうことが無くなる。
【００２６】上述のメタライズ基板のように下地にタン
グステンを有していても、タングステンとＣｕは拡散し
にくいため、下地層（タングステン）の表層への析出は
ない。従って、良好なボンディング性を確保しつつ、半
導体チップ搭載工程前に配線部表面のプラズマクリーニ
ングを可能とでき、半導体チップ５０は、プラズマ雰囲
気にさらされることがないから、ダメージの懸念が無く
なる。
【００２７】また、本実施形態では、基板として、セラ
ミック基板又はプリント基板上にＣｕを配線材料として
使用したものを用い、Ｃｕの配線部２０、２１はめっ
き、厚膜印刷などの手法により形成している。従来のプ
リント基板上のＡｕフラッシュめっきでも厚く形成する
ことにより、Ｎｉめっきの析出を防ぐことはできるが、
大きなコストアップとなってしまう。ところが、Ｃｕ材
料を使用することにより、膜厚を厚く形成しても安く仕
上げることができるという利点を持つ。
【００２８】なお、基板１０の一面１１に形成された配
線部においては、少なくともワイヤボンディングされる
ものが、ＣｕめっきやＣｕ厚膜で構成されていればよ
く、部品６０を接続するものはＣｕで構成されていない
ものであってもよい。
【００２９】また、基板１０としては、セラミック基板
上にＡｇ厚膜、ガラスペーストを交互に印刷、焼成して
作成した配線基板を用いることもできる。この場合、表
層配線はＡｇ厚膜配線となる。この場合も、ボンディン
グ性を悪化させる要因となるＮｉめっきの使用がないた
め、半導体チップ搭載前にプラズマクリーニング工程を
実施することができ、良好なボンディング性を確保しつ
つ、半導体チップへのダメージの懸念を無くすことがで
きる。
【図面の簡単な説明】
【図１】本発明の実施形態に係る半導体装置の製造方法
を示す流れ図である。
【図２】上記実施形態に係る半導体装置の製造方法を説
明する工程説明図である。
【図３】図２に続く製造方法を説明する工程説明図であ
る。
【図４】従来の半導体装置の製造方法を説明する工程説
明図である。
【符号の説明】
１０…メタライズ基板、１１…メタライズ基板の一面、
２０…Ｃｕめっき層、２１…Ｃｕ厚膜、５０…半導体チ
ップ、Ｓ１…基板用意工程、Ｓ２…Ｃｕめっき工程、Ｓ
３…Ｃｕ厚膜印刷工程、Ｓ４…プラズマクリーニング工
程、Ｓ５…全部品一括組付工程、Ｓ６…ワイヤボンディ
ング工程、Ｓ８…半導体チップ組付工程。

Claims (3)

    【特許請求の範囲】
  1. 【請求項１】 一面（１１）上に配線部（２０、２１）
    が形成された基板（１０）を用意する工程（Ｓ１、Ｓ
    ２、Ｓ３）と、 前記基板の一面に、プラズマ放電によって発生するイオ
    ン粒子を衝突させることにより前記配線部の表面を清浄
    化する工程（Ｓ４）と、 この工程の後、前記基板の一面に半導体チップ（５０）
    を搭載する工程（Ｓ５、Ｓ８）と、 搭載された半導体チップと前記配線部とをワイヤボンデ
    ィングにより電気的に接続する工程（Ｓ６）と、を有す
    ることを特徴とする半導体装置の製造方法。
  2. 【請求項２】 前記配線部（２０、２１）をＣｕめっ
    き、Ｃｕ厚膜またはＡｇ厚膜により形成することを特徴
    とする請求項１に記載に半導体装置の製造方法。
  3. 【請求項３】 前記ワイヤボンディング工程（Ｓ６）
    は、ＡｕあるいはＡｕ合金またはＡｌあるいはＡｌ合金
    を用いて行うことを特徴とする請求項１または２に記載
    の半導体装置の製造方法。
JP2000077830A 1999-03-25 2000-03-15 半導体装置の製造方法 Expired - Fee Related JP4000745B2 (ja)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
JP2010010383A (ja) * 2008-06-26 2010-01-14 National Institute Of Advanced Industrial & Technology 半導体チップ電極接合方法
DE10222670B4 (de) * 2001-06-06 2011-07-21 DENSO CORPORATION, Aichi-pref. Elektrische Vorrichtung, welche eine Mehrzahl von Metallkontaktstellen besitzt,auf die eine Metallverdrahtung gebondet ist, und ein Herstellungsverfahren davon
US11024599B2 (en) 2018-12-05 2021-06-01 Renesas Electronics Corporation Semiconductor device and method of manufacturing thereof
KR102301223B1 (ko) * 2020-11-25 2021-09-09 박현배 대기압 플라즈마를 이용한 와이어 본딩 결합 구조체의 제조방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
DE10222670B4 (de) * 2001-06-06 2011-07-21 DENSO CORPORATION, Aichi-pref. Elektrische Vorrichtung, welche eine Mehrzahl von Metallkontaktstellen besitzt,auf die eine Metallverdrahtung gebondet ist, und ein Herstellungsverfahren davon
JP2010010383A (ja) * 2008-06-26 2010-01-14 National Institute Of Advanced Industrial & Technology 半導体チップ電極接合方法
US11024599B2 (en) 2018-12-05 2021-06-01 Renesas Electronics Corporation Semiconductor device and method of manufacturing thereof
KR102301223B1 (ko) * 2020-11-25 2021-09-09 박현배 대기압 플라즈마를 이용한 와이어 본딩 결합 구조체의 제조방법

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