JP2000339872A - Decode frame adjusting method, decode frame adjusting circuit and magnetic recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the decode timing adjustment in 1-7 decoder without outputting the erroneous decoding result. SOLUTION: When a request giving signal is made to be '1' by a request signal fetch circuit 22, the synchronizing pattern is once only detected from the upper 4 bits of a 9 bits shift register circuit 23 by a synchronizing pattern detecting circuit 24 to transmit the synchronizing pattern detecting signal to a decode frame producing circuit 25. By the decode frame producing circuit 25, the decode frame is extended by the required number conforming to the synchronizing pattern detecting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a magnetic recording apparatus. In particular, the present invention relates to a run-length limited code conversion decoding method used when writing and reading data in a magnetic recording device.

[0002]

2. Description of the Related Art Generally, when writing data to a magnetic recording apparatus, the data is encoded and recorded in a run-length limited (RLL) code. Therefore, when reading data recorded in the magnetic recording device, the data must be decoded (decoded) from the RLL code. At that time, it is necessary to adjust the decoding timing, that is, the decode frame.

[0003] Decoding frame adjustment at the time of decoding of a conventional RLL code will be described with reference to an example of a 1-7 code decoder which is a kind of RLL code. First, the input 1
-7 Gap pattern (GAP PATTER
When N) and the synchronization pattern (SYNC PATTERN) are detected successively, the 1-7 code data is decoded. However, the decoded frame at this time is not adjusted. Next, the timing of the decoded frame is adjusted based on the result of decoding the synchronization pattern. As a result, the adjusted decoding is executed at the correct timing.

[0004] The timing adjustment of a decoded frame will be described more specifically with reference to a 1-7 decoding table shown in FIG. When the synchronization pattern (001001... 001) is decoded without adjusting the timing of the decode frame, the synchronization pattern is decoded as a continuous one of (100), (001) and (010). According to FIG. 3, these are (* 001001), respectively.
It corresponds to (** 100 **) and (* 1001 **) (* is an arbitrary value). Therefore, N output after decoding
The RZ signals are (10), (11) and (00), respectively.
Becomes Therefore, the synchronization pattern is decoded and its N
If the RZ signal is determined, the correct timing of the decoded frame can be known.

[0005]

As described above, in the prior art, the input 1-7 code data is decoded without adjusting the timing at first, and the pattern of the decoding result is determined. The timing of decoding was adjusted. For this reason, the conventional decoding of 1-7 code data has a problem that a correct decoding result is not always output until the timing adjustment is completed.

In view of such a problem, the problem to be solved by the present invention is to provide a decoding frame adjustment method, a decoding frame adjustment circuit, and a magnetic recording apparatus having this circuit, which can obtain a correct decoding result immediately after the start of decoding. It is to provide.

[0007]

In order to solve such a problem, the present invention provides a decoding frame adjustment method, a decoding frame adjustment circuit, and a magnetic recording apparatus as described below.

A decoding frame adjustment method provided by the present invention is a method for adjusting a decoding frame when decoding encoded data encoded based on a run-length limited code conversion method. And a decoding frame adjustment step of adjusting a decoding frame based on the detected timing.

In the conventional method, there is a possibility that the result immediately after the start of decoding may be incorrect. However, in the decoding frame adjustment method of the present invention, the decoding frame is adjusted by the bit pattern of the data before decoding. Therefore, it is possible to eliminate the possibility that the decoding result is erroneous.

In the bit pattern detection step, for example, a bit pattern when the encoded data shifts from the gap pattern to the synchronization pattern is detected. As a specific example, in the process of shifting from the gap pattern (010101... 01) to the synchronization pattern (001001... 001), the bit pattern of (1001) from the last one bit of the gap pattern and the first three bits of the synchronization pattern is changed. As a result, it is possible to detect this and correctly adjust the decoding timing. In this example, a 4-bit bit pattern is detected. However, if a longer bit pattern is used, the influence of noise or the like can be reduced. In the decoding frame adjustment stage, for example, a decoding frame based on the detected timing is generated.

The run-length limited conversion system used in the present invention includes, for example, a 1-7 code conversion system.

A decode frame adjustment circuit provided by the present invention is a circuit for adjusting a decode frame used for decoding encoded data encoded based on a run-length limited code conversion method, wherein A decode frame adjustment circuit comprising: a bit pattern detection unit that detects a specific bit pattern; and a decode frame adjustment unit that adjusts a decode frame based on the timing at which the bit pattern detection unit detects the bit pattern. It is.

The bit pattern detecting means detects, for example, a bit pattern when coded data shifts from a gap pattern to a synchronous pattern. Further, the decode frame adjusting means generates a decode frame based on the timing at which the bit pattern detecting means detects the bit pattern.

A more specific configuration example of the decode frame adjustment circuit of the present invention is, in addition to the configuration described above, means for dividing an external clock supplied from the outside and generating an internal clock. Means for fetching and outputting a signal for requesting start of decoding from the outside in accordance with the internal clock, means for storing encoded data input from the outside, means for generating an enable signal from the internal clock, and decoding The apparatus further includes first capturing means for capturing and outputting the output of the external decoder in synchronization with the frame timing, and means for capturing and outputting the output of the first capturing means in accordance with the timing of the enable signal.

Further, the present invention provides a magnetic recording apparatus comprising the above-described decode frame adjusting circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A decode frame adjusting circuit 10 according to a first embodiment of the present invention will be described in detail with reference to the drawings.

1. Configuration of Decode Frame Adjustment Circuit 10 First, an outline of the configuration of the decode frame adjustment circuit 10 will be described.

Referring to FIG. 1, a decode frame adjustment circuit 10 includes an NRZ clock generation circuit 21, a request signal fetch circuit 22, a 9-bit shift register circuit 23, a synchronization pattern detection circuit 24, a decode frame generation circuit 25, and a primary An NRZ capture circuit 26, an NRZ enable generation circuit 27, and a secondary NRZ capture circuit 28 are provided. These circuits all operate in synchronization with a clock signal (hereinafter, referred to as a common clock) input from a 1-7 clock input line 13. The 1-7 code data input from the 1-7 code data input line 12 and the request signal input from the request signal input line 11 are input in synchronization with a common clock.

A 1-7 decoder 31 connected to the decode frame adjustment circuit 10 asynchronously decodes 7-bit 1-7 code data sent from the 9-bit shift register circuit 23 into a 2-bit NRZ signal. Next NRZ
It is sent to the capture circuit 26.

Next, each circuit constituting the decode frame adjustment circuit 10 will be described.

The NRZ clock generation circuit 21 outputs a signal obtained by dividing the common clock by three (hereinafter, this signal is referred to as an NRZ clock pulse). The NRZ clock pulse is output to three circuits: a request signal capturing circuit 22, a decode frame generating circuit 25, and an NRZ enable generating circuit 27. Further, the NRZ clock pulse is output from the HALF output line 41 to the outside through the inversion element. The output is used as a clock for NRZ data output from the OUT_NRZ output line 42 to the outside.

The request signal fetching circuit 22 calculates the NR
The Z clock pulse is used as a timing signal for capturing an input request signal. That is, when the NRZ clock pulse is “1”, the request signal capturing circuit 22 captures a request signal externally input to the request signal input line 11 and outputs a request notification signal. The request notification signal is output to the decode frame generation circuit 25 and the synchronization pattern detection circuit 24, and serves as a start signal of a decode frame adjustment sequence.

The 9-bit shift register circuit 23 has a 9-bit shift register, and takes in 9 pieces of 1-7 code data input from the outside to the 1-7 code data input line 12 in order. Top 4 of this 9-bit shift register
The bits are output to the synchronization pattern detection circuit 24 and used for detecting a synchronization pattern. On the other hand, the lower 7 bits are
The signal is output to the 1-7 decoder 31 and used for generating an NRZ signal.

When the request notification signal is "1", the synchronization pattern detection circuit 24 detects once that the output of the upper 4 bits of the 9-bit shift register circuit 23 is "1001", and detects the synchronization pattern. The signal is sent to the decode frame generation circuit 25. The decode frame generation circuit 25 uses the NRZ clock pulse as a decode frame generation timing signal.

When the request notification signal is "0", the decode frame generation circuit 25 takes the signal obtained by taking the NRZ clock pulse once into a D-type flip-flop (hereinafter, referred to as DFF) as a decode frame and outputs the signal as a primary NRZ signal. It is sent to the capture circuit 26. When the request notification signal is “1”, generation of a signal obtained by internally dividing the common clock by 3 is started (hereinafter, this signal is referred to as a generated frame), and the primary NRZ capture circuit 26 decodes the signal as a decoded frame. send. In addition, the synchronization pattern detection circuit 24
, The generated frame signal is extended by the required number there to match the timing of the correct decoded frame. The NRZ enable generation circuit 27 uses the NRZ clock pulse as an enable generation timing signal.

The NRZ enable generation circuit 27 generates the NRZ
A signal in which a clock pulse is captured once by a DFF (hereinafter, referred to as a DFF)
NRZ enable signal), and the NRZ enable signal is output to the secondary NRZ capture circuit 28.
It is used as an RZ signal fetch timing.

The primary NRZ fetch circuit 26 outputs the N output from the 1-7 decoder 31 in synchronization with the timing of the decode frame sent from the decode frame generation circuit 25.
The RZ signal is taken in, and the NRZ signal taken into the secondary NRZ taking circuit 27 is sent.

The secondary NRZ capture circuit 28 is adapted to match the timing of the NRZ enable signal sent from the NRZ enable generation circuit 27 with the primary NRZ capture circuit 2.
6 is taken in. Further, the fetched NRZ signal is output to the output OUT_NRZ41, and is output from the output OUT_NRZ41 to the outside as NRZ data.

2. Operation of Decode Frame Adjustment Circuit 10 Next, the operation of the decode frame adjustment circuit 10 will be described.
This will be described with reference to FIGS.

Normally, a 1-7 code data is followed by a gap pattern and a synchronization pattern before data to be actually written. In the present invention, decoding timing is adjusted by detecting the appearance of a synchronization pattern.

Referring to the 1-7 decoding table of FIG.
The −7 code data is converted into NRZ Z0 and Z1 with the data pattern of X2, X3, and X4 as the center in the input order. That is, in the 1-7 decoding, the NRZ signal (Z0, Z0,
It can be seen that Z1) is determined.

Here, the gap pattern (... 01010)
10101010101) and the synchronization pattern (0010
Let us consider the 1-7 code data of “01001001) divided into three. If the delimiter type is correct, it will be delimited as follows:

'101 010 101 010 10
1 ',' 001 001 001 001 'Converting this to an NRZ signal yields the following.

'10 00 10 00 10 ',' 0
0 00 00 00 'However, it is not always the case that the division is made correctly. In addition to the correct division, two incorrect divisions can occur.

First, there are cases where the division is made as follows.

'010 101 010 101 01
, 0 010 010 010 010 ′ When this is converted into an NRZ signal, the following is obtained.

'00 10 00 10 00 10
10 10 10 'Second, there are cases where the sections are divided as follows.

'010 101 010 101 01
0 1, 00 100 100 100 'When converted into an NRZ signal, the following is obtained.

'00 10 00 10 00 11
11 11 11 'In other words, it is correct to convert the synchronization pattern into a' 00 'and an NRZ signal as a continuation of' 001 '. On the other hand, when converting to '10' by separating from '010', or when converting to '11' by separating from '100',
Since the decode timing is incorrect, it is necessary to adjust the decode timing.

FIG. 2 shows the output of the 1-7 decoder 31 and the timing of the decode frame adjustment when the gap pattern and the synchronization pattern are continuously input. The signals are, in order from the top, 1-7 code data input from the 1-7 code data input line 12, the contents of the shift register of the 9-bit shift register circuit 23,
7 shows an NRZ signal output from the decoder 31 and an input request signal of the request signal input line 11. Next, a decode frame adjustment sequence (CASE) when 1-7 code data is input at the correct timing
The timing of each signal of 0) is shown. Below this, there is a decode frame adjustment sequence (CAS) when 1-7 code data is input at an incorrect timing.
The timing of each signal of E1) and (CASE 2) is shown.

(CASE 0) and (CASE 0) in FIG.
The operation timing of each signal in 1) and (CASE 2) will be described in order from the top.

The NRZ clock generation circuit 21 generates an NRZ clock obtained by dividing the common clock by three. NRZ
The clock is output from the HALF output line 41 to the outside as a clock of the NRZ data through the inversion element.

The NRZ enable generation circuit 27 generates the NRZ
An NRZ enable signal in which the clock is taken into the DFF once is generated.

The request signal fetch circuit 22 calculates the NR
At the timing when the Z clock is “1”, the input request signal of the request signal input line 11 is taken in, and a request notification signal is generated.

When the input request signal becomes "1" and the decode frame generating circuit 25 receives that the request notification signal is "1", the decode frame generating circuit 25 internally starts generating a generated frame (at this time, the generated frame is Becomes "1" at the third common clock after "1" becomes "1".)
The RZ clock is switched from a signal fetched once by the DFF to a generated frame and output.

The synchronization pattern detection circuit 24 detects that the upper 4 bits of the 9-bit shift register circuit 23 are "1001" only once after the request notification signal becomes "1", and outputs the synchronization pattern detection signal. Only one pulse '
1 '.

The decode frame generation circuit 25, which has received the fact that the synchronization pattern detection signal has become "1", extends the generated frame so that the third generated frame becomes "1" with the common clock (CASE). 0 means 0,
(CASE 1 extends one, CASE 2 extends two).

The primary NRZ capture circuit 26 captures the NRZ signal output from the 1-7 decoder 31 at the timing when the decode frame is "1", and outputs the primary NRZ signal.

The secondary NRZ capture circuit 28 captures the NRZ signal output from the primary NRZ capture circuit 26 at the timing when the NRZ enable signal is "1".
Outputs the Z signal. The secondary NRZ signal is output to the outside from the OUT_NRZ output line 42 as NRZ data.

In the decode frame generation circuit 25, the input request signal becomes “0” and the request notification signal becomes “0”.
When receiving that it has become 0 ', generation of the generated frame is stopped, and the decoded frame is converted from the generated frame to NRZ.
The clock is switched once to the signal captured by the DFF.

3. Second Embodiment Next, a second embodiment of the present invention will be described.

In the first embodiment, a 9-bit shift register circuit 23, that is, a 9-stage shift register is used. On the other hand, in the second embodiment, a shift register having a larger number of stages is used instead of the 9-bit shift register circuit 23. The other points are the same as in the first embodiment. By doing so, it is possible to prevent an erroneous decoding frame adjustment operation.

For example, a 9-bit shift register circuit 23
If the number of stages is increased to an 11-bit shift register circuit, and the synchronous pattern detection circuit 24 detects the upper 6 bits “001001” of the 11-bit shift register, data is more garbled due to noise or the like. It becomes a circuit that is strong against misdecode frame adjustment.

[0054]

According to the present invention, the decoding frame is adjusted using the encoded data (1-7 code data in the first embodiment) before decoding. Therefore, there is an effect that an erroneous decoding result is not output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the present invention.

FIG. 3 is a decoding table of a 1-7 decoder.

[Explanation of symbols]

 Reference Signs List 21 NRZ clock generation circuit 22 Request signal capture circuit 23 9-bit shift register circuit 24 Synchronous pattern detection circuit 25 Decode frame generation circuit 26 Primary NRZ capture circuit 27 NRZ enable generation circuit 28 Secondary NRZ capture circuit 31 1-7 decoder

Claims (9)

[Claims] 1. A method for adjusting a decoded frame when decoding encoded data encoded based on a run-length limited code conversion method, comprising: detecting a specific bit pattern from the encoded data; A decoding frame adjusting method, comprising: a detecting step; and a decoding frame adjusting step of adjusting a decoded frame based on the detected timing. 2. The decoding frame adjusting method according to claim 1, wherein said bit pattern detecting step detects a bit pattern when coded data shifts from a gap pattern to a synchronization pattern. Adjustment method. 3. The decoding frame adjustment method according to claim 1, wherein the decoding frame adjustment step is a step of generating a decoding frame based on the detected timing. Decoding frame adjustment method. 4. The decoding frame adjustment method according to claim 1, wherein said run-length limited conversion method is a 1-7 code conversion method. 5. A circuit for adjusting a decode frame used for decoding coded data coded based on a run-length limited code conversion method, comprising: detecting a specific bit pattern from the coded data. Means for adjusting a decode frame with reference to a timing at which the bit pattern detection means detects the bit pattern. 6. The decoding frame adjusting circuit according to claim 5, wherein said bit pattern detecting means detects a bit pattern when the coded data shifts from a gap pattern to a synchronization pattern. Adjustment circuit. 7. The decode frame adjustment circuit according to claim 5, wherein said decode frame adjustment means generates a decode frame based on a timing at which said bit pattern detection means detects said bit pattern. A decode frame adjustment circuit. 8. The decoding frame adjusting circuit according to claim 5, wherein: a means for dividing an external clock supplied from the outside to generate an internal clock; Means for receiving and outputting a signal for requesting the start of decoding from the CPU, means for storing encoded data input from the outside, means for generating an enable signal from an internal clock, and external means in accordance with the timing of the decode frame. Decoding frame adjustment, further comprising: first capturing means for capturing and outputting the output of the decoder, and means for capturing and outputting the output of the first capturing means in accordance with the timing of the enable signal. circuit. 9. A magnetic recording apparatus comprising the decode frame adjusting circuit according to claim 5.