JP2000332237A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2000332237A
JP2000332237A JP11135236A JP13523699A JP2000332237A JP 2000332237 A JP2000332237 A JP 2000332237A JP 11135236 A JP11135236 A JP 11135236A JP 13523699 A JP13523699 A JP 13523699A JP 2000332237 A JP2000332237 A JP 2000332237A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor substrate
main surface
channel region
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11135236A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000332237A5 (https=
Inventor
Tatsuya Kunikiyo
辰也 國清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11135236A priority Critical patent/JP2000332237A/ja
Priority to US09/441,889 priority patent/US6770550B2/en
Priority to KR1020000005066A priority patent/KR100315900B1/ko
Priority to TW089109798A priority patent/TW461114B/zh
Publication of JP2000332237A publication Critical patent/JP2000332237A/ja
Publication of JP2000332237A5 publication Critical patent/JP2000332237A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/664—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/224—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a cluster, e.g. using a gas cluster ion beam
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
JP11135236A 1999-05-17 1999-05-17 半導体装置の製造方法 Pending JP2000332237A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP11135236A JP2000332237A (ja) 1999-05-17 1999-05-17 半導体装置の製造方法
US09/441,889 US6770550B2 (en) 1999-05-17 1999-11-17 Semiconductor device manufacturing method
KR1020000005066A KR100315900B1 (ko) 1999-05-17 2000-02-02 반도체 장치의 제조 방법
TW089109798A TW461114B (en) 1999-05-17 2000-05-17 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11135236A JP2000332237A (ja) 1999-05-17 1999-05-17 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2000332237A true JP2000332237A (ja) 2000-11-30
JP2000332237A5 JP2000332237A5 (https=) 2006-06-15

Family

ID=15147005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11135236A Pending JP2000332237A (ja) 1999-05-17 1999-05-17 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US6770550B2 (https=)
JP (1) JP2000332237A (https=)
KR (1) KR100315900B1 (https=)
TW (1) TW461114B (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002208645A (ja) * 2001-01-09 2002-07-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
DE10240893A1 (de) * 2002-09-04 2004-03-18 Infineon Technologies Ag Verfahren zur Herstellung von SONOS-Speicherzellen, SONOS-Speicherzelle und Speicherzellenfeld
US7276775B2 (en) * 2001-02-27 2007-10-02 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process
JP2009290221A (ja) * 2007-02-06 2009-12-10 Sony Corp 絶縁ゲート電界効果トランジスタ及びその製造方法
US7977751B2 (en) 2007-02-06 2011-07-12 Sony Corporation Insulated gate field effect transistor and a method of manufacturing the same
JP2014072235A (ja) * 2012-09-27 2014-04-21 Seiko Instruments Inc 半導体集積回路装置
JP2024042761A (ja) * 2022-09-16 2024-03-29 キオクシア株式会社 半導体装置、および半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196581A (ja) * 2000-01-17 2001-07-19 Oki Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP4152598B2 (ja) * 2001-03-16 2008-09-17 スパンション エルエルシー 半導体装置の製造方法
JP2002313966A (ja) * 2001-04-16 2002-10-25 Yasuo Tarui トランジスタ型強誘電体不揮発性記憶素子とその製造方法
US6649460B2 (en) * 2001-10-25 2003-11-18 International Business Machines Corporation Fabricating a substantially self-aligned MOSFET
US7132698B2 (en) * 2002-01-25 2006-11-07 International Rectifier Corporation Compression assembled electronic package having a plastic molded insulation ring
US20050124127A1 (en) * 2003-12-04 2005-06-09 Tzu-En Ho Method for manufacturing gate structure for use in semiconductor device
TWI295085B (en) * 2003-12-05 2008-03-21 Int Rectifier Corp Field effect transistor with enhanced insulator structure
US7235431B2 (en) * 2004-09-02 2007-06-26 Micron Technology, Inc. Methods for packaging a plurality of semiconductor dice using a flowable dielectric material
KR100741467B1 (ko) * 2006-07-12 2007-07-20 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100734327B1 (ko) * 2006-07-18 2007-07-02 삼성전자주식회사 서로 다른 두께의 게이트 절연막들을 구비하는 반도체소자의 제조방법
US8021940B2 (en) * 2007-12-31 2011-09-20 Intel Corporation Methods for fabricating PMOS metal gate structures
KR101776955B1 (ko) * 2009-02-10 2017-09-08 소니 주식회사 고체 촬상 장치와 그 제조 방법, 및 전자 기기
JP2014216377A (ja) * 2013-04-23 2014-11-17 イビデン株式会社 電子部品とその製造方法及び多層プリント配線板の製造方法
CN110537251B (zh) * 2017-04-25 2023-07-04 三菱电机株式会社 半导体装置
KR102760046B1 (ko) * 2018-12-14 2025-01-24 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
US11387338B1 (en) * 2021-01-22 2022-07-12 Applied Materials, Inc. Methods for forming planar metal-oxide-semiconductor field-effect transistors

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US3979241A (en) 1968-12-28 1976-09-07 Fujitsu Ltd. Method of etching films of silicon nitride and silicon dioxide
JPH0669078B2 (ja) 1983-03-30 1994-08-31 株式会社東芝 半導体装置の製造方法
JPH0247838A (ja) 1988-08-10 1990-02-16 Nec Corp Ｍｏｓ型半導体装置の製造方法
US5591681A (en) * 1994-06-03 1997-01-07 Advanced Micro Devices, Inc. Method for achieving a highly reliable oxide film
US5480828A (en) * 1994-09-30 1996-01-02 Taiwan Semiconductor Manufacturing Corp. Ltd. Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process
US5478436A (en) 1994-12-27 1995-12-26 Motorola, Inc. Selective cleaning process for fabricating a semiconductor device
US5502009A (en) * 1995-02-16 1996-03-26 United Microelectronics Corp. Method for fabricating gate oxide layers of different thicknesses
US5985735A (en) * 1995-09-29 1999-11-16 Intel Corporation Trench isolation process using nitrogen preconditioning to reduce crystal defects
US6319804B1 (en) 1996-03-27 2001-11-20 Advanced Micro Devices, Inc. Process to separate the doping of polygate and source drain regions in dual gate field effect transistors
US5811347A (en) * 1996-04-29 1998-09-22 Advanced Micro Devices, Inc. Nitrogenated trench liner for improved shallow trench isolation
US5668035A (en) * 1996-06-10 1997-09-16 Taiwan Semiconductor Manufacturing Company Ltd. Method for fabricating a dual-gate dielectric module for memory with embedded logic technology
TW389944B (en) * 1997-03-17 2000-05-11 United Microelectronics Corp Method for forming gate oxide layers with different thickness
US5920779A (en) * 1997-05-21 1999-07-06 United Microelectronics Corp. Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits
US5963841A (en) 1997-08-01 1999-10-05 Advanced Micro Devices, Inc. Gate pattern formation using a bottom anti-reflective coating
US6080682A (en) * 1997-12-18 2000-06-27 Advanced Micro Devices, Inc. Methodology for achieving dual gate oxide thicknesses
US6033998A (en) * 1998-03-09 2000-03-07 Lsi Logic Corporation Method of forming variable thickness gate dielectrics
US6156620A (en) * 1998-07-22 2000-12-05 Lsi Logic Corporation Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
US6110780A (en) * 1999-04-01 2000-08-29 Taiwan Semiconductor Manufacturing Company Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory
US6063704A (en) 1999-08-02 2000-05-16 National Semiconductor Corporation Process for incorporating silicon oxynitride DARC layer into formation of silicide polysilicon contact
US6323106B1 (en) * 1999-09-02 2001-11-27 Lsi Logic Corporation Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002208645A (ja) * 2001-01-09 2002-07-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US7276775B2 (en) * 2001-02-27 2007-10-02 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process
DE10240893A1 (de) * 2002-09-04 2004-03-18 Infineon Technologies Ag Verfahren zur Herstellung von SONOS-Speicherzellen, SONOS-Speicherzelle und Speicherzellenfeld
US7323388B2 (en) 2002-09-04 2008-01-29 Infineon Technologies Ag SONOS memory cells and arrays and method of forming the same
JP2009290221A (ja) * 2007-02-06 2009-12-10 Sony Corp 絶縁ゲート電界効果トランジスタ及びその製造方法
US7977751B2 (en) 2007-02-06 2011-07-12 Sony Corporation Insulated gate field effect transistor and a method of manufacturing the same
JP2014072235A (ja) * 2012-09-27 2014-04-21 Seiko Instruments Inc 半導体集積回路装置
JP2024042761A (ja) * 2022-09-16 2024-03-29 キオクシア株式会社 半導体装置、および半導体装置の製造方法

Also Published As

Publication number Publication date
KR20000076591A (ko) 2000-12-26
KR100315900B1 (ko) 2001-12-12
US20020123212A1 (en) 2002-09-05
TW461114B (en) 2001-10-21
US6770550B2 (en) 2004-08-03

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